1 //===-- MSP430InstrInfo.h - MSP430 Instruction Information ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the MSP430 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_TARGET_MSP430INSTRINFO_H 15 #define LLVM_TARGET_MSP430INSTRINFO_H 16 17 #include "MSP430RegisterInfo.h" 18 #include "llvm/Target/TargetInstrInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #include "MSP430GenInstrInfo.inc" 22 23 namespace llvm { 24 25 class MSP430TargetMachine; 26 27 /// MSP430II - This namespace holds all of the target specific flags that 28 /// instruction info tracks. 29 /// 30 namespace MSP430II { 31 enum { 32 SizeShift = 2, 33 SizeMask = 7 << SizeShift, 34 35 SizeUnknown = 0 << SizeShift, 36 SizeSpecial = 1 << SizeShift, 37 Size2Bytes = 2 << SizeShift, 38 Size4Bytes = 3 << SizeShift, 39 Size6Bytes = 4 << SizeShift 40 }; 41 } 42 43 class MSP430InstrInfo : public MSP430GenInstrInfo { 44 const MSP430RegisterInfo RI; 45 public: 46 explicit MSP430InstrInfo(MSP430TargetMachine &TM); 47 48 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 49 /// such, whenever a client has an instance of instruction info, it should 50 /// always be able to get register info as well (through this method). 51 /// 52 virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } 53 54 void copyPhysReg(MachineBasicBlock &MBB, 55 MachineBasicBlock::iterator I, DebugLoc DL, 56 unsigned DestReg, unsigned SrcReg, 57 bool KillSrc) const; 58 59 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 60 MachineBasicBlock::iterator MI, 61 unsigned SrcReg, bool isKill, 62 int FrameIndex, 63 const TargetRegisterClass *RC, 64 const TargetRegisterInfo *TRI) const; 65 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 66 MachineBasicBlock::iterator MI, 67 unsigned DestReg, int FrameIdx, 68 const TargetRegisterClass *RC, 69 const TargetRegisterInfo *TRI) const; 70 71 unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 72 73 // Branch folding goodness 74 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 75 bool isUnpredicatedTerminator(const MachineInstr *MI) const; 76 bool AnalyzeBranch(MachineBasicBlock &MBB, 77 MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 78 SmallVectorImpl<MachineOperand> &Cond, 79 bool AllowModify) const; 80 81 unsigned RemoveBranch(MachineBasicBlock &MBB) const; 82 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 83 MachineBasicBlock *FBB, 84 const SmallVectorImpl<MachineOperand> &Cond, 85 DebugLoc DL) const; 86 87 }; 88 89 } 90 91 #endif 92
