1 //===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Declarations that describe the MIPS register file 12 //===----------------------------------------------------------------------===// 13 let Namespace = "Mips" in { 14 def sub_fpeven : SubRegIndex; 15 def sub_fpodd : SubRegIndex; 16 def sub_32 : SubRegIndex; 17 def sub_lo : SubRegIndex; 18 def sub_hi : SubRegIndex; 19 } 20 21 class Unallocatable { 22 bit isAllocatable = 0; 23 } 24 25 // We have banks of 32 registers each. 26 class MipsReg<bits<16> Enc, string n> : Register<n> { 27 let HWEncoding = Enc; 28 let Namespace = "Mips"; 29 } 30 31 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs> 32 : RegisterWithSubRegs<n, subregs> { 33 let HWEncoding = Enc; 34 let Namespace = "Mips"; 35 } 36 37 // Mips CPU Registers 38 class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>; 39 40 // Mips 64-bit CPU Registers 41 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs> 42 : MipsRegWithSubRegs<Enc, n, subregs> { 43 let SubRegIndices = [sub_32]; 44 } 45 46 // Mips 32-bit FPU Registers 47 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>; 48 49 // Mips 64-bit (aliased) FPU Registers 50 class AFPR<bits<16> Enc, string n, list<Register> subregs> 51 : MipsRegWithSubRegs<Enc, n, subregs> { 52 let SubRegIndices = [sub_fpeven, sub_fpodd]; 53 let CoveredBySubRegs = 1; 54 } 55 56 class AFPR64<bits<16> Enc, string n, list<Register> subregs> 57 : MipsRegWithSubRegs<Enc, n, subregs> { 58 let SubRegIndices = [sub_32]; 59 } 60 61 // Mips Hardware Registers 62 class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>; 63 64 //===----------------------------------------------------------------------===// 65 // Registers 66 //===----------------------------------------------------------------------===// 67 68 let Namespace = "Mips" in { 69 // General Purpose Registers 70 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 71 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; 72 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 73 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 74 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 75 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 76 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 77 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 78 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 79 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 80 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 81 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 82 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 83 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 84 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 85 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 86 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 87 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 88 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 89 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 90 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 91 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 92 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 93 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 94 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 95 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 96 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 97 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 98 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 99 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 100 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 101 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 102 103 // General Purpose 64-bit Registers 104 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 105 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; 106 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 107 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 108 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 109 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 110 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 111 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 112 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 113 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 114 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 115 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 116 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 117 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 118 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 119 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 120 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 121 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 122 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 123 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 124 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 125 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 126 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 127 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 128 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 129 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 130 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 131 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 132 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 133 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 134 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 135 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 136 137 /// Mips Single point precision FPU Registers 138 def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>; 139 def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>; 140 def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>; 141 def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>; 142 def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>; 143 def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>; 144 def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>; 145 def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>; 146 def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>; 147 def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>; 148 def F10 : FPR<10, "f10">, DwarfRegNum<[42]>; 149 def F11 : FPR<11, "f11">, DwarfRegNum<[43]>; 150 def F12 : FPR<12, "f12">, DwarfRegNum<[44]>; 151 def F13 : FPR<13, "f13">, DwarfRegNum<[45]>; 152 def F14 : FPR<14, "f14">, DwarfRegNum<[46]>; 153 def F15 : FPR<15, "f15">, DwarfRegNum<[47]>; 154 def F16 : FPR<16, "f16">, DwarfRegNum<[48]>; 155 def F17 : FPR<17, "f17">, DwarfRegNum<[49]>; 156 def F18 : FPR<18, "f18">, DwarfRegNum<[50]>; 157 def F19 : FPR<19, "f19">, DwarfRegNum<[51]>; 158 def F20 : FPR<20, "f20">, DwarfRegNum<[52]>; 159 def F21 : FPR<21, "f21">, DwarfRegNum<[53]>; 160 def F22 : FPR<22, "f22">, DwarfRegNum<[54]>; 161 def F23 : FPR<23, "f23">, DwarfRegNum<[55]>; 162 def F24 : FPR<24, "f24">, DwarfRegNum<[56]>; 163 def F25 : FPR<25, "f25">, DwarfRegNum<[57]>; 164 def F26 : FPR<26, "f26">, DwarfRegNum<[58]>; 165 def F27 : FPR<27, "f27">, DwarfRegNum<[59]>; 166 def F28 : FPR<28, "f28">, DwarfRegNum<[60]>; 167 def F29 : FPR<29, "f29">, DwarfRegNum<[61]>; 168 def F30 : FPR<30, "f30">, DwarfRegNum<[62]>; 169 def F31 : FPR<31, "f31">, DwarfRegNum<[63]>; 170 171 /// Mips Double point precision FPU Registers (aliased 172 /// with the single precision to hold 64 bit values) 173 def D0 : AFPR< 0, "f0", [F0, F1]>; 174 def D1 : AFPR< 2, "f2", [F2, F3]>; 175 def D2 : AFPR< 4, "f4", [F4, F5]>; 176 def D3 : AFPR< 6, "f6", [F6, F7]>; 177 def D4 : AFPR< 8, "f8", [F8, F9]>; 178 def D5 : AFPR<10, "f10", [F10, F11]>; 179 def D6 : AFPR<12, "f12", [F12, F13]>; 180 def D7 : AFPR<14, "f14", [F14, F15]>; 181 def D8 : AFPR<16, "f16", [F16, F17]>; 182 def D9 : AFPR<18, "f18", [F18, F19]>; 183 def D10 : AFPR<20, "f20", [F20, F21]>; 184 def D11 : AFPR<22, "f22", [F22, F23]>; 185 def D12 : AFPR<24, "f24", [F24, F25]>; 186 def D13 : AFPR<26, "f26", [F26, F27]>; 187 def D14 : AFPR<28, "f28", [F28, F29]>; 188 def D15 : AFPR<30, "f30", [F30, F31]>; 189 190 /// Mips Double point precision FPU Registers in MFP64 mode. 191 def D0_64 : AFPR64<0, "f0", [F0]>, DwarfRegNum<[32]>; 192 def D1_64 : AFPR64<1, "f1", [F1]>, DwarfRegNum<[33]>; 193 def D2_64 : AFPR64<2, "f2", [F2]>, DwarfRegNum<[34]>; 194 def D3_64 : AFPR64<3, "f3", [F3]>, DwarfRegNum<[35]>; 195 def D4_64 : AFPR64<4, "f4", [F4]>, DwarfRegNum<[36]>; 196 def D5_64 : AFPR64<5, "f5", [F5]>, DwarfRegNum<[37]>; 197 def D6_64 : AFPR64<6, "f6", [F6]>, DwarfRegNum<[38]>; 198 def D7_64 : AFPR64<7, "f7", [F7]>, DwarfRegNum<[39]>; 199 def D8_64 : AFPR64<8, "f8", [F8]>, DwarfRegNum<[40]>; 200 def D9_64 : AFPR64<9, "f9", [F9]>, DwarfRegNum<[41]>; 201 def D10_64 : AFPR64<10, "f10", [F10]>, DwarfRegNum<[42]>; 202 def D11_64 : AFPR64<11, "f11", [F11]>, DwarfRegNum<[43]>; 203 def D12_64 : AFPR64<12, "f12", [F12]>, DwarfRegNum<[44]>; 204 def D13_64 : AFPR64<13, "f13", [F13]>, DwarfRegNum<[45]>; 205 def D14_64 : AFPR64<14, "f14", [F14]>, DwarfRegNum<[46]>; 206 def D15_64 : AFPR64<15, "f15", [F15]>, DwarfRegNum<[47]>; 207 def D16_64 : AFPR64<16, "f16", [F16]>, DwarfRegNum<[48]>; 208 def D17_64 : AFPR64<17, "f17", [F17]>, DwarfRegNum<[49]>; 209 def D18_64 : AFPR64<18, "f18", [F18]>, DwarfRegNum<[50]>; 210 def D19_64 : AFPR64<19, "f19", [F19]>, DwarfRegNum<[51]>; 211 def D20_64 : AFPR64<20, "f20", [F20]>, DwarfRegNum<[52]>; 212 def D21_64 : AFPR64<21, "f21", [F21]>, DwarfRegNum<[53]>; 213 def D22_64 : AFPR64<22, "f22", [F22]>, DwarfRegNum<[54]>; 214 def D23_64 : AFPR64<23, "f23", [F23]>, DwarfRegNum<[55]>; 215 def D24_64 : AFPR64<24, "f24", [F24]>, DwarfRegNum<[56]>; 216 def D25_64 : AFPR64<25, "f25", [F25]>, DwarfRegNum<[57]>; 217 def D26_64 : AFPR64<26, "f26", [F26]>, DwarfRegNum<[58]>; 218 def D27_64 : AFPR64<27, "f27", [F27]>, DwarfRegNum<[59]>; 219 def D28_64 : AFPR64<28, "f28", [F28]>, DwarfRegNum<[60]>; 220 def D29_64 : AFPR64<29, "f29", [F29]>, DwarfRegNum<[61]>; 221 def D30_64 : AFPR64<30, "f30", [F30]>, DwarfRegNum<[62]>; 222 def D31_64 : AFPR64<31, "f31", [F31]>, DwarfRegNum<[63]>; 223 224 // Hi/Lo registers 225 def HI : Register<"hi">, DwarfRegNum<[64]>; 226 def LO : Register<"lo">, DwarfRegNum<[65]>; 227 228 let SubRegIndices = [sub_32] in { 229 def HI64 : RegisterWithSubRegs<"hi", [HI]>; 230 def LO64 : RegisterWithSubRegs<"lo", [LO]>; 231 } 232 233 // Status flags register 234 def FCR31 : Register<"31">; 235 236 // fcc0 register 237 def FCC0 : MipsReg<0, "fcc0">; 238 239 // PC register 240 def PC : Register<"pc">; 241 242 // Hardware register $29 243 def HWR29 : MipsReg<29, "29">; 244 def HWR29_64 : MipsReg<29, "29">; 245 246 // Accum registers 247 let SubRegIndices = [sub_lo, sub_hi] in 248 def AC0 : MipsRegWithSubRegs<0, "ac0", [LO, HI]>; 249 def AC1 : MipsReg<1, "ac1">; 250 def AC2 : MipsReg<2, "ac2">; 251 def AC3 : MipsReg<3, "ac3">; 252 253 def DSPCtrl : Register<"dspctrl">; 254 } 255 256 //===----------------------------------------------------------------------===// 257 // Register Classes 258 //===----------------------------------------------------------------------===// 259 260 class CPURegsClass<list<ValueType> regTypes> : 261 RegisterClass<"Mips", regTypes, 32, (add 262 // Reserved 263 ZERO, AT, 264 // Return Values and Arguments 265 V0, V1, A0, A1, A2, A3, 266 // Not preserved across procedure calls 267 T0, T1, T2, T3, T4, T5, T6, T7, 268 // Callee save 269 S0, S1, S2, S3, S4, S5, S6, S7, 270 // Not preserved across procedure calls 271 T8, T9, 272 // Reserved 273 K0, K1, GP, SP, FP, RA)>; 274 275 def CPURegs : CPURegsClass<[i32]>; 276 def DSPRegs : CPURegsClass<[v4i8, v2i16]>; 277 278 def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add 279 // Reserved 280 ZERO_64, AT_64, 281 // Return Values and Arguments 282 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 283 // Not preserved across procedure calls 284 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 285 // Callee save 286 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 287 // Not preserved across procedure calls 288 T8_64, T9_64, 289 // Reserved 290 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 291 292 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 293 // Return Values and Arguments 294 V0, V1, A0, A1, A2, A3, 295 // Callee save 296 S0, S1)>; 297 298 def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable; 299 300 def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; 301 302 // 64bit fp: 303 // * FGR64 - 32 64-bit registers 304 // * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 305 // 306 // 32bit fp: 307 // * FGR32 - 16 32-bit even registers 308 // * FGR32 - 32 32-bit registers (single float only mode) 309 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 310 311 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add 312 // Return Values and Arguments 313 D0, D1, 314 // Not preserved across procedure calls 315 D2, D3, D4, D5, 316 // Return Values and Arguments 317 D6, D7, 318 // Not preserved across procedure calls 319 D8, D9, 320 // Callee save 321 D10, D11, D12, D13, D14, D15)>; 322 323 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 324 325 // Condition Register for floating point operations 326 def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>, Unallocatable; 327 328 // Hi/Lo Registers 329 def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>, Unallocatable; 330 def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)>, Unallocatable; 331 332 // Hardware registers 333 def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable; 334 def HWRegs64 : RegisterClass<"Mips", [i64], 64, (add HWR29_64)>, Unallocatable; 335 336 // Accumulator Registers 337 def ACRegs : RegisterClass<"Mips", [i64], 64, (sequence "AC%u", 0, 3)>, 338 Unallocatable; 339 340 def CPURegsAsmOperand : AsmOperandClass { 341 let Name = "CPURegsAsm"; 342 let ParserMethod = "parseCPURegs"; 343 } 344 345 def CPU64RegsAsmOperand : AsmOperandClass { 346 let Name = "CPU64RegsAsm"; 347 let ParserMethod = "parseCPU64Regs"; 348 } 349 350 def CCRAsmOperand : AsmOperandClass { 351 let Name = "CCRAsm"; 352 let ParserMethod = "parseCCRRegs"; 353 } 354 355 def CPURegsOpnd : RegisterOperand<CPURegs, "printCPURegs"> { 356 let ParserMatchClass = CPURegsAsmOperand; 357 } 358 359 def CPU64RegsOpnd : RegisterOperand<CPU64Regs, "printCPURegs"> { 360 let ParserMatchClass = CPU64RegsAsmOperand; 361 } 362 363 def CCROpnd : RegisterOperand<CCR, "printCPURegs"> { 364 let ParserMatchClass = CCRAsmOperand; 365 } 366 367 def HWRegsAsmOperand : AsmOperandClass { 368 let Name = "HWRegsAsm"; 369 let ParserMethod = "parseHWRegs"; 370 } 371 372 def HW64RegsAsmOperand : AsmOperandClass { 373 let Name = "HW64RegsAsm"; 374 let ParserMethod = "parseHW64Regs"; 375 } 376 377 def HWRegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> { 378 let ParserMatchClass = HWRegsAsmOperand; 379 } 380 381 def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> { 382 let ParserMatchClass = HW64RegsAsmOperand; 383 } 384
