1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // 12 // PowerPC instruction formats 13 14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 18 bit PPC64 = 0; // Default value, override with isPPC64 19 20 let Namespace = "PPC"; 21 let Inst{0-5} = opcode; 22 let OutOperandList = OOL; 23 let InOperandList = IOL; 24 let AsmString = asmstr; 25 let Itinerary = itin; 26 27 bits<1> PPC970_First = 0; 28 bits<1> PPC970_Single = 0; 29 bits<1> PPC970_Cracked = 0; 30 bits<3> PPC970_Unit = 0; 31 32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 33 /// these must be reflected there! See comments there for what these are. 34 let TSFlags{0} = PPC970_First; 35 let TSFlags{1} = PPC970_Single; 36 let TSFlags{2} = PPC970_Cracked; 37 let TSFlags{5-3} = PPC970_Unit; 38 } 39 40 class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 41 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 42 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 43 class PPC970_MicroCode; 44 45 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 46 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 47 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 48 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 49 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 50 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 51 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 52 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 53 54 // Two joined instructions; used to emit two adjacent instructions as one. 55 // The itinerary from the first instruction is used for scheduling and 56 // classification. 57 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 58 InstrItinClass itin> 59 : Instruction { 60 field bits<64> Inst; 61 62 bit PPC64 = 0; // Default value, override with isPPC64 63 64 let Namespace = "PPC"; 65 let Inst{0-5} = opcode1; 66 let Inst{32-37} = opcode2; 67 let OutOperandList = OOL; 68 let InOperandList = IOL; 69 let AsmString = asmstr; 70 let Itinerary = itin; 71 72 bits<1> PPC970_First = 0; 73 bits<1> PPC970_Single = 0; 74 bits<1> PPC970_Cracked = 0; 75 bits<3> PPC970_Unit = 0; 76 77 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 78 /// these must be reflected there! See comments there for what these are. 79 let TSFlags{0} = PPC970_First; 80 let TSFlags{1} = PPC970_Single; 81 let TSFlags{2} = PPC970_Cracked; 82 let TSFlags{5-3} = PPC970_Unit; 83 } 84 85 // 1.7.1 I-Form 86 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 87 InstrItinClass itin, list<dag> pattern> 88 : I<opcode, OOL, IOL, asmstr, itin> { 89 let Pattern = pattern; 90 bits<24> LI; 91 92 let Inst{6-29} = LI; 93 let Inst{30} = aa; 94 let Inst{31} = lk; 95 } 96 97 // 1.7.2 B-Form 98 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 99 : I<opcode, OOL, IOL, asmstr, BrB> { 100 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 101 bits<3> CR; 102 bits<14> BD; 103 104 bits<5> BI; 105 let BI{0-1} = BIBO{5-6}; 106 let BI{2-4} = CR{0-2}; 107 108 let Inst{6-10} = BIBO{4-0}; 109 let Inst{11-15} = BI; 110 let Inst{16-29} = BD; 111 let Inst{30} = aa; 112 let Inst{31} = lk; 113 } 114 115 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 116 string asmstr> 117 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 118 let BIBO{4-0} = bo; 119 let BIBO{6-5} = 0; 120 let CR = 0; 121 } 122 123 // 1.7.4 D-Form 124 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 125 InstrItinClass itin, list<dag> pattern> 126 : I<opcode, OOL, IOL, asmstr, itin> { 127 bits<5> A; 128 bits<5> B; 129 bits<16> C; 130 131 let Pattern = pattern; 132 133 let Inst{6-10} = A; 134 let Inst{11-15} = B; 135 let Inst{16-31} = C; 136 } 137 138 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 139 InstrItinClass itin, list<dag> pattern> 140 : I<opcode, OOL, IOL, asmstr, itin> { 141 bits<5> A; 142 bits<21> Addr; 143 144 let Pattern = pattern; 145 146 let Inst{6-10} = A; 147 let Inst{11-15} = Addr{20-16}; // Base Reg 148 let Inst{16-31} = Addr{15-0}; // Displacement 149 } 150 151 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 152 InstrItinClass itin, list<dag> pattern> 153 : I<opcode, OOL, IOL, asmstr, itin> { 154 bits<5> A; 155 bits<16> C; 156 bits<5> B; 157 158 let Pattern = pattern; 159 160 let Inst{6-10} = A; 161 let Inst{11-15} = B; 162 let Inst{16-31} = C; 163 } 164 165 166 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 167 InstrItinClass itin, list<dag> pattern> 168 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>; 169 170 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 171 InstrItinClass itin, list<dag> pattern> 172 : I<opcode, OOL, IOL, asmstr, itin> { 173 bits<5> A; 174 bits<16> B; 175 176 let Pattern = pattern; 177 178 let Inst{6-10} = A; 179 let Inst{11-15} = 0; 180 let Inst{16-31} = B; 181 } 182 183 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 184 InstrItinClass itin, list<dag> pattern> 185 : I<opcode, OOL, IOL, asmstr, itin> { 186 bits<5> B; 187 bits<5> A; 188 bits<16> C; 189 190 let Pattern = pattern; 191 192 let Inst{6-10} = A; 193 let Inst{11-15} = B; 194 let Inst{16-31} = C; 195 } 196 197 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 198 InstrItinClass itin, list<dag> pattern> 199 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 200 let A = 0; 201 let Addr = 0; 202 } 203 204 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 205 dag OOL, dag IOL, string asmstr, 206 InstrItinClass itin, list<dag> pattern> 207 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 208 bits<5> A; 209 bits<21> Addr; 210 211 let Pattern = pattern; 212 bits<24> LI; 213 214 let Inst{6-29} = LI; 215 let Inst{30} = aa; 216 let Inst{31} = lk; 217 218 let Inst{38-42} = A; 219 let Inst{43-47} = Addr{20-16}; // Base Reg 220 let Inst{48-63} = Addr{15-0}; // Displacement 221 } 222 223 // This is used to emit BL8+NOP. 224 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 225 dag OOL, dag IOL, string asmstr, 226 InstrItinClass itin, list<dag> pattern> 227 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 228 OOL, IOL, asmstr, itin, pattern> { 229 let A = 0; 230 let Addr = 0; 231 } 232 233 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 234 InstrItinClass itin> 235 : I<opcode, OOL, IOL, asmstr, itin> { 236 bits<3> BF; 237 bits<1> L; 238 bits<5> RA; 239 bits<16> I; 240 241 let Inst{6-8} = BF; 242 let Inst{9} = 0; 243 let Inst{10} = L; 244 let Inst{11-15} = RA; 245 let Inst{16-31} = I; 246 } 247 248 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 249 InstrItinClass itin> 250 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 251 let L = PPC64; 252 } 253 254 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 255 InstrItinClass itin> 256 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 257 258 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 259 InstrItinClass itin> 260 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 261 let L = PPC64; 262 } 263 264 265 // 1.7.5 DS-Form 266 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 267 InstrItinClass itin, list<dag> pattern> 268 : I<opcode, OOL, IOL, asmstr, itin> { 269 bits<5> RST; 270 bits<19> DS_RA; 271 272 let Pattern = pattern; 273 274 let Inst{6-10} = RST; 275 let Inst{11-15} = DS_RA{18-14}; // Register # 276 let Inst{16-29} = DS_RA{13-0}; // Displacement. 277 let Inst{30-31} = xo; 278 } 279 280 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 281 InstrItinClass itin, list<dag> pattern> 282 : I<opcode, OOL, IOL, asmstr, itin> { 283 bits<5> RST; 284 bits<14> DS; 285 bits<5> RA; 286 287 let Pattern = pattern; 288 289 let Inst{6-10} = RST; 290 let Inst{11-15} = RA; 291 let Inst{16-29} = DS; 292 let Inst{30-31} = xo; 293 } 294 295 // 1.7.6 X-Form 296 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 297 InstrItinClass itin, list<dag> pattern> 298 : I<opcode, OOL, IOL, asmstr, itin> { 299 bits<5> RST; 300 bits<5> A; 301 bits<5> B; 302 303 let Pattern = pattern; 304 305 bit RC = 0; // set by isDOT 306 307 let Inst{6-10} = RST; 308 let Inst{11-15} = A; 309 let Inst{16-20} = B; 310 let Inst{21-30} = xo; 311 let Inst{31} = RC; 312 } 313 314 // This is the same as XForm_base_r3xo, but the first two operands are swapped 315 // when code is emitted. 316 class XForm_base_r3xo_swapped 317 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 318 InstrItinClass itin> 319 : I<opcode, OOL, IOL, asmstr, itin> { 320 bits<5> A; 321 bits<5> RST; 322 bits<5> B; 323 324 bit RC = 0; // set by isDOT 325 326 let Inst{6-10} = RST; 327 let Inst{11-15} = A; 328 let Inst{16-20} = B; 329 let Inst{21-30} = xo; 330 let Inst{31} = RC; 331 } 332 333 334 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 335 InstrItinClass itin, list<dag> pattern> 336 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 337 338 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 339 InstrItinClass itin, list<dag> pattern> 340 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 341 let Pattern = pattern; 342 } 343 344 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 345 InstrItinClass itin, list<dag> pattern> 346 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 347 348 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 349 InstrItinClass itin, list<dag> pattern> 350 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 351 let Pattern = pattern; 352 } 353 354 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 355 InstrItinClass itin, list<dag> pattern> 356 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 357 let B = 0; 358 let Pattern = pattern; 359 } 360 361 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 362 InstrItinClass itin> 363 : I<opcode, OOL, IOL, asmstr, itin> { 364 bits<3> BF; 365 bits<1> L; 366 bits<5> RA; 367 bits<5> RB; 368 369 let Inst{6-8} = BF; 370 let Inst{9} = 0; 371 let Inst{10} = L; 372 let Inst{11-15} = RA; 373 let Inst{16-20} = RB; 374 let Inst{21-30} = xo; 375 let Inst{31} = 0; 376 } 377 378 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 379 InstrItinClass itin> 380 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 381 let L = PPC64; 382 } 383 384 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 385 InstrItinClass itin> 386 : I<opcode, OOL, IOL, asmstr, itin> { 387 bits<3> BF; 388 bits<5> FRA; 389 bits<5> FRB; 390 391 let Inst{6-8} = BF; 392 let Inst{9-10} = 0; 393 let Inst{11-15} = FRA; 394 let Inst{16-20} = FRB; 395 let Inst{21-30} = xo; 396 let Inst{31} = 0; 397 } 398 399 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 400 InstrItinClass itin, list<dag> pattern> 401 : I<opcode, OOL, IOL, asmstr, itin> { 402 let Pattern = pattern; 403 let Inst{6-10} = 31; 404 let Inst{11-15} = 0; 405 let Inst{16-20} = 0; 406 let Inst{21-30} = xo; 407 let Inst{31} = 0; 408 } 409 410 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 411 string asmstr, InstrItinClass itin, list<dag> pattern> 412 : I<opcode, OOL, IOL, asmstr, itin> { 413 let Pattern = pattern; 414 let Inst{6-10} = 0; 415 let Inst{11-15} = 0; 416 let Inst{16-20} = 0; 417 let Inst{21-30} = xo; 418 let Inst{31} = 0; 419 } 420 421 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 422 InstrItinClass itin, list<dag> pattern> 423 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 424 } 425 426 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 427 InstrItinClass itin, list<dag> pattern> 428 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 429 let A = 0; 430 } 431 432 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 433 InstrItinClass itin, list<dag> pattern> 434 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 435 } 436 437 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 438 // numbers presumably relates to some document, but I haven't found it. 439 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 440 InstrItinClass itin, list<dag> pattern> 441 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 442 let Pattern = pattern; 443 444 bit RC = 0; // set by isDOT 445 446 let Inst{6-10} = RST; 447 let Inst{11-20} = 0; 448 let Inst{21-30} = xo; 449 let Inst{31} = RC; 450 } 451 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 452 InstrItinClass itin, list<dag> pattern> 453 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 454 let Pattern = pattern; 455 bits<5> FM; 456 457 bit RC = 0; // set by isDOT 458 459 let Inst{6-10} = FM; 460 let Inst{11-20} = 0; 461 let Inst{21-30} = xo; 462 let Inst{31} = RC; 463 } 464 465 // DCB_Form - Form X instruction, used for dcb* instructions. 466 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 467 InstrItinClass itin, list<dag> pattern> 468 : I<31, OOL, IOL, asmstr, itin> { 469 bits<5> A; 470 bits<5> B; 471 472 let Pattern = pattern; 473 474 let Inst{6-10} = immfield; 475 let Inst{11-15} = A; 476 let Inst{16-20} = B; 477 let Inst{21-30} = xo; 478 let Inst{31} = 0; 479 } 480 481 482 // DSS_Form - Form X instruction, used for altivec dss* instructions. 483 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr, 484 InstrItinClass itin, list<dag> pattern> 485 : I<31, OOL, IOL, asmstr, itin> { 486 bits<1> T; 487 bits<2> STRM; 488 bits<5> A; 489 bits<5> B; 490 491 let Pattern = pattern; 492 493 let Inst{6} = T; 494 let Inst{7-8} = 0; 495 let Inst{9-10} = STRM; 496 let Inst{11-15} = A; 497 let Inst{16-20} = B; 498 let Inst{21-30} = xo; 499 let Inst{31} = 0; 500 } 501 502 // 1.7.7 XL-Form 503 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 504 InstrItinClass itin, list<dag> pattern> 505 : I<opcode, OOL, IOL, asmstr, itin> { 506 bits<5> CRD; 507 bits<5> CRA; 508 bits<5> CRB; 509 510 let Pattern = pattern; 511 512 let Inst{6-10} = CRD; 513 let Inst{11-15} = CRA; 514 let Inst{16-20} = CRB; 515 let Inst{21-30} = xo; 516 let Inst{31} = 0; 517 } 518 519 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 520 InstrItinClass itin, list<dag> pattern> 521 : I<opcode, OOL, IOL, asmstr, itin> { 522 bits<5> CRD; 523 524 let Pattern = pattern; 525 526 let Inst{6-10} = CRD; 527 let Inst{11-15} = CRD; 528 let Inst{16-20} = CRD; 529 let Inst{21-30} = xo; 530 let Inst{31} = 0; 531 } 532 533 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 534 InstrItinClass itin, list<dag> pattern> 535 : I<opcode, OOL, IOL, asmstr, itin> { 536 bits<5> BO; 537 bits<5> BI; 538 bits<2> BH; 539 540 let Pattern = pattern; 541 542 let Inst{6-10} = BO; 543 let Inst{11-15} = BI; 544 let Inst{16-18} = 0; 545 let Inst{19-20} = BH; 546 let Inst{21-30} = xo; 547 let Inst{31} = lk; 548 } 549 550 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 551 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 552 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 553 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 554 bits<3> CR; 555 556 let BO = BIBO{2-6}; 557 let BI{0-1} = BIBO{0-1}; 558 let BI{2-4} = CR; 559 let BH = 0; 560 } 561 562 563 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 564 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 565 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 566 let BO = bo; 567 let BI = bi; 568 let BH = 0; 569 } 570 571 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 572 InstrItinClass itin> 573 : I<opcode, OOL, IOL, asmstr, itin> { 574 bits<3> BF; 575 bits<3> BFA; 576 577 let Inst{6-8} = BF; 578 let Inst{9-10} = 0; 579 let Inst{11-13} = BFA; 580 let Inst{14-15} = 0; 581 let Inst{16-20} = 0; 582 let Inst{21-30} = xo; 583 let Inst{31} = 0; 584 } 585 586 // 1.7.8 XFX-Form 587 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 588 InstrItinClass itin> 589 : I<opcode, OOL, IOL, asmstr, itin> { 590 bits<5> RT; 591 bits<10> SPR; 592 593 let Inst{6-10} = RT; 594 let Inst{11} = SPR{4}; 595 let Inst{12} = SPR{3}; 596 let Inst{13} = SPR{2}; 597 let Inst{14} = SPR{1}; 598 let Inst{15} = SPR{0}; 599 let Inst{16} = SPR{9}; 600 let Inst{17} = SPR{8}; 601 let Inst{18} = SPR{7}; 602 let Inst{19} = SPR{6}; 603 let Inst{20} = SPR{5}; 604 let Inst{21-30} = xo; 605 let Inst{31} = 0; 606 } 607 608 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 609 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 610 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 611 let SPR = spr; 612 } 613 614 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 615 InstrItinClass itin> 616 : I<opcode, OOL, IOL, asmstr, itin> { 617 bits<5> RT; 618 619 let Inst{6-10} = RT; 620 let Inst{11-20} = 0; 621 let Inst{21-30} = xo; 622 let Inst{31} = 0; 623 } 624 625 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 626 InstrItinClass itin> 627 : I<opcode, OOL, IOL, asmstr, itin> { 628 bits<8> FXM; 629 bits<5> rS; 630 631 let Inst{6-10} = rS; 632 let Inst{11} = 0; 633 let Inst{12-19} = FXM; 634 let Inst{20} = 0; 635 let Inst{21-30} = xo; 636 let Inst{31} = 0; 637 } 638 639 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 640 InstrItinClass itin> 641 : I<opcode, OOL, IOL, asmstr, itin> { 642 bits<5> ST; 643 bits<8> FXM; 644 645 let Inst{6-10} = ST; 646 let Inst{11} = 1; 647 let Inst{12-19} = FXM; 648 let Inst{20} = 0; 649 let Inst{21-30} = xo; 650 let Inst{31} = 0; 651 } 652 653 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 654 InstrItinClass itin> 655 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 656 657 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 658 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 659 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 660 let SPR = spr; 661 } 662 663 // XFL-Form - MTFSF 664 // This is probably 1.7.9, but I don't have the reference that uses this 665 // numbering scheme... 666 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 667 string cstr, InstrItinClass itin, list<dag>pattern> 668 : I<opcode, OOL, IOL, asmstr, itin> { 669 bits<8> FM; 670 bits<5> rT; 671 672 bit RC = 0; // set by isDOT 673 let Pattern = pattern; 674 let Constraints = cstr; 675 676 let Inst{6} = 0; 677 let Inst{7-14} = FM; 678 let Inst{15} = 0; 679 let Inst{16-20} = rT; 680 let Inst{21-30} = xo; 681 let Inst{31} = RC; 682 } 683 684 // 1.7.10 XS-Form - SRADI. 685 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 686 InstrItinClass itin, list<dag> pattern> 687 : I<opcode, OOL, IOL, asmstr, itin> { 688 bits<5> A; 689 bits<5> RS; 690 bits<6> SH; 691 692 bit RC = 0; // set by isDOT 693 let Pattern = pattern; 694 695 let Inst{6-10} = RS; 696 let Inst{11-15} = A; 697 let Inst{16-20} = SH{4,3,2,1,0}; 698 let Inst{21-29} = xo; 699 let Inst{30} = SH{5}; 700 let Inst{31} = RC; 701 } 702 703 // 1.7.11 XO-Form 704 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 705 InstrItinClass itin, list<dag> pattern> 706 : I<opcode, OOL, IOL, asmstr, itin> { 707 bits<5> RT; 708 bits<5> RA; 709 bits<5> RB; 710 711 let Pattern = pattern; 712 713 bit RC = 0; // set by isDOT 714 715 let Inst{6-10} = RT; 716 let Inst{11-15} = RA; 717 let Inst{16-20} = RB; 718 let Inst{21} = oe; 719 let Inst{22-30} = xo; 720 let Inst{31} = RC; 721 } 722 723 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 724 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 725 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 726 let RB = 0; 727 } 728 729 // 1.7.12 A-Form 730 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 731 InstrItinClass itin, list<dag> pattern> 732 : I<opcode, OOL, IOL, asmstr, itin> { 733 bits<5> FRT; 734 bits<5> FRA; 735 bits<5> FRC; 736 bits<5> FRB; 737 738 let Pattern = pattern; 739 740 bit RC = 0; // set by isDOT 741 742 let Inst{6-10} = FRT; 743 let Inst{11-15} = FRA; 744 let Inst{16-20} = FRB; 745 let Inst{21-25} = FRC; 746 let Inst{26-30} = xo; 747 let Inst{31} = RC; 748 } 749 750 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 751 InstrItinClass itin, list<dag> pattern> 752 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 753 let FRC = 0; 754 } 755 756 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 757 InstrItinClass itin, list<dag> pattern> 758 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 759 let FRB = 0; 760 } 761 762 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 763 InstrItinClass itin, list<dag> pattern> 764 : I<opcode, OOL, IOL, asmstr, itin> { 765 bits<5> RT; 766 bits<5> RA; 767 bits<5> RB; 768 bits<7> BIBO; // 2 bits of BI and 5 bits of BO (must be 12). 769 bits<3> CR; 770 771 let Pattern = pattern; 772 773 let Inst{6-10} = RT; 774 let Inst{11-15} = RA; 775 let Inst{16-20} = RB; 776 let Inst{21-23} = CR; 777 let Inst{24-25} = BIBO{6-5}; 778 let Inst{26-30} = xo; 779 let Inst{31} = 0; 780 } 781 782 // 1.7.13 M-Form 783 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 784 InstrItinClass itin, list<dag> pattern> 785 : I<opcode, OOL, IOL, asmstr, itin> { 786 bits<5> RA; 787 bits<5> RS; 788 bits<5> RB; 789 bits<5> MB; 790 bits<5> ME; 791 792 let Pattern = pattern; 793 794 bit RC = 0; // set by isDOT 795 796 let Inst{6-10} = RS; 797 let Inst{11-15} = RA; 798 let Inst{16-20} = RB; 799 let Inst{21-25} = MB; 800 let Inst{26-30} = ME; 801 let Inst{31} = RC; 802 } 803 804 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 805 InstrItinClass itin, list<dag> pattern> 806 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 807 } 808 809 // 1.7.14 MD-Form 810 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 811 InstrItinClass itin, list<dag> pattern> 812 : I<opcode, OOL, IOL, asmstr, itin> { 813 bits<5> RA; 814 bits<5> RS; 815 bits<6> SH; 816 bits<6> MBE; 817 818 let Pattern = pattern; 819 820 bit RC = 0; // set by isDOT 821 822 let Inst{6-10} = RS; 823 let Inst{11-15} = RA; 824 let Inst{16-20} = SH{4,3,2,1,0}; 825 let Inst{21-26} = MBE{4,3,2,1,0,5}; 826 let Inst{27-29} = xo; 827 let Inst{30} = SH{5}; 828 let Inst{31} = RC; 829 } 830 831 832 833 // E-1 VA-Form 834 835 // VAForm_1 - DACB ordering. 836 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 837 InstrItinClass itin, list<dag> pattern> 838 : I<4, OOL, IOL, asmstr, itin> { 839 bits<5> VD; 840 bits<5> VA; 841 bits<5> VC; 842 bits<5> VB; 843 844 let Pattern = pattern; 845 846 let Inst{6-10} = VD; 847 let Inst{11-15} = VA; 848 let Inst{16-20} = VB; 849 let Inst{21-25} = VC; 850 let Inst{26-31} = xo; 851 } 852 853 // VAForm_1a - DABC ordering. 854 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 855 InstrItinClass itin, list<dag> pattern> 856 : I<4, OOL, IOL, asmstr, itin> { 857 bits<5> VD; 858 bits<5> VA; 859 bits<5> VB; 860 bits<5> VC; 861 862 let Pattern = pattern; 863 864 let Inst{6-10} = VD; 865 let Inst{11-15} = VA; 866 let Inst{16-20} = VB; 867 let Inst{21-25} = VC; 868 let Inst{26-31} = xo; 869 } 870 871 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 872 InstrItinClass itin, list<dag> pattern> 873 : I<4, OOL, IOL, asmstr, itin> { 874 bits<5> VD; 875 bits<5> VA; 876 bits<5> VB; 877 bits<4> SH; 878 879 let Pattern = pattern; 880 881 let Inst{6-10} = VD; 882 let Inst{11-15} = VA; 883 let Inst{16-20} = VB; 884 let Inst{21} = 0; 885 let Inst{22-25} = SH; 886 let Inst{26-31} = xo; 887 } 888 889 // E-2 VX-Form 890 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 891 InstrItinClass itin, list<dag> pattern> 892 : I<4, OOL, IOL, asmstr, itin> { 893 bits<5> VD; 894 bits<5> VA; 895 bits<5> VB; 896 897 let Pattern = pattern; 898 899 let Inst{6-10} = VD; 900 let Inst{11-15} = VA; 901 let Inst{16-20} = VB; 902 let Inst{21-31} = xo; 903 } 904 905 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 906 InstrItinClass itin, list<dag> pattern> 907 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 908 let VA = VD; 909 let VB = VD; 910 } 911 912 913 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 914 InstrItinClass itin, list<dag> pattern> 915 : I<4, OOL, IOL, asmstr, itin> { 916 bits<5> VD; 917 bits<5> VB; 918 919 let Pattern = pattern; 920 921 let Inst{6-10} = VD; 922 let Inst{11-15} = 0; 923 let Inst{16-20} = VB; 924 let Inst{21-31} = xo; 925 } 926 927 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 928 InstrItinClass itin, list<dag> pattern> 929 : I<4, OOL, IOL, asmstr, itin> { 930 bits<5> VD; 931 bits<5> IMM; 932 933 let Pattern = pattern; 934 935 let Inst{6-10} = VD; 936 let Inst{11-15} = IMM; 937 let Inst{16-20} = 0; 938 let Inst{21-31} = xo; 939 } 940 941 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 942 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 943 InstrItinClass itin, list<dag> pattern> 944 : I<4, OOL, IOL, asmstr, itin> { 945 bits<5> VD; 946 947 let Pattern = pattern; 948 949 let Inst{6-10} = VD; 950 let Inst{11-15} = 0; 951 let Inst{16-20} = 0; 952 let Inst{21-31} = xo; 953 } 954 955 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 956 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 957 InstrItinClass itin, list<dag> pattern> 958 : I<4, OOL, IOL, asmstr, itin> { 959 bits<5> VB; 960 961 let Pattern = pattern; 962 963 let Inst{6-10} = 0; 964 let Inst{11-15} = 0; 965 let Inst{16-20} = VB; 966 let Inst{21-31} = xo; 967 } 968 969 // E-4 VXR-Form 970 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 971 InstrItinClass itin, list<dag> pattern> 972 : I<4, OOL, IOL, asmstr, itin> { 973 bits<5> VD; 974 bits<5> VA; 975 bits<5> VB; 976 bit RC = 0; 977 978 let Pattern = pattern; 979 980 let Inst{6-10} = VD; 981 let Inst{11-15} = VA; 982 let Inst{16-20} = VB; 983 let Inst{21} = RC; 984 let Inst{22-31} = xo; 985 } 986 987 //===----------------------------------------------------------------------===// 988 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 989 : I<0, OOL, IOL, asmstr, NoItinerary> { 990 let PPC64 = 0; 991 let Pattern = pattern; 992 let Inst{31-0} = 0; 993 } 994
