1 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s 2 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s --check-prefix=CHECK-VFP 3 ; RUN: llc < %s -mattr=+neon,+thumb2 -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=CHECK-NEON 4 5 define i32 @f1(i32 %a.s) { 6 ;CHECK: f1: 7 ;CHECK: moveq 8 entry: 9 %tmp = icmp eq i32 %a.s, 4 10 %tmp1.s = select i1 %tmp, i32 2, i32 3 11 ret i32 %tmp1.s 12 } 13 14 define i32 @f2(i32 %a.s) { 15 ;CHECK: f2: 16 ;CHECK: movgt 17 entry: 18 %tmp = icmp sgt i32 %a.s, 4 19 %tmp1.s = select i1 %tmp, i32 2, i32 3 20 ret i32 %tmp1.s 21 } 22 23 define i32 @f3(i32 %a.s, i32 %b.s) { 24 ;CHECK: f3: 25 ;CHECK: movlt 26 entry: 27 %tmp = icmp slt i32 %a.s, %b.s 28 %tmp1.s = select i1 %tmp, i32 2, i32 3 29 ret i32 %tmp1.s 30 } 31 32 define i32 @f4(i32 %a.s, i32 %b.s) { 33 ;CHECK: f4: 34 ;CHECK: movle 35 entry: 36 %tmp = icmp sle i32 %a.s, %b.s 37 %tmp1.s = select i1 %tmp, i32 2, i32 3 38 ret i32 %tmp1.s 39 } 40 41 define i32 @f5(i32 %a.u, i32 %b.u) { 42 ;CHECK: f5: 43 ;CHECK: movls 44 entry: 45 %tmp = icmp ule i32 %a.u, %b.u 46 %tmp1.s = select i1 %tmp, i32 2, i32 3 47 ret i32 %tmp1.s 48 } 49 50 define i32 @f6(i32 %a.u, i32 %b.u) { 51 ;CHECK: f6: 52 ;CHECK: movhi 53 entry: 54 %tmp = icmp ugt i32 %a.u, %b.u 55 %tmp1.s = select i1 %tmp, i32 2, i32 3 56 ret i32 %tmp1.s 57 } 58 59 define double @f7(double %a, double %b) { 60 ;CHECK: f7: 61 ;CHECK: movlt 62 ;CHECK: movlt 63 ;CHECK-VFP: f7: 64 ;CHECK-VFP: vmovmi 65 %tmp = fcmp olt double %a, 1.234e+00 66 %tmp1 = select i1 %tmp, double -1.000e+00, double %b 67 ret double %tmp1 68 } 69 70 ; <rdar://problem/7260094> 71 ; 72 ; We used to generate really horrible code for this function. The main cause was 73 ; a lack of a custom lowering routine for an ISD::SELECT. This would result in 74 ; two "it" blocks in the code: one for the "icmp" and another to move the index 75 ; into the constant pool based on the value of the "icmp". If we have one "it" 76 ; block generated, odds are good that we have close to the ideal code for this: 77 ; 78 ; CHECK-NEON: _f8: 79 ; CHECK-NEON: movw [[R3:r[0-9]+]], #1123 80 ; CHECK-NEON: adr [[R2:r[0-9]+]], LCPI7_0 81 ; CHECK-NEON-NEXT: cmp r0, [[R3]] 82 ; CHECK-NEON-NEXT: it eq 83 ; CHECK-NEON-NEXT: addeq{{.*}} [[R2]], #4 84 ; CHECK-NEON-NEXT: ldr 85 ; CHECK-NEON: bx 86 87 define arm_apcscc float @f8(i32 %a) nounwind { 88 %tmp = icmp eq i32 %a, 1123 89 %tmp1 = select i1 %tmp, float 0x3FF3BE76C0000000, float 0x40030E9A20000000 90 ret float %tmp1 91 } 92 93 ; <rdar://problem/9049552> 94 ; Glue values can only have a single use, but the following test exposed a 95 ; case where a SELECT was lowered with 2 uses of a comparison, causing the 96 ; scheduler to assert. 97 ; CHECK-VFP: f9: 98 99 declare i8* @objc_msgSend(i8*, i8*, ...) 100 define void @f9() optsize { 101 entry: 102 %cmp = icmp eq i8* undef, inttoptr (i32 4 to i8*) 103 %conv191 = select i1 %cmp, float -3.000000e+00, float 0.000000e+00 104 %conv195 = select i1 %cmp, double -1.000000e+00, double 0.000000e+00 105 %add = fadd double %conv195, 1.100000e+01 106 %conv196 = fptrunc double %add to float 107 %add201 = fadd float undef, %conv191 108 %tmp484 = bitcast float %conv196 to i32 109 %tmp478 = bitcast float %add201 to i32 110 %tmp490 = insertvalue [2 x i32] undef, i32 %tmp484, 0 111 %tmp493 = insertvalue [2 x i32] %tmp490, i32 %tmp478, 1 112 call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, [2 x i32], i32, float)*)(i8* undef, i8* undef, [2 x i32] %tmp493, i32 0, float 1.000000e+00) optsize 113 ret void 114 } 115 116 ; CHECK: f10 117 define float @f10(i32 %a, i32 %b) nounwind uwtable readnone ssp { 118 ; CHECK-NOT: floatsisf 119 %1 = icmp eq i32 %a, %b 120 %2 = zext i1 %1 to i32 121 %3 = sitofp i32 %2 to float 122 ret float %3 123 } 124 125 ; CHECK: f11 126 define float @f11(i32 %a, i32 %b) nounwind uwtable readnone ssp { 127 ; CHECK-NOT: floatsisf 128 %1 = icmp eq i32 %a, %b 129 %2 = sitofp i1 %1 to float 130 ret float %2 131 } 132 133 ; CHECK: f12 134 define float @f12(i32 %a, i32 %b) nounwind uwtable readnone ssp { 135 ; CHECK-NOT: floatunsisf 136 %1 = icmp eq i32 %a, %b 137 %2 = uitofp i1 %1 to float 138 ret float %2 139 } 140 141
