1 ; RUN: llc < %s -enable-misched -pre-RA-sched=source -scheditins=false \ 2 ; RUN: -disable-ifcvt-triangle-false -disable-post-ra | FileCheck %s 3 ; 4 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" 5 target triple = "powerpc64-bgq-linux" 6 7 ; %val1 is a load live out of %entry. It should be hoisted 8 ; above the add. 9 ; CHECK: testload: 10 ; CHECK: %entry 11 ; CHECK: lwz 12 ; CHECK: addi 13 ; CHECK: bne 14 ; CHECK: %true 15 define i32 @testload(i32 *%ptr, i32 %sumin) { 16 entry: 17 %sum1 = add i32 %sumin, 1 18 %val1 = load i32* %ptr 19 %p = icmp eq i32 %sumin, 0 20 br i1 %p, label %true, label %end 21 true: 22 %sum2 = add i32 %sum1, 1 23 %ptr2 = getelementptr i32* %ptr, i32 1 24 %val = load i32* %ptr2 25 %val2 = add i32 %val1, %val 26 br label %end 27 end: 28 %valmerge = phi i32 [ %val1, %entry], [ %val2, %true ] 29 %summerge = phi i32 [ %sum1, %entry], [ %sum2, %true ] 30 %sumout = add i32 %valmerge, %summerge 31 ret i32 %sumout 32 } 33 34 ; The prefetch gets a default latency of 3 cycles and should be hoisted 35 ; above the add. 36 ; 37 ; CHECK: testprefetch: 38 ; CHECK: %entry 39 ; CHECK: dcbt 40 ; CHECK: addi 41 ; CHECK: blr 42 define i32 @testprefetch(i8 *%ptr, i32 %i) { 43 entry: 44 %val1 = add i32 %i, 1 45 tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 ) 46 %p = icmp eq i32 %i, 0 47 br i1 %p, label %true, label %end 48 true: 49 %val2 = add i32 %val1, 1 50 br label %end 51 end: 52 %valmerge = phi i32 [ %val1, %entry], [ %val2, %true ] 53 ret i32 %valmerge 54 } 55 declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind 56
