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      1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
      2 
      3 ; Make sure that we don't match this shuffle using the vpblendw YMM instruction.
      4 ; The mask for the vpblendw instruction needs to be identical for both halves
      5 ; of the YMM. Need to use two vpblendw instructions.
      6 
      7 ; CHECK: vpblendw_test1
      8 ; mask = 10010110,b = 150,d
      9 ; CHECK: vpblendw  $150, %ymm
     10 ; CHECK: ret
     11 define <16 x i16> @vpblendw_test1(<16 x i16> %a, <16 x i16> %b) nounwind alwaysinline {
     12   %t = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 17, i32 18, i32 3,  i32 20, i32 5,  i32 6,  i32 23, 
     13                                                                i32 8, i32 25, i32 26, i32 11, i32 28, i32 13, i32 14, i32 31>
     14   ret <16 x i16> %t
     15 }
     16 
     17 ; CHECK: vpblendw_test2
     18 ; mask1 = 00010110 = 22
     19 ; mask2 = 10000000 = 128
     20 ; CHECK: vpblendw  $128, %xmm
     21 ; CHECK: vpblendw  $22, %xmm
     22 ; CHECK: vinserti128
     23 ; CHECK: ret
     24 define <16 x i16> @vpblendw_test2(<16 x i16> %a, <16 x i16> %b) nounwind alwaysinline {
     25   %t = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 17, i32 18, i32 3, i32 20, i32 5, i32 6, i32 7, 
     26                                                                i32 8, i32 9,  i32 10, i32 11, i32 12, i32 13, i32 14, i32 31>
     27   ret <16 x i16> %t
     28 }
     29 
     30 ; CHECK: blend_test1
     31 ; CHECK: vpblendd
     32 ; CHECK: ret
     33 define <8 x i32> @blend_test1(<8 x i32> %a, <8 x i32> %b) nounwind alwaysinline {
     34   %t = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 12, i32 5, i32 6, i32 7>
     35   ret <8 x i32> %t
     36 }
     37 
     38 ; CHECK: blend_test2
     39 ; CHECK: vpblendd
     40 ; CHECK: ret
     41 define <8 x i32> @blend_test2(<8 x i32> %a, <8 x i32> %b) nounwind alwaysinline {
     42   %t = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 12, i32 5, i32 6, i32 7>
     43   ret <8 x i32> %t
     44 }
     45 
     46 
     47 ; CHECK: blend_test3
     48 ; CHECK: vblendps
     49 ; CHECK: ret
     50 define <8 x float> @blend_test3(<8 x float> %a, <8 x float> %b) nounwind alwaysinline {
     51   %t = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 12, i32 5, i32 6, i32 7>
     52   ret <8 x float> %t
     53 }
     54 
     55 ; CHECK: blend_test4
     56 ; CHECK: vblendpd
     57 ; CHECK: ret
     58 define <4 x i64> @blend_test4(<4 x i64> %a, <4 x i64> %b) nounwind alwaysinline {
     59   %t = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
     60   ret <4 x i64> %t
     61 }
     62 
     63 ; CHECK: vpshufhw $27, %ymm
     64 define <16 x i16> @vpshufhw(<16 x i16> %src1) nounwind uwtable readnone ssp {
     65 entry:
     66   %shuffle.i = shufflevector <16 x i16> %src1, <16 x i16> %src1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 6, i32 5, i32 4, i32 8, i32 9, i32 10, i32 11, i32 15, i32 14, i32 13, i32 12>
     67   ret <16 x i16> %shuffle.i
     68 }
     69 
     70 ; CHECK: vpshuflw $27, %ymm
     71 define <16 x i16> @vpshuflw(<16 x i16> %src1) nounwind uwtable readnone ssp {
     72 entry:
     73   %shuffle.i = shufflevector <16 x i16> %src1, <16 x i16> %src1, <16 x i32> <i32 3, i32 undef, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7, i32 11, i32 10, i32 9, i32 8, i32 12, i32 13, i32 14, i32 15>
     74   ret <16 x i16> %shuffle.i
     75 }
     76 
     77 ; CHECK: vpshufb_test
     78 ; CHECK: vpshufb {{.*\(%r.*}}, %ymm
     79 ; CHECK: ret
     80 define <32 x i8> @vpshufb_test(<32 x i8> %a) nounwind {
     81   %S = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15, 
     82                                                                 i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15,  
     83                                                                 i32 18, i32 19, i32 30, i32 16, i32 25, i32 23, i32 17, i32 25, 
     84                                                                 i32 20, i32 19, i32 31, i32 17, i32 23, i32 undef, i32 29, i32 18>
     85   ret <32 x i8>%S
     86 }
     87 
     88 ; CHECK: vpshufb1_test
     89 ; CHECK: vpshufb {{.*\(%r.*}}, %ymm
     90 ; CHECK: ret
     91 define <32 x i8> @vpshufb1_test(<32 x i8> %a) nounwind {
     92   %S = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15, 
     93                                                                 i32 1, i32 9, i32 36, i32 11, i32 5, i32 13, i32 7, i32 15,  
     94                                                                 i32 18, i32 49, i32 30, i32 16, i32 25, i32 23, i32 17, i32 25, 
     95                                                                 i32 20, i32 19, i32 31, i32 17, i32 23, i32 undef, i32 29, i32 18>
     96   ret <32 x i8>%S
     97 }
     98 
     99 
    100 ; CHECK: vpshufb2_test
    101 ; CHECK: vpshufb {{.*\(%r.*}}, %ymm
    102 ; CHECK: ret
    103 define <32 x i8> @vpshufb2_test(<32 x i8> %a) nounwind {
    104   %S = shufflevector <32 x i8> zeroinitializer, <32 x i8> %a, <32 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15, 
    105                                                                 i32 1, i32 9, i32 36, i32 11, i32 5, i32 13, i32 7, i32 15,  
    106                                                                 i32 18, i32 49, i32 30, i32 16, i32 25, i32 23, i32 17, i32 25, 
    107                                                                 i32 20, i32 19, i32 31, i32 17, i32 23, i32 undef, i32 29, i32 18>
    108   ret <32 x i8>%S
    109 }
    110