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      1 // RUN: llvm-tblgen %s | grep "add_ps" | count 3
      2 
      3 class ValueType<int size, int value> {
      4   int Size = size;
      5   int Value = value;
      6 }
      7 
      8 def v2i64  : ValueType<128, 22>;   //  2 x i64 vector value
      9 def v2f64  : ValueType<128, 28>;   //  2 x f64 vector value
     10 
     11 class Intrinsic<string name> {
     12   string Name = name;
     13 }
     14 
     15 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr, 
     16            list<dag> pattern> {
     17   bits<8> Opcode = opcode;
     18   dag OutOperands = oopnds;
     19   dag InOperands = iopnds;
     20   string AssemblyString = asmstr;
     21   list<dag> Pattern = pattern;
     22 }
     23 
     24 def ops;
     25 def outs;
     26 def ins;
     27 
     28 def set;
     29 
     30 // Define registers
     31 class Register<string n> {
     32   string Name = n;
     33 }
     34 
     35 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
     36   list<ValueType> RegTypes = regTypes;
     37   list<Register> MemberList = regList;
     38 }
     39 
     40 def XMM0: Register<"xmm0">;
     41 def XMM1: Register<"xmm1">;
     42 def XMM2: Register<"xmm2">;
     43 def XMM3: Register<"xmm3">;
     44 def XMM4: Register<"xmm4">;
     45 def XMM5: Register<"xmm5">;
     46 def XMM6: Register<"xmm6">;
     47 def XMM7: Register<"xmm7">;
     48 def XMM8:  Register<"xmm8">;
     49 def XMM9:  Register<"xmm9">;
     50 def XMM10: Register<"xmm10">;
     51 def XMM11: Register<"xmm11">;
     52 def XMM12: Register<"xmm12">;
     53 def XMM13: Register<"xmm13">;
     54 def XMM14: Register<"xmm14">;
     55 def XMM15: Register<"xmm15">;
     56 
     57 def VR128 : RegisterClass<[v2i64, v2f64],
     58                           [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
     59                            XMM8, XMM9, XMM10, XMM11,
     60                            XMM12, XMM13, XMM14, XMM15]>;
     61 
     62 // Define intrinsics
     63 def int_x86_sse2_add_ps : Intrinsic<"addps">;
     64 def int_x86_sse2_add_pd : Intrinsic<"addpd">;
     65 
     66 multiclass arith<bits<8> opcode, string asmstr, string Intr> {
     67   def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
     68                  !strconcat(asmstr, "\t$dst, $src1, $src2"),
     69                  [(set VR128:$dst, (!cast<Intrinsic>(!strconcat(Intr, "_ps")) VR128:$src1, VR128:$src2))]>;
     70 
     71   def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
     72                  !strconcat(asmstr, "\t$dst, $src1, $src2"),
     73                  [(set VR128:$dst, (!cast<Intrinsic>(!strconcat(Intr, "_pd")) VR128:$src1, VR128:$src2))]>;
     74 }
     75 
     76 defm ADD : arith<0x58, "add", "int_x86_sse2_add">;
     77 
     78 class IntInst<bits<8> opcode, string asmstr, Intrinsic Intr> :
     79   Inst<opcode,(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
     80        !strconcat(asmstr, "\t$dst, $src1, $src2"),
     81        [(set VR128:$dst, (Intr VR128:$src1, VR128:$src2))]>;
     82 
     83 
     84 multiclass arith_int<bits<8> opcode, string asmstr, string Intr> {
     85   def PS_Int : IntInst<opcode, asmstr, !cast<Intrinsic>(!strconcat(Intr, "_ps"))>;
     86 
     87   def PD_Int : IntInst<opcode, asmstr, !cast<Intrinsic>(!strconcat(Intr, "_pd"))>;
     88 }
     89 
     90 defm ADD : arith_int<0x58, "add", "int_x86_sse2_add">;
     91