1 #ifndef __SOUND_EMU10K1_H 2 #define __SOUND_EMU10K1_H 3 4 /* 5 * Copyright (c) by Jaroslav Kysela <perex (at) perex.cz>, 6 * Creative Labs, Inc. 7 * Definitions for EMU10K1 (SB Live!) chips 8 * 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 26 #include <stdint.h> 27 28 /* 29 * ---- FX8010 ---- 30 */ 31 32 #define EMU10K1_CARD_CREATIVE 0x00000000 33 #define EMU10K1_CARD_EMUAPS 0x00000001 34 35 #define EMU10K1_FX8010_PCM_COUNT 8 36 37 /* instruction set */ 38 #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */ 39 #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */ 40 #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */ 41 #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */ 42 #define iMACINT0 0x04 /* R = A + X * Y ; saturation */ 43 #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */ 44 #define iACC3 0x06 /* R = A + X + Y ; saturation */ 45 #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */ 46 #define iANDXOR 0x08 /* R = (A & X) ^ Y */ 47 #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */ 48 #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */ 49 #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */ 50 #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */ 51 #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */ 52 #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */ 53 #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */ 54 55 /* GPRs */ 56 #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */ 57 #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */ 58 #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f */ 59 #define C_00000000 0x40 60 #define C_00000001 0x41 61 #define C_00000002 0x42 62 #define C_00000003 0x43 63 #define C_00000004 0x44 64 #define C_00000008 0x45 65 #define C_00000010 0x46 66 #define C_00000020 0x47 67 #define C_00000100 0x48 68 #define C_00010000 0x49 69 #define C_00080000 0x4a 70 #define C_10000000 0x4b 71 #define C_20000000 0x4c 72 #define C_40000000 0x4d 73 #define C_80000000 0x4e 74 #define C_7fffffff 0x4f 75 #define C_ffffffff 0x50 76 #define C_fffffffe 0x51 77 #define C_c0000000 0x52 78 #define C_4f1bbcdc 0x53 79 #define C_5a7ef9db 0x54 80 #define C_00100000 0x55 /* ?? */ 81 #define GPR_ACCU 0x56 /* ACCUM, accumulator */ 82 #define GPR_COND 0x57 /* CCR, condition register */ 83 #define GPR_NOISE0 0x58 /* noise source */ 84 #define GPR_NOISE1 0x59 /* noise source */ 85 #define GPR_IRQ 0x5a /* IRQ register */ 86 #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */ 87 #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */ 88 #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */ 89 #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ 90 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */ 91 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ 92 93 #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f? */ 94 #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x1f? */ 95 #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f? */ 96 #define A_GPR(x) (A_FXGPREGBASE + (x)) 97 98 /* cc_reg constants */ 99 #define CC_REG_NORMALIZED C_00000001 100 #define CC_REG_BORROW C_00000002 101 #define CC_REG_MINUS C_00000004 102 #define CC_REG_ZERO C_00000008 103 #define CC_REG_SATURATE C_00000010 104 #define CC_REG_NONZERO C_00000100 105 106 /* FX buses */ 107 #define FXBUS_PCM_LEFT 0x00 108 #define FXBUS_PCM_RIGHT 0x01 109 #define FXBUS_PCM_LEFT_REAR 0x02 110 #define FXBUS_PCM_RIGHT_REAR 0x03 111 #define FXBUS_MIDI_LEFT 0x04 112 #define FXBUS_MIDI_RIGHT 0x05 113 #define FXBUS_PCM_CENTER 0x06 114 #define FXBUS_PCM_LFE 0x07 115 #define FXBUS_PCM_LEFT_FRONT 0x08 116 #define FXBUS_PCM_RIGHT_FRONT 0x09 117 #define FXBUS_MIDI_REVERB 0x0c 118 #define FXBUS_MIDI_CHORUS 0x0d 119 #define FXBUS_PCM_LEFT_SIDE 0x0e 120 #define FXBUS_PCM_RIGHT_SIDE 0x0f 121 #define FXBUS_PT_LEFT 0x14 122 #define FXBUS_PT_RIGHT 0x15 123 124 /* Inputs */ 125 #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */ 126 #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */ 127 #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */ 128 #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */ 129 #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */ 130 #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */ 131 #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */ 132 #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */ 133 #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */ 134 #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */ 135 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */ 136 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */ 137 #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */ 138 #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */ 139 140 /* Outputs */ 141 #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */ 142 #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */ 143 #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */ 144 #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */ 145 #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */ 146 #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */ 147 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */ 148 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */ 149 #define EXTOUT_REAR_L 0x08 /* Rear channel - left */ 150 #define EXTOUT_REAR_R 0x09 /* Rear channel - right */ 151 #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */ 152 #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */ 153 #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */ 154 #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */ 155 #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */ 156 #define EXTOUT_ACENTER 0x11 /* Analog Center */ 157 #define EXTOUT_ALFE 0x12 /* Analog LFE */ 158 159 /* Audigy Inputs */ 160 #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */ 161 #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */ 162 #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */ 163 #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */ 164 #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */ 165 #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */ 166 #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */ 167 #define A_EXTIN_LINE2_R 0x09 /* right */ 168 #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */ 169 #define A_EXTIN_ADC_R 0x0b /* right */ 170 #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */ 171 #define A_EXTIN_AUX2_R 0x0d /* - right */ 172 173 /* Audigiy Outputs */ 174 #define A_EXTOUT_FRONT_L 0x00 /* digital front left */ 175 #define A_EXTOUT_FRONT_R 0x01 /* right */ 176 #define A_EXTOUT_CENTER 0x02 /* digital front center */ 177 #define A_EXTOUT_LFE 0x03 /* digital front lfe */ 178 #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */ 179 #define A_EXTOUT_HEADPHONE_R 0x05 /* right */ 180 #define A_EXTOUT_REAR_L 0x06 /* digital rear left */ 181 #define A_EXTOUT_REAR_R 0x07 /* right */ 182 #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */ 183 #define A_EXTOUT_AFRONT_R 0x09 /* right */ 184 #define A_EXTOUT_ACENTER 0x0a /* analog center */ 185 #define A_EXTOUT_ALFE 0x0b /* analog LFE */ 186 #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */ 187 #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */ 188 #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */ 189 #define A_EXTOUT_AREAR_R 0x0f /* right */ 190 #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */ 191 #define A_EXTOUT_AC97_R 0x11 /* right */ 192 #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */ 193 #define A_EXTOUT_ADC_CAP_R 0x17 /* right */ 194 #define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */ 195 196 /* Audigy constants */ 197 #define A_C_00000000 0xc0 198 #define A_C_00000001 0xc1 199 #define A_C_00000002 0xc2 200 #define A_C_00000003 0xc3 201 #define A_C_00000004 0xc4 202 #define A_C_00000008 0xc5 203 #define A_C_00000010 0xc6 204 #define A_C_00000020 0xc7 205 #define A_C_00000100 0xc8 206 #define A_C_00010000 0xc9 207 #define A_C_00000800 0xca 208 #define A_C_10000000 0xcb 209 #define A_C_20000000 0xcc 210 #define A_C_40000000 0xcd 211 #define A_C_80000000 0xce 212 #define A_C_7fffffff 0xcf 213 #define A_C_ffffffff 0xd0 214 #define A_C_fffffffe 0xd1 215 #define A_C_c0000000 0xd2 216 #define A_C_4f1bbcdc 0xd3 217 #define A_C_5a7ef9db 0xd4 218 #define A_C_00100000 0xd5 219 #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */ 220 #define A_GPR_COND 0xd7 /* CCR, condition register */ 221 #define A_GPR_NOISE0 0xd8 /* noise source */ 222 #define A_GPR_NOISE1 0xd9 /* noise source */ 223 #define A_GPR_IRQ 0xda /* IRQ register */ 224 #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */ 225 #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */ 226 227 /* definitions for debug register */ 228 #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */ 229 #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */ 230 #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */ 231 #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */ 232 #define EMU10K1_DBG_STEP 0x00004000 /* start single step */ 233 #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */ 234 #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */ 235 236 /* tank memory address line */ 237 #ifndef __KERNEL__ 238 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */ 239 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */ 240 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */ 241 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */ 242 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */ 243 #endif 244 245 typedef struct { 246 unsigned int internal_tram_size; /* in samples */ 247 unsigned int external_tram_size; /* in samples */ 248 char fxbus_names[16][32]; /* names of FXBUSes */ 249 char extin_names[16][32]; /* names of external inputs */ 250 char extout_names[32][32]; /* names of external outputs */ 251 unsigned int gpr_controls; /* count of GPR controls */ 252 } emu10k1_fx8010_info_t; 253 254 #define EMU10K1_GPR_TRANSLATION_NONE 0 255 #define EMU10K1_GPR_TRANSLATION_TABLE100 1 256 #define EMU10K1_GPR_TRANSLATION_BASS 2 257 #define EMU10K1_GPR_TRANSLATION_TREBLE 3 258 #define EMU10K1_GPR_TRANSLATION_ONOFF 4 259 260 enum emu10k1_ctl_elem_iface { 261 EMU10K1_CTL_ELEM_IFACE_MIXER = 2, /* virtual mixer device */ 262 EMU10K1_CTL_ELEM_IFACE_PCM = 3, /* PCM device */ 263 }; 264 265 typedef struct { 266 unsigned int pad; /* don't use */ 267 int iface; /* interface identifier */ 268 unsigned int device; /* device/client number */ 269 unsigned int subdevice; /* subdevice (substream) number */ 270 unsigned char name[44]; /* ASCII name of item */ 271 unsigned int index; /* index of item */ 272 } emu10k1_ctl_elem_id_t; 273 274 typedef struct { 275 emu10k1_ctl_elem_id_t id; /* full control ID definition */ 276 unsigned int vcount; /* visible count */ 277 unsigned int count; /* count of GPR (1..16) */ 278 unsigned short gpr[32]; /* GPR number(s) */ 279 unsigned int value[32]; /* initial values */ 280 unsigned int min; /* minimum range */ 281 unsigned int max; /* maximum range */ 282 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ 283 unsigned int *tlv; 284 } emu10k1_fx8010_control_gpr_t; 285 286 typedef struct { 287 char name[128]; 288 289 unsigned long gpr_valid[0x200/(sizeof(unsigned long)*8)]; /* bitmask of valid initializers */ 290 uint32_t *gpr_map; /* initializers */ 291 292 unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */ 293 emu10k1_fx8010_control_gpr_t *gpr_add_controls; /* GPR controls to add/replace */ 294 295 unsigned int gpr_del_control_count; /* count of GPR controls to remove */ 296 emu10k1_ctl_elem_id_t *gpr_del_controls; /* IDs of GPR controls to remove */ 297 298 unsigned int gpr_list_control_count; /* count of GPR controls to list */ 299 unsigned int gpr_list_control_total; /* total count of GPR controls */ 300 emu10k1_fx8010_control_gpr_t *gpr_list_controls; /* listed GPR controls */ 301 302 unsigned long tram_valid[0x100/(sizeof(unsigned long)*8)]; /* bitmask of valid initializers */ 303 uint32_t *tram_data_map; /* data initializers */ 304 uint32_t *tram_addr_map; /* map initializers */ 305 306 unsigned long code_valid[1024/(sizeof(unsigned long)*8)]; /* bitmask of valid instructions */ 307 uint32_t *code; /* one instruction - 64 bits */ 308 } emu10k1_fx8010_code_t; 309 310 typedef struct { 311 unsigned int address; /* 31.bit == 1 -> external TRAM */ 312 unsigned int size; /* size in samples (4 bytes) */ 313 unsigned int *samples; /* pointer to samples (20-bit) */ 314 /* NULL->clear memory */ 315 } emu10k1_fx8010_tram_t; 316 317 typedef struct { 318 unsigned int substream; /* substream number */ 319 unsigned int res1; /* reserved */ 320 unsigned int channels; /* 16-bit channels count, zero = remove this substream */ 321 unsigned int tram_start; /* ring buffer position in TRAM (in samples) */ 322 unsigned int buffer_size; /* count of buffered samples */ 323 unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */ 324 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */ 325 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */ 326 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */ 327 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */ 328 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */ 329 unsigned char pad; /* reserved */ 330 unsigned char etram[32]; /* external TRAM address & data (one per channel) */ 331 unsigned int res2; /* reserved */ 332 } emu10k1_fx8010_pcm_t; 333 334 #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, emu10k1_fx8010_info_t) 335 #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, emu10k1_fx8010_code_t) 336 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, emu10k1_fx8010_code_t) 337 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int) 338 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, emu10k1_fx8010_tram_t) 339 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, emu10k1_fx8010_tram_t) 340 #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, emu10k1_fx8010_pcm_t) 341 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, emu10k1_fx8010_pcm_t) 342 #define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int) 343 #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80) 344 #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81) 345 #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82) 346 #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int) 347 #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int) 348 349 #endif /* __SOUND_EMU10K1_H */ 350
