| /external/llvm/lib/Target/R600/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 49 unsigned Imm = MI->getOperand(OpNum).getImm();
51 if (Imm == 2) {
53 } else if (Imm == 1) {
55 } else if (Imm == 0) {
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 88 IntFloatUnion Imm;
90 Imm.I = MO.getImm();
92 Imm.F = MO.getFPImm();
96 if (Imm.I >= 0 && Imm.I <= 64)
97 return 128 + Imm.I;
99 if (Imm.I >= -16 && Imm.I <= -1)
100 return 192 + abs(Imm.I);
102 if (Imm.F == 0.5f
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 64 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
65 switch (Imm) {
88 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
89 switch (Imm) {
159 O << markup("<imm:")
164 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
168 O << markup("<imm:")
209 << markup("<imm:")
|
| X86IntelInstPrinter.cpp | 54 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
55 switch (Imm) {
78 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
79 switch (Imm) {
|
| /external/llvm/lib/IR/ |
| AutoUpgrade.cpp | 237 unsigned Imm;
239 Imm = 0;
241 Imm = 1;
243 Imm = 2;
245 Imm = 3;
247 Imm = 4;
249 Imm = 5;
251 Imm = 6;
253 Imm = 7;
259 CI->getArgOperand(1), Builder.getInt8(Imm));
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 89 inline SDValue getI32Imm(unsigned Imm) {
90 return CurDAG->getTargetConstant(Imm, MVT::i32);
100 static bool isIntS32Immediate(SDNode *N, int32_t &Imm) {
105 Imm = (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
107 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
109 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
112 static bool isIntS32Immediate(SDValue Op, int32_t &Imm) {
113 return isIntS32Immediate(Op.getNode(), Imm);
119 /// can be more efficiently represented with [r+imm].
127 int32_t imm = 0
154 int32_t imm = 0; local
209 SDValue imm = CurDAG->getTargetConstant(0, MVT::i32); local
[all...] |
| /external/llvm/utils/TableGen/ |
| PseudoLoweringEmitter.cpp | 27 enum MapKind { Operand, Imm, Reg };
31 uint64_t Imm; // Integer immedate value.
104 OperandMap[BaseIdx + i].Kind = OpData::Imm;
105 OperandMap[BaseIdx + i].Data.Imm = II->getValue();
235 case OpData::Imm:
237 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
|
| CodeGenInstruction.h | 298 int64_t Imm;
307 ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {}
316 int64_t getImm() const { assert(isImm()); return Imm; }
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 82 bool SelectLogicalImm(SDValue N, SDValue &Imm);
153 ConstantFPSDNode *Imm = dyn_cast<ConstantFPSDNode>(N);
154 if (!Imm || !Imm->getValueAPF().isPosZero())
162 bool AArch64DAGToDAGISel::SelectLogicalImm(SDValue N, SDValue &Imm) {
172 Imm = CurDAG->getTargetConstant(Bits, MVT::i32);
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 106 // reg [asr|lsl|lsr|ror|rrx] imm
109 // reg, the second is the shift amount (or reg0 if not present or imm). The
110 // third operand encodes the shift opcode and the imm if a reg isn't present.
112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
113 return ShOp | (Imm << 3);
122 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
123 /// the 8-bit imm value.
124 static inline unsigned getSOImmValImm(unsigned Imm) {
125 return Imm & 0xFF
[all...] |
| ARMMCCodeEmitter.cpp | 84 unsigned &Reg, unsigned &Imm,
163 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
432 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
435 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
456 Imm = SImm;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelLowering.cpp | 630 int64_t imm = MI->getOperand(1).getImm(); local
633 if (isUInt<8>(imm))
635 else if (isUInt<16>(imm))
639 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
646 (unsigned shortOp, unsigned longOp, int64_t Imm) {
647 if (isUInt<8>(Imm))
649 else if (isInt<16>(Imm))
680 int64_t Imm = MI->getOperand(2).getImm();
681 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
683 TII->get(SltOpc)).addReg(regX).addImm(Imm);
[all...] |
| MipsSEISelDAGToDAG.cpp | 396 int64_t Imm = CN->getSExtValue();
399 AnalyzeImm.Analyze(Imm, Size, false);
|
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 492 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
493 int Offset = FIOffset + Imm;
494 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 381 // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
421 uint64_t Imm;
422 if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
589 // Rn_wb, Rt, Rt2, Rn, Imm
643 // Rt, Rt2, Rn_wb, Rt2, Rn, Imm
747 // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
775 // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 56 int32_t Imm = unpackSignedImm(9, MOImm.getImm());
58 O << '#' << Imm;
98 assert(Imm12 >= 0 && "Invalid immediate for add/sub imm");
247 uint32_t Imm = MOImm.getImm() * MemSize;
249 O << "#" << Imm;
366 int32_t Imm = unpackSignedImm(7, MOImm.getImm());
368 O << "#" << (Imm * MemScale);
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 438 } Imm;
441 Imm.I = Node->getSExtValue();
443 Imm.F = Node->getValueAPF().convertToFloat();
447 if ((Imm.I >= -16 && Imm.I <= 64) ||
448 Imm.F == 0.5f || Imm.F == -0.5f ||
449 Imm.F == 1.0f || Imm.F == -1.0f ||
450 Imm.F == 2.0f || Imm.F == -2.0f |
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | [all...] |
| Thumb2SizeReduction.cpp | 513 unsigned Imm = MI->getOperand(2).getImm();
517 if (Imm & 3 || Imm > 1020)
532 .addImm(Imm / 4); // The tADDrSPi has an implied scale by four.
648 unsigned Imm = MI->getOperand(2).getImm();
650 if (Imm > Limit)
[all...] |
| ARMAsmPrinter.cpp | 354 int64_t Imm = MO.getImm();
362 O << Imm;
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 31 static unsigned translateShiftImm(unsigned imm) {
33 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
35 if (imm == 0)
37 return imm;
53 O << "<imm:";
145 << markup("<imm:")
295 O << markup("<imm:")
322 << markup("<imm:") << "#" << formatImm(MO1.getImm())
333 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
382 << markup("<imm:"
[all...] |
| /external/llvm/lib/Target/MBlaze/AsmParser/ |
| MBlazeAsmParser.cpp | 111 struct ImmOp Imm;
127 Imm = o.Imm;
154 return Imm.Val;
246 Op->Imm.Val = Val;
254 Op->Imm.Val = Val;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 410 uint64_t Imm = CI->getZExtValue();
415 isPowerOf2_64(Imm)) {
416 Imm = Log2_64(Imm);
422 isPowerOf2_64(Imm)) {
423 --Imm;
428 Op0IsKill, Imm, VT.getSimpleVT());
[all...] |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 74 inline SDValue getI32Imm(unsigned Imm) {
75 return CurDAG->getTargetConstant(Imm, MVT::i32);
80 inline SDValue getI64Imm(uint64_t Imm) {
81 return CurDAG->getTargetConstant(Imm, MVT::i64);
85 inline SDValue getSmallIPtrImm(unsigned Imm) {
86 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
116 /// a base register plus a signed 16-bit displacement [r+imm].
149 /// be represented by [r+imm], which are preferred.
161 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
287 static bool isIntS16Immediate(SDNode *N, short &Imm) {
[all...] |
