| /external/llvm/lib/CodeGen/ |
| ScoreboardHazardRecognizer.cpp | 35 ScheduleHazardRecognizer(), ItinData(II), DAG(SchedDAG), IssueWidth(0),
46 if (ItinData && !ItinData->isEmpty()) {
48 if (ItinData->isEndMarker(idx))
51 const InstrStage *IS = ItinData->beginStage(idx);
52 const InstrStage *E = ItinData->endStage(idx);
80 IssueWidth = ItinData->SchedModel->IssueWidth;
119 if (!ItinData || ItinData->isEmpty())
134 for (const InstrStage *IS = ItinData->beginStage(idx)
[all...] |
| TargetInstrInfo.cpp | 574 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
577 if (!ItinData || ItinData->isEmpty())
585 return ItinData->getOperandCycle(DefClass, DefIdx);
587 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
590 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
592 if (!ItinData || ItinData->isEmpty())
598 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
606 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.h | 39 ARMHazardRecognizer(const InstrItineraryData *ItinData,
44 ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), TII(tii),
|
| ARMBaseInstrInfo.h | 220 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
224 int getOperandLatency(const InstrItineraryData *ItinData,
228 int getOperandLatency(const InstrItineraryData *ItinData,
247 int getVLDMDefCycle(const InstrItineraryData *ItinData,
251 int getLDMDefCycle(const InstrItineraryData *ItinData,
255 int getVSTMUseCycle(const InstrItineraryData *ItinData,
259 int getSTMUseCycle(const InstrItineraryData *ItinData,
263 int getOperandLatency(const InstrItineraryData *ItinData,
269 unsigned getInstrLatency(const InstrItineraryData *ItinData,
273 int getInstrLatency(const InstrItineraryData *ItinData,
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.h | 29 PPCScoreboardHazardRecognizer(const InstrItineraryData *ItinData,
31 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_) {}
|
| /external/llvm/include/llvm/CodeGen/ |
| ScoreboardHazardRecognizer.h | 93 const InstrItineraryData *ItinData;
107 ScoreboardHazardRecognizer(const InstrItineraryData *ItinData,
|
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /external/llvm/utils/TableGen/ |
| DFAPacketizerEmitter.cpp | 51 Record *ItinData,
354 Record *ItinData,
377 ItinData->getValueAsListOfDefs("Stages");
439 Record *ItinData = ItinDataList[j];
441 collectAllInsnClasses(Name, ItinData, NStages, OS);
|
| SubtargetEmitter.cpp | 69 Record *ItinData, std::string &ItinString,
71 void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
74 Record *ItinData,
293 Record *ItinData,
298 ItinData->getValueAsListOfDefs("Stages");
337 void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData,
341 ItinData->getValueAsListOfInts("OperandCycles");
355 Record *ItinData,
359 ItinData->getValueAsListOfDefs("Bypasses");
462 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]
[all...] |
| CodeGenSchedule.cpp | 780 Record *ItinData = ItinRecords[i];
781 Record *ItinDef = ItinData->getValueAsDef("TheClass");
787 ProcModel.ItinDefList[SCI->Index] = ItinData;
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.h | 112 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
116 virtual int getInstrLatency(const InstrItineraryData *ItinData,
|
| R600InstrInfo.cpp | 523 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 373 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
|
| X86InstrInfo.cpp | [all...] |
