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      1 //===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This tablegen backend emits subtarget enumerations.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #define DEBUG_TYPE "subtarget-emitter"
     15 
     16 #include "CodeGenTarget.h"
     17 #include "CodeGenSchedule.h"
     18 #include "llvm/ADT/STLExtras.h"
     19 #include "llvm/ADT/StringExtras.h"
     20 #include "llvm/MC/MCInstrItineraries.h"
     21 #include "llvm/Support/Debug.h"
     22 #include "llvm/Support/Format.h"
     23 #include "llvm/TableGen/Error.h"
     24 #include "llvm/TableGen/Record.h"
     25 #include "llvm/TableGen/TableGenBackend.h"
     26 #include <algorithm>
     27 #include <map>
     28 #include <string>
     29 #include <vector>
     30 using namespace llvm;
     31 
     32 namespace {
     33 class SubtargetEmitter {
     34   // Each processor has a SchedClassDesc table with an entry for each SchedClass.
     35   // The SchedClassDesc table indexes into a global write resource table, write
     36   // latency table, and read advance table.
     37   struct SchedClassTables {
     38     std::vector<std::vector<MCSchedClassDesc> > ProcSchedClasses;
     39     std::vector<MCWriteProcResEntry> WriteProcResources;
     40     std::vector<MCWriteLatencyEntry> WriteLatencies;
     41     std::vector<std::string> WriterNames;
     42     std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
     43 
     44     // Reserve an invalid entry at index 0
     45     SchedClassTables() {
     46       ProcSchedClasses.resize(1);
     47       WriteProcResources.resize(1);
     48       WriteLatencies.resize(1);
     49       WriterNames.push_back("InvalidWrite");
     50       ReadAdvanceEntries.resize(1);
     51     }
     52   };
     53 
     54   struct LessWriteProcResources {
     55     bool operator()(const MCWriteProcResEntry &LHS,
     56                     const MCWriteProcResEntry &RHS) {
     57       return LHS.ProcResourceIdx < RHS.ProcResourceIdx;
     58     }
     59   };
     60 
     61   RecordKeeper &Records;
     62   CodeGenSchedModels &SchedModels;
     63   std::string Target;
     64 
     65   void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
     66   unsigned FeatureKeyValues(raw_ostream &OS);
     67   unsigned CPUKeyValues(raw_ostream &OS);
     68   void FormItineraryStageString(const std::string &Names,
     69                                 Record *ItinData, std::string &ItinString,
     70                                 unsigned &NStages);
     71   void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
     72                                        unsigned &NOperandCycles);
     73   void FormItineraryBypassString(const std::string &Names,
     74                                  Record *ItinData,
     75                                  std::string &ItinString, unsigned NOperandCycles);
     76   void EmitStageAndOperandCycleData(raw_ostream &OS,
     77                                     std::vector<std::vector<InstrItinerary> >
     78                                       &ProcItinLists);
     79   void EmitItineraries(raw_ostream &OS,
     80                        std::vector<std::vector<InstrItinerary> >
     81                          &ProcItinLists);
     82   void EmitProcessorProp(raw_ostream &OS, const Record *R, const char *Name,
     83                          char Separator);
     84   void EmitProcessorResources(const CodeGenProcModel &ProcModel,
     85                               raw_ostream &OS);
     86   Record *FindWriteResources(const CodeGenSchedRW &SchedWrite,
     87                              const CodeGenProcModel &ProcModel);
     88   Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,
     89                           const CodeGenProcModel &ProcModel);
     90   void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
     91                            const CodeGenProcModel &ProcModel);
     92   void GenSchedClassTables(const CodeGenProcModel &ProcModel,
     93                            SchedClassTables &SchedTables);
     94   void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
     95   void EmitProcessorModels(raw_ostream &OS);
     96   void EmitProcessorLookup(raw_ostream &OS);
     97   void EmitSchedModelHelpers(std::string ClassName, raw_ostream &OS);
     98   void EmitSchedModel(raw_ostream &OS);
     99   void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
    100                              unsigned NumProcs);
    101 
    102 public:
    103   SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT):
    104     Records(R), SchedModels(TGT.getSchedModels()), Target(TGT.getName()) {}
    105 
    106   void run(raw_ostream &o);
    107 
    108 };
    109 } // End anonymous namespace
    110 
    111 //
    112 // Enumeration - Emit the specified class as an enumeration.
    113 //
    114 void SubtargetEmitter::Enumeration(raw_ostream &OS,
    115                                    const char *ClassName,
    116                                    bool isBits) {
    117   // Get all records of class and sort
    118   std::vector<Record*> DefList = Records.getAllDerivedDefinitions(ClassName);
    119   std::sort(DefList.begin(), DefList.end(), LessRecord());
    120 
    121   unsigned N = DefList.size();
    122   if (N == 0)
    123     return;
    124   if (N > 64) {
    125     errs() << "Too many (> 64) subtarget features!\n";
    126     exit(1);
    127   }
    128 
    129   OS << "namespace " << Target << " {\n";
    130 
    131   // For bit flag enumerations with more than 32 items, emit constants.
    132   // Emit an enum for everything else.
    133   if (isBits && N > 32) {
    134     // For each record
    135     for (unsigned i = 0; i < N; i++) {
    136       // Next record
    137       Record *Def = DefList[i];
    138 
    139       // Get and emit name and expression (1 << i)
    140       OS << "  const uint64_t " << Def->getName() << " = 1ULL << " << i << ";\n";
    141     }
    142   } else {
    143     // Open enumeration
    144     OS << "enum {\n";
    145 
    146     // For each record
    147     for (unsigned i = 0; i < N;) {
    148       // Next record
    149       Record *Def = DefList[i];
    150 
    151       // Get and emit name
    152       OS << "  " << Def->getName();
    153 
    154       // If bit flags then emit expression (1 << i)
    155       if (isBits)  OS << " = " << " 1ULL << " << i;
    156 
    157       // Depending on 'if more in the list' emit comma
    158       if (++i < N) OS << ",";
    159 
    160       OS << "\n";
    161     }
    162 
    163     // Close enumeration
    164     OS << "};\n";
    165   }
    166 
    167   OS << "}\n";
    168 }
    169 
    170 //
    171 // FeatureKeyValues - Emit data of all the subtarget features.  Used by the
    172 // command line.
    173 //
    174 unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
    175   // Gather and sort all the features
    176   std::vector<Record*> FeatureList =
    177                            Records.getAllDerivedDefinitions("SubtargetFeature");
    178 
    179   if (FeatureList.empty())
    180     return 0;
    181 
    182   std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName());
    183 
    184   // Begin feature table
    185   OS << "// Sorted (by key) array of values for CPU features.\n"
    186      << "extern const llvm::SubtargetFeatureKV " << Target
    187      << "FeatureKV[] = {\n";
    188 
    189   // For each feature
    190   unsigned NumFeatures = 0;
    191   for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
    192     // Next feature
    193     Record *Feature = FeatureList[i];
    194 
    195     const std::string &Name = Feature->getName();
    196     const std::string &CommandLineName = Feature->getValueAsString("Name");
    197     const std::string &Desc = Feature->getValueAsString("Desc");
    198 
    199     if (CommandLineName.empty()) continue;
    200 
    201     // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in }
    202     OS << "  { "
    203        << "\"" << CommandLineName << "\", "
    204        << "\"" << Desc << "\", "
    205        << Target << "::" << Name << ", ";
    206 
    207     const std::vector<Record*> &ImpliesList =
    208       Feature->getValueAsListOfDefs("Implies");
    209 
    210     if (ImpliesList.empty()) {
    211       OS << "0ULL";
    212     } else {
    213       for (unsigned j = 0, M = ImpliesList.size(); j < M;) {
    214         OS << Target << "::" << ImpliesList[j]->getName();
    215         if (++j < M) OS << " | ";
    216       }
    217     }
    218 
    219     OS << " }";
    220     ++NumFeatures;
    221 
    222     // Depending on 'if more in the list' emit comma
    223     if ((i + 1) < N) OS << ",";
    224 
    225     OS << "\n";
    226   }
    227 
    228   // End feature table
    229   OS << "};\n";
    230 
    231   return NumFeatures;
    232 }
    233 
    234 //
    235 // CPUKeyValues - Emit data of all the subtarget processors.  Used by command
    236 // line.
    237 //
    238 unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) {
    239   // Gather and sort processor information
    240   std::vector<Record*> ProcessorList =
    241                           Records.getAllDerivedDefinitions("Processor");
    242   std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
    243 
    244   // Begin processor table
    245   OS << "// Sorted (by key) array of values for CPU subtype.\n"
    246      << "extern const llvm::SubtargetFeatureKV " << Target
    247      << "SubTypeKV[] = {\n";
    248 
    249   // For each processor
    250   for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
    251     // Next processor
    252     Record *Processor = ProcessorList[i];
    253 
    254     const std::string &Name = Processor->getValueAsString("Name");
    255     const std::vector<Record*> &FeatureList =
    256       Processor->getValueAsListOfDefs("Features");
    257 
    258     // Emit as { "cpu", "description", f1 | f2 | ... fn },
    259     OS << "  { "
    260        << "\"" << Name << "\", "
    261        << "\"Select the " << Name << " processor\", ";
    262 
    263     if (FeatureList.empty()) {
    264       OS << "0ULL";
    265     } else {
    266       for (unsigned j = 0, M = FeatureList.size(); j < M;) {
    267         OS << Target << "::" << FeatureList[j]->getName();
    268         if (++j < M) OS << " | ";
    269       }
    270     }
    271 
    272     // The "0" is for the "implies" section of this data structure.
    273     OS << ", 0ULL }";
    274 
    275     // Depending on 'if more in the list' emit comma
    276     if (++i < N) OS << ",";
    277 
    278     OS << "\n";
    279   }
    280 
    281   // End processor table
    282   OS << "};\n";
    283 
    284   return ProcessorList.size();
    285 }
    286 
    287 //
    288 // FormItineraryStageString - Compose a string containing the stage
    289 // data initialization for the specified itinerary.  N is the number
    290 // of stages.
    291 //
    292 void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
    293                                                 Record *ItinData,
    294                                                 std::string &ItinString,
    295                                                 unsigned &NStages) {
    296   // Get states list
    297   const std::vector<Record*> &StageList =
    298     ItinData->getValueAsListOfDefs("Stages");
    299 
    300   // For each stage
    301   unsigned N = NStages = StageList.size();
    302   for (unsigned i = 0; i < N;) {
    303     // Next stage
    304     const Record *Stage = StageList[i];
    305 
    306     // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
    307     int Cycles = Stage->getValueAsInt("Cycles");
    308     ItinString += "  { " + itostr(Cycles) + ", ";
    309 
    310     // Get unit list
    311     const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units");
    312 
    313     // For each unit
    314     for (unsigned j = 0, M = UnitList.size(); j < M;) {
    315       // Add name and bitwise or
    316       ItinString += Name + "FU::" + UnitList[j]->getName();
    317       if (++j < M) ItinString += " | ";
    318     }
    319 
    320     int TimeInc = Stage->getValueAsInt("TimeInc");
    321     ItinString += ", " + itostr(TimeInc);
    322 
    323     int Kind = Stage->getValueAsInt("Kind");
    324     ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(Kind);
    325 
    326     // Close off stage
    327     ItinString += " }";
    328     if (++i < N) ItinString += ", ";
    329   }
    330 }
    331 
    332 //
    333 // FormItineraryOperandCycleString - Compose a string containing the
    334 // operand cycle initialization for the specified itinerary.  N is the
    335 // number of operands that has cycles specified.
    336 //
    337 void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData,
    338                          std::string &ItinString, unsigned &NOperandCycles) {
    339   // Get operand cycle list
    340   const std::vector<int64_t> &OperandCycleList =
    341     ItinData->getValueAsListOfInts("OperandCycles");
    342 
    343   // For each operand cycle
    344   unsigned N = NOperandCycles = OperandCycleList.size();
    345   for (unsigned i = 0; i < N;) {
    346     // Next operand cycle
    347     const int OCycle = OperandCycleList[i];
    348 
    349     ItinString += "  " + itostr(OCycle);
    350     if (++i < N) ItinString += ", ";
    351   }
    352 }
    353 
    354 void SubtargetEmitter::FormItineraryBypassString(const std::string &Name,
    355                                                  Record *ItinData,
    356                                                  std::string &ItinString,
    357                                                  unsigned NOperandCycles) {
    358   const std::vector<Record*> &BypassList =
    359     ItinData->getValueAsListOfDefs("Bypasses");
    360   unsigned N = BypassList.size();
    361   unsigned i = 0;
    362   for (; i < N;) {
    363     ItinString += Name + "Bypass::" + BypassList[i]->getName();
    364     if (++i < NOperandCycles) ItinString += ", ";
    365   }
    366   for (; i < NOperandCycles;) {
    367     ItinString += " 0";
    368     if (++i < NOperandCycles) ItinString += ", ";
    369   }
    370 }
    371 
    372 //
    373 // EmitStageAndOperandCycleData - Generate unique itinerary stages and operand
    374 // cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed
    375 // by CodeGenSchedClass::Index.
    376 //
    377 void SubtargetEmitter::
    378 EmitStageAndOperandCycleData(raw_ostream &OS,
    379                              std::vector<std::vector<InstrItinerary> >
    380                                &ProcItinLists) {
    381 
    382   // Multiple processor models may share an itinerary record. Emit it once.
    383   SmallPtrSet<Record*, 8> ItinsDefSet;
    384 
    385   // Emit functional units for all the itineraries.
    386   for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
    387          PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
    388 
    389     if (!ItinsDefSet.insert(PI->ItinsDef))
    390       continue;
    391 
    392     std::vector<Record*> FUs = PI->ItinsDef->getValueAsListOfDefs("FU");
    393     if (FUs.empty())
    394       continue;
    395 
    396     const std::string &Name = PI->ItinsDef->getName();
    397     OS << "\n// Functional units for \"" << Name << "\"\n"
    398        << "namespace " << Name << "FU {\n";
    399 
    400     for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j)
    401       OS << "  const unsigned " << FUs[j]->getName()
    402          << " = 1 << " << j << ";\n";
    403 
    404     OS << "}\n";
    405 
    406     std::vector<Record*> BPs = PI->ItinsDef->getValueAsListOfDefs("BP");
    407     if (BPs.size()) {
    408       OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name
    409          << "\"\n" << "namespace " << Name << "Bypass {\n";
    410 
    411       OS << "  const unsigned NoBypass = 0;\n";
    412       for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j)
    413         OS << "  const unsigned " << BPs[j]->getName()
    414            << " = 1 << " << j << ";\n";
    415 
    416       OS << "}\n";
    417     }
    418   }
    419 
    420   // Begin stages table
    421   std::string StageTable = "\nextern const llvm::InstrStage " + Target +
    422                            "Stages[] = {\n";
    423   StageTable += "  { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
    424 
    425   // Begin operand cycle table
    426   std::string OperandCycleTable = "extern const unsigned " + Target +
    427     "OperandCycles[] = {\n";
    428   OperandCycleTable += "  0, // No itinerary\n";
    429 
    430   // Begin pipeline bypass table
    431   std::string BypassTable = "extern const unsigned " + Target +
    432     "ForwardingPaths[] = {\n";
    433   BypassTable += " 0, // No itinerary\n";
    434 
    435   // For each Itinerary across all processors, add a unique entry to the stages,
    436   // operand cycles, and pipepine bypess tables. Then add the new Itinerary
    437   // object with computed offsets to the ProcItinLists result.
    438   unsigned StageCount = 1, OperandCycleCount = 1;
    439   std::map<std::string, unsigned> ItinStageMap, ItinOperandMap;
    440   for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
    441          PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
    442     const CodeGenProcModel &ProcModel = *PI;
    443 
    444     // Add process itinerary to the list.
    445     ProcItinLists.resize(ProcItinLists.size()+1);
    446 
    447     // If this processor defines no itineraries, then leave the itinerary list
    448     // empty.
    449     std::vector<InstrItinerary> &ItinList = ProcItinLists.back();
    450     if (!ProcModel.hasItineraries())
    451       continue;
    452 
    453     const std::string &Name = ProcModel.ItinsDef->getName();
    454 
    455     ItinList.resize(SchedModels.numInstrSchedClasses());
    456     assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins");
    457 
    458     for (unsigned SchedClassIdx = 0, SchedClassEnd = ItinList.size();
    459          SchedClassIdx < SchedClassEnd; ++SchedClassIdx) {
    460 
    461       // Next itinerary data
    462       Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
    463 
    464       // Get string and stage count
    465       std::string ItinStageString;
    466       unsigned NStages = 0;
    467       if (ItinData)
    468         FormItineraryStageString(Name, ItinData, ItinStageString, NStages);
    469 
    470       // Get string and operand cycle count
    471       std::string ItinOperandCycleString;
    472       unsigned NOperandCycles = 0;
    473       std::string ItinBypassString;
    474       if (ItinData) {
    475         FormItineraryOperandCycleString(ItinData, ItinOperandCycleString,
    476                                         NOperandCycles);
    477 
    478         FormItineraryBypassString(Name, ItinData, ItinBypassString,
    479                                   NOperandCycles);
    480       }
    481 
    482       // Check to see if stage already exists and create if it doesn't
    483       unsigned FindStage = 0;
    484       if (NStages > 0) {
    485         FindStage = ItinStageMap[ItinStageString];
    486         if (FindStage == 0) {
    487           // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
    488           StageTable += ItinStageString + ", // " + itostr(StageCount);
    489           if (NStages > 1)
    490             StageTable += "-" + itostr(StageCount + NStages - 1);
    491           StageTable += "\n";
    492           // Record Itin class number.
    493           ItinStageMap[ItinStageString] = FindStage = StageCount;
    494           StageCount += NStages;
    495         }
    496       }
    497 
    498       // Check to see if operand cycle already exists and create if it doesn't
    499       unsigned FindOperandCycle = 0;
    500       if (NOperandCycles > 0) {
    501         std::string ItinOperandString = ItinOperandCycleString+ItinBypassString;
    502         FindOperandCycle = ItinOperandMap[ItinOperandString];
    503         if (FindOperandCycle == 0) {
    504           // Emit as  cycle, // index
    505           OperandCycleTable += ItinOperandCycleString + ", // ";
    506           std::string OperandIdxComment = itostr(OperandCycleCount);
    507           if (NOperandCycles > 1)
    508             OperandIdxComment += "-"
    509               + itostr(OperandCycleCount + NOperandCycles - 1);
    510           OperandCycleTable += OperandIdxComment + "\n";
    511           // Record Itin class number.
    512           ItinOperandMap[ItinOperandCycleString] =
    513             FindOperandCycle = OperandCycleCount;
    514           // Emit as bypass, // index
    515           BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n";
    516           OperandCycleCount += NOperandCycles;
    517         }
    518       }
    519 
    520       // Set up itinerary as location and location + stage count
    521       int NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;
    522       InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
    523                                     FindOperandCycle,
    524                                     FindOperandCycle + NOperandCycles};
    525 
    526       // Inject - empty slots will be 0, 0
    527       ItinList[SchedClassIdx] = Intinerary;
    528     }
    529   }
    530 
    531   // Closing stage
    532   StageTable += "  { 0, 0, 0, llvm::InstrStage::Required } // End stages\n";
    533   StageTable += "};\n";
    534 
    535   // Closing operand cycles
    536   OperandCycleTable += "  0 // End operand cycles\n";
    537   OperandCycleTable += "};\n";
    538 
    539   BypassTable += " 0 // End bypass tables\n";
    540   BypassTable += "};\n";
    541 
    542   // Emit tables.
    543   OS << StageTable;
    544   OS << OperandCycleTable;
    545   OS << BypassTable;
    546 }
    547 
    548 //
    549 // EmitProcessorData - Generate data for processor itineraries that were
    550 // computed during EmitStageAndOperandCycleData(). ProcItinLists lists all
    551 // Itineraries for each processor. The Itinerary lists are indexed on
    552 // CodeGenSchedClass::Index.
    553 //
    554 void SubtargetEmitter::
    555 EmitItineraries(raw_ostream &OS,
    556                 std::vector<std::vector<InstrItinerary> > &ProcItinLists) {
    557 
    558   // Multiple processor models may share an itinerary record. Emit it once.
    559   SmallPtrSet<Record*, 8> ItinsDefSet;
    560 
    561   // For each processor's machine model
    562   std::vector<std::vector<InstrItinerary> >::iterator
    563       ProcItinListsIter = ProcItinLists.begin();
    564   for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
    565          PE = SchedModels.procModelEnd(); PI != PE; ++PI, ++ProcItinListsIter) {
    566 
    567     Record *ItinsDef = PI->ItinsDef;
    568     if (!ItinsDefSet.insert(ItinsDef))
    569       continue;
    570 
    571     // Get processor itinerary name
    572     const std::string &Name = ItinsDef->getName();
    573 
    574     // Get the itinerary list for the processor.
    575     assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator");
    576     std::vector<InstrItinerary> &ItinList = *ProcItinListsIter;
    577 
    578     OS << "\n";
    579     OS << "static const llvm::InstrItinerary ";
    580     if (ItinList.empty()) {
    581       OS << '*' << Name << " = 0;\n";
    582       continue;
    583     }
    584 
    585     // Begin processor itinerary table
    586     OS << Name << "[] = {\n";
    587 
    588     // For each itinerary class in CodeGenSchedClass::Index order.
    589     for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
    590       InstrItinerary &Intinerary = ItinList[j];
    591 
    592       // Emit Itinerary in the form of
    593       // { firstStage, lastStage, firstCycle, lastCycle } // index
    594       OS << "  { " <<
    595         Intinerary.NumMicroOps << ", " <<
    596         Intinerary.FirstStage << ", " <<
    597         Intinerary.LastStage << ", " <<
    598         Intinerary.FirstOperandCycle << ", " <<
    599         Intinerary.LastOperandCycle << " }" <<
    600         ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n";
    601     }
    602     // End processor itinerary table
    603     OS << "  { 0, ~0U, ~0U, ~0U, ~0U } // end marker\n";
    604     OS << "};\n";
    605   }
    606 }
    607 
    608 // Emit either the value defined in the TableGen Record, or the default
    609 // value defined in the C++ header. The Record is null if the processor does not
    610 // define a model.
    611 void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R,
    612                                          const char *Name, char Separator) {
    613   OS << "  ";
    614   int V = R ? R->getValueAsInt(Name) : -1;
    615   if (V >= 0)
    616     OS << V << Separator << " // " << Name;
    617   else
    618     OS << "MCSchedModel::Default" << Name << Separator;
    619   OS << '\n';
    620 }
    621 
    622 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
    623                                               raw_ostream &OS) {
    624   char Sep = ProcModel.ProcResourceDefs.empty() ? ' ' : ',';
    625 
    626   OS << "\n// {Name, NumUnits, SuperIdx, IsBuffered}\n";
    627   OS << "static const llvm::MCProcResourceDesc "
    628      << ProcModel.ModelName << "ProcResources" << "[] = {\n"
    629      << "  {DBGFIELD(\"InvalidUnit\")     0, 0, 0}" << Sep << "\n";
    630 
    631   for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
    632     Record *PRDef = ProcModel.ProcResourceDefs[i];
    633 
    634     Record *SuperDef = 0;
    635     unsigned SuperIdx = 0;
    636     unsigned NumUnits = 0;
    637     bool IsBuffered = true;
    638     if (PRDef->isSubClassOf("ProcResGroup")) {
    639       RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
    640       for (RecIter RUI = ResUnits.begin(), RUE = ResUnits.end();
    641            RUI != RUE; ++RUI) {
    642         if (!NumUnits)
    643           IsBuffered = (*RUI)->getValueAsBit("Buffered");
    644         else if(IsBuffered != (*RUI)->getValueAsBit("Buffered"))
    645           PrintFatalError(PRDef->getLoc(),
    646                           "Mixing buffered and unbuffered resources.");
    647         NumUnits += (*RUI)->getValueAsInt("NumUnits");
    648       }
    649     }
    650     else {
    651       // Find the SuperIdx
    652       if (PRDef->getValueInit("Super")->isComplete()) {
    653         SuperDef = SchedModels.findProcResUnits(
    654           PRDef->getValueAsDef("Super"), ProcModel);
    655         SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
    656       }
    657       NumUnits = PRDef->getValueAsInt("NumUnits");
    658       IsBuffered = PRDef->getValueAsBit("Buffered");
    659     }
    660     // Emit the ProcResourceDesc
    661     if (i+1 == e)
    662       Sep = ' ';
    663     OS << "  {DBGFIELD(\"" << PRDef->getName() << "\") ";
    664     if (PRDef->getName().size() < 15)
    665       OS.indent(15 - PRDef->getName().size());
    666     OS << NumUnits << ", " << SuperIdx << ", "
    667        << IsBuffered << "}" << Sep << " // #" << i+1;
    668     if (SuperDef)
    669       OS << ", Super=" << SuperDef->getName();
    670     OS << "\n";
    671   }
    672   OS << "};\n";
    673 }
    674 
    675 // Find the WriteRes Record that defines processor resources for this
    676 // SchedWrite.
    677 Record *SubtargetEmitter::FindWriteResources(
    678   const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) {
    679 
    680   // Check if the SchedWrite is already subtarget-specific and directly
    681   // specifies a set of processor resources.
    682   if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes"))
    683     return SchedWrite.TheDef;
    684 
    685   Record *AliasDef = 0;
    686   for (RecIter AI = SchedWrite.Aliases.begin(), AE = SchedWrite.Aliases.end();
    687        AI != AE; ++AI) {
    688     const CodeGenSchedRW &AliasRW =
    689       SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
    690     if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
    691       Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
    692       if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
    693         continue;
    694     }
    695     if (AliasDef)
    696       PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
    697                     "defined for processor " + ProcModel.ModelName +
    698                     " Ensure only one SchedAlias exists per RW.");
    699     AliasDef = AliasRW.TheDef;
    700   }
    701   if (AliasDef && AliasDef->isSubClassOf("SchedWriteRes"))
    702     return AliasDef;
    703 
    704   // Check this processor's list of write resources.
    705   Record *ResDef = 0;
    706   for (RecIter WRI = ProcModel.WriteResDefs.begin(),
    707          WRE = ProcModel.WriteResDefs.end(); WRI != WRE; ++WRI) {
    708     if (!(*WRI)->isSubClassOf("WriteRes"))
    709       continue;
    710     if (AliasDef == (*WRI)->getValueAsDef("WriteType")
    711         || SchedWrite.TheDef == (*WRI)->getValueAsDef("WriteType")) {
    712       if (ResDef) {
    713         PrintFatalError((*WRI)->getLoc(), "Resources are defined for both "
    714                       "SchedWrite and its alias on processor " +
    715                       ProcModel.ModelName);
    716       }
    717       ResDef = *WRI;
    718     }
    719   }
    720   // TODO: If ProcModel has a base model (previous generation processor),
    721   // then call FindWriteResources recursively with that model here.
    722   if (!ResDef) {
    723     PrintFatalError(ProcModel.ModelDef->getLoc(),
    724                   std::string("Processor does not define resources for ")
    725                   + SchedWrite.TheDef->getName());
    726   }
    727   return ResDef;
    728 }
    729 
    730 /// Find the ReadAdvance record for the given SchedRead on this processor or
    731 /// return NULL.
    732 Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
    733                                           const CodeGenProcModel &ProcModel) {
    734   // Check for SchedReads that directly specify a ReadAdvance.
    735   if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance"))
    736     return SchedRead.TheDef;
    737 
    738   // Check this processor's list of aliases for SchedRead.
    739   Record *AliasDef = 0;
    740   for (RecIter AI = SchedRead.Aliases.begin(), AE = SchedRead.Aliases.end();
    741        AI != AE; ++AI) {
    742     const CodeGenSchedRW &AliasRW =
    743       SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
    744     if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
    745       Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
    746       if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
    747         continue;
    748     }
    749     if (AliasDef)
    750       PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
    751                     "defined for processor " + ProcModel.ModelName +
    752                     " Ensure only one SchedAlias exists per RW.");
    753     AliasDef = AliasRW.TheDef;
    754   }
    755   if (AliasDef && AliasDef->isSubClassOf("SchedReadAdvance"))
    756     return AliasDef;
    757 
    758   // Check this processor's ReadAdvanceList.
    759   Record *ResDef = 0;
    760   for (RecIter RAI = ProcModel.ReadAdvanceDefs.begin(),
    761          RAE = ProcModel.ReadAdvanceDefs.end(); RAI != RAE; ++RAI) {
    762     if (!(*RAI)->isSubClassOf("ReadAdvance"))
    763       continue;
    764     if (AliasDef == (*RAI)->getValueAsDef("ReadType")
    765         || SchedRead.TheDef == (*RAI)->getValueAsDef("ReadType")) {
    766       if (ResDef) {
    767         PrintFatalError((*RAI)->getLoc(), "Resources are defined for both "
    768                       "SchedRead and its alias on processor " +
    769                       ProcModel.ModelName);
    770       }
    771       ResDef = *RAI;
    772     }
    773   }
    774   // TODO: If ProcModel has a base model (previous generation processor),
    775   // then call FindReadAdvance recursively with that model here.
    776   if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") {
    777     PrintFatalError(ProcModel.ModelDef->getLoc(),
    778                   std::string("Processor does not define resources for ")
    779                   + SchedRead.TheDef->getName());
    780   }
    781   return ResDef;
    782 }
    783 
    784 // Expand an explicit list of processor resources into a full list of implied
    785 // resource groups that cover them.
    786 //
    787 // FIXME: Effectively consider a super-resource a group that include all of its
    788 // subresources to allow mixing and matching super-resources and groups.
    789 //
    790 // FIXME: Warn if two overlapping groups don't have a common supergroup.
    791 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec,
    792                                            std::vector<int64_t> &Cycles,
    793                                            const CodeGenProcModel &ProcModel) {
    794   // Default to 1 resource cycle.
    795   Cycles.resize(PRVec.size(), 1);
    796   for (unsigned i = 0, e = PRVec.size(); i != e; ++i) {
    797     RecVec SubResources;
    798     if (PRVec[i]->isSubClassOf("ProcResGroup")) {
    799       SubResources = PRVec[i]->getValueAsListOfDefs("Resources");
    800       std::sort(SubResources.begin(), SubResources.end(), LessRecord());
    801     }
    802     else {
    803       SubResources.push_back(PRVec[i]);
    804     }
    805     for (RecIter PRI = ProcModel.ProcResourceDefs.begin(),
    806            PRE = ProcModel.ProcResourceDefs.end();
    807          PRI != PRE; ++PRI) {
    808       if (*PRI == PRVec[i] || !(*PRI)->isSubClassOf("ProcResGroup"))
    809         continue;
    810       RecVec SuperResources = (*PRI)->getValueAsListOfDefs("Resources");
    811       std::sort(SuperResources.begin(), SuperResources.end(), LessRecord());
    812       RecIter SubI = SubResources.begin(), SubE = SubResources.end();
    813       RecIter SuperI = SuperResources.begin(), SuperE = SuperResources.end();
    814       for ( ; SubI != SubE && SuperI != SuperE; ++SuperI) {
    815         if (*SubI < *SuperI)
    816           break;
    817         else if (*SuperI < *SubI)
    818           continue;
    819         ++SubI;
    820       }
    821       if (SubI == SubE) {
    822         PRVec.push_back(*PRI);
    823         Cycles.push_back(Cycles[i]);
    824       }
    825     }
    826   }
    827 }
    828 
    829 // Generate the SchedClass table for this processor and update global
    830 // tables. Must be called for each processor in order.
    831 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
    832                                            SchedClassTables &SchedTables) {
    833   SchedTables.ProcSchedClasses.resize(SchedTables.ProcSchedClasses.size() + 1);
    834   if (!ProcModel.hasInstrSchedModel())
    835     return;
    836 
    837   std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back();
    838   for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(),
    839          SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) {
    840     DEBUG(SCI->dump(&SchedModels));
    841 
    842     SCTab.resize(SCTab.size() + 1);
    843     MCSchedClassDesc &SCDesc = SCTab.back();
    844     // SCDesc.Name is guarded by NDEBUG
    845     SCDesc.NumMicroOps = 0;
    846     SCDesc.BeginGroup = false;
    847     SCDesc.EndGroup = false;
    848     SCDesc.WriteProcResIdx = 0;
    849     SCDesc.WriteLatencyIdx = 0;
    850     SCDesc.ReadAdvanceIdx = 0;
    851 
    852     // A Variant SchedClass has no resources of its own.
    853     if (!SCI->Transitions.empty()) {
    854       SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps;
    855       continue;
    856     }
    857 
    858     // Determine if the SchedClass is actually reachable on this processor. If
    859     // not don't try to locate the processor resources, it will fail.
    860     // If ProcIndices contains 0, this class applies to all processors.
    861     assert(!SCI->ProcIndices.empty() && "expect at least one procidx");
    862     if (SCI->ProcIndices[0] != 0) {
    863       IdxIter PIPos = std::find(SCI->ProcIndices.begin(),
    864                                 SCI->ProcIndices.end(), ProcModel.Index);
    865       if (PIPos == SCI->ProcIndices.end())
    866         continue;
    867     }
    868     IdxVec Writes = SCI->Writes;
    869     IdxVec Reads = SCI->Reads;
    870     if (!SCI->InstRWs.empty()) {
    871       // This class has a default ReadWrite list which can be overriden by
    872       // InstRW definitions.
    873       Record *RWDef = 0;
    874       for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end();
    875            RWI != RWE; ++RWI) {
    876         Record *RWModelDef = (*RWI)->getValueAsDef("SchedModel");
    877         if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) {
    878           RWDef = *RWI;
    879           break;
    880         }
    881       }
    882       if (RWDef) {
    883         Writes.clear();
    884         Reads.clear();
    885         SchedModels.findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),
    886                             Writes, Reads);
    887       }
    888     }
    889     if (Writes.empty()) {
    890       // Check this processor's itinerary class resources.
    891       for (RecIter II = ProcModel.ItinRWDefs.begin(),
    892              IE = ProcModel.ItinRWDefs.end(); II != IE; ++II) {
    893         RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");
    894         if (std::find(Matched.begin(), Matched.end(), SCI->ItinClassDef)
    895             != Matched.end()) {
    896           SchedModels.findRWs((*II)->getValueAsListOfDefs("OperandReadWrites"),
    897                               Writes, Reads);
    898           break;
    899         }
    900       }
    901       if (Writes.empty()) {
    902         DEBUG(dbgs() << ProcModel.ModelName
    903               << " does not have resources for class " << SCI->Name << '\n');
    904       }
    905     }
    906     // Sum resources across all operand writes.
    907     std::vector<MCWriteProcResEntry> WriteProcResources;
    908     std::vector<MCWriteLatencyEntry> WriteLatencies;
    909     std::vector<std::string> WriterNames;
    910     std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
    911     for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) {
    912       IdxVec WriteSeq;
    913       SchedModels.expandRWSeqForProc(*WI, WriteSeq, /*IsRead=*/false,
    914                                      ProcModel);
    915 
    916       // For each operand, create a latency entry.
    917       MCWriteLatencyEntry WLEntry;
    918       WLEntry.Cycles = 0;
    919       unsigned WriteID = WriteSeq.back();
    920       WriterNames.push_back(SchedModels.getSchedWrite(WriteID).Name);
    921       // If this Write is not referenced by a ReadAdvance, don't distinguish it
    922       // from other WriteLatency entries.
    923       if (!SchedModels.hasReadOfWrite(
    924             SchedModels.getSchedWrite(WriteID).TheDef)) {
    925         WriteID = 0;
    926       }
    927       WLEntry.WriteResourceID = WriteID;
    928 
    929       for (IdxIter WSI = WriteSeq.begin(), WSE = WriteSeq.end();
    930            WSI != WSE; ++WSI) {
    931 
    932         Record *WriteRes =
    933           FindWriteResources(SchedModels.getSchedWrite(*WSI), ProcModel);
    934 
    935         // Mark the parent class as invalid for unsupported write types.
    936         if (WriteRes->getValueAsBit("Unsupported")) {
    937           SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
    938           break;
    939         }
    940         WLEntry.Cycles += WriteRes->getValueAsInt("Latency");
    941         SCDesc.NumMicroOps += WriteRes->getValueAsInt("NumMicroOps");
    942         SCDesc.BeginGroup |= WriteRes->getValueAsBit("BeginGroup");
    943         SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup");
    944 
    945         // Create an entry for each ProcResource listed in WriteRes.
    946         RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources");
    947         std::vector<int64_t> Cycles =
    948           WriteRes->getValueAsListOfInts("ResourceCycles");
    949 
    950         ExpandProcResources(PRVec, Cycles, ProcModel);
    951 
    952         for (unsigned PRIdx = 0, PREnd = PRVec.size();
    953              PRIdx != PREnd; ++PRIdx) {
    954           MCWriteProcResEntry WPREntry;
    955           WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);
    956           assert(WPREntry.ProcResourceIdx && "Bad ProcResourceIdx");
    957           WPREntry.Cycles = Cycles[PRIdx];
    958           // If this resource is already used in this sequence, add the current
    959           // entry's cycles so that the same resource appears to be used
    960           // serially, rather than multiple parallel uses. This is important for
    961           // in-order machine where the resource consumption is a hazard.
    962           unsigned WPRIdx = 0, WPREnd = WriteProcResources.size();
    963           for( ; WPRIdx != WPREnd; ++WPRIdx) {
    964             if (WriteProcResources[WPRIdx].ProcResourceIdx
    965                 == WPREntry.ProcResourceIdx) {
    966               WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles;
    967               break;
    968             }
    969           }
    970           if (WPRIdx == WPREnd)
    971             WriteProcResources.push_back(WPREntry);
    972         }
    973       }
    974       WriteLatencies.push_back(WLEntry);
    975     }
    976     // Create an entry for each operand Read in this SchedClass.
    977     // Entries must be sorted first by UseIdx then by WriteResourceID.
    978     for (unsigned UseIdx = 0, EndIdx = Reads.size();
    979          UseIdx != EndIdx; ++UseIdx) {
    980       Record *ReadAdvance =
    981         FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
    982       if (!ReadAdvance)
    983         continue;
    984 
    985       // Mark the parent class as invalid for unsupported write types.
    986       if (ReadAdvance->getValueAsBit("Unsupported")) {
    987         SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
    988         break;
    989       }
    990       RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites");
    991       IdxVec WriteIDs;
    992       if (ValidWrites.empty())
    993         WriteIDs.push_back(0);
    994       else {
    995         for (RecIter VWI = ValidWrites.begin(), VWE = ValidWrites.end();
    996              VWI != VWE; ++VWI) {
    997           WriteIDs.push_back(SchedModels.getSchedRWIdx(*VWI, /*IsRead=*/false));
    998         }
    999       }
   1000       std::sort(WriteIDs.begin(), WriteIDs.end());
   1001       for(IdxIter WI = WriteIDs.begin(), WE = WriteIDs.end(); WI != WE; ++WI) {
   1002         MCReadAdvanceEntry RAEntry;
   1003         RAEntry.UseIdx = UseIdx;
   1004         RAEntry.WriteResourceID = *WI;
   1005         RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles");
   1006         ReadAdvanceEntries.push_back(RAEntry);
   1007       }
   1008     }
   1009     if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
   1010       WriteProcResources.clear();
   1011       WriteLatencies.clear();
   1012       ReadAdvanceEntries.clear();
   1013     }
   1014     // Add the information for this SchedClass to the global tables using basic
   1015     // compression.
   1016     //
   1017     // WritePrecRes entries are sorted by ProcResIdx.
   1018     std::sort(WriteProcResources.begin(), WriteProcResources.end(),
   1019               LessWriteProcResources());
   1020 
   1021     SCDesc.NumWriteProcResEntries = WriteProcResources.size();
   1022     std::vector<MCWriteProcResEntry>::iterator WPRPos =
   1023       std::search(SchedTables.WriteProcResources.begin(),
   1024                   SchedTables.WriteProcResources.end(),
   1025                   WriteProcResources.begin(), WriteProcResources.end());
   1026     if (WPRPos != SchedTables.WriteProcResources.end())
   1027       SCDesc.WriteProcResIdx = WPRPos - SchedTables.WriteProcResources.begin();
   1028     else {
   1029       SCDesc.WriteProcResIdx = SchedTables.WriteProcResources.size();
   1030       SchedTables.WriteProcResources.insert(WPRPos, WriteProcResources.begin(),
   1031                                             WriteProcResources.end());
   1032     }
   1033     // Latency entries must remain in operand order.
   1034     SCDesc.NumWriteLatencyEntries = WriteLatencies.size();
   1035     std::vector<MCWriteLatencyEntry>::iterator WLPos =
   1036       std::search(SchedTables.WriteLatencies.begin(),
   1037                   SchedTables.WriteLatencies.end(),
   1038                   WriteLatencies.begin(), WriteLatencies.end());
   1039     if (WLPos != SchedTables.WriteLatencies.end()) {
   1040       unsigned idx = WLPos - SchedTables.WriteLatencies.begin();
   1041       SCDesc.WriteLatencyIdx = idx;
   1042       for (unsigned i = 0, e = WriteLatencies.size(); i < e; ++i)
   1043         if (SchedTables.WriterNames[idx + i].find(WriterNames[i]) ==
   1044             std::string::npos) {
   1045           SchedTables.WriterNames[idx + i] += std::string("_") + WriterNames[i];
   1046         }
   1047     }
   1048     else {
   1049       SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size();
   1050       SchedTables.WriteLatencies.insert(SchedTables.WriteLatencies.end(),
   1051                                         WriteLatencies.begin(),
   1052                                         WriteLatencies.end());
   1053       SchedTables.WriterNames.insert(SchedTables.WriterNames.end(),
   1054                                      WriterNames.begin(), WriterNames.end());
   1055     }
   1056     // ReadAdvanceEntries must remain in operand order.
   1057     SCDesc.NumReadAdvanceEntries = ReadAdvanceEntries.size();
   1058     std::vector<MCReadAdvanceEntry>::iterator RAPos =
   1059       std::search(SchedTables.ReadAdvanceEntries.begin(),
   1060                   SchedTables.ReadAdvanceEntries.end(),
   1061                   ReadAdvanceEntries.begin(), ReadAdvanceEntries.end());
   1062     if (RAPos != SchedTables.ReadAdvanceEntries.end())
   1063       SCDesc.ReadAdvanceIdx = RAPos - SchedTables.ReadAdvanceEntries.begin();
   1064     else {
   1065       SCDesc.ReadAdvanceIdx = SchedTables.ReadAdvanceEntries.size();
   1066       SchedTables.ReadAdvanceEntries.insert(RAPos, ReadAdvanceEntries.begin(),
   1067                                             ReadAdvanceEntries.end());
   1068     }
   1069   }
   1070 }
   1071 
   1072 // Emit SchedClass tables for all processors and associated global tables.
   1073 void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
   1074                                             raw_ostream &OS) {
   1075   // Emit global WriteProcResTable.
   1076   OS << "\n// {ProcResourceIdx, Cycles}\n"
   1077      << "extern const llvm::MCWriteProcResEntry "
   1078      << Target << "WriteProcResTable[] = {\n"
   1079      << "  { 0,  0}, // Invalid\n";
   1080   for (unsigned WPRIdx = 1, WPREnd = SchedTables.WriteProcResources.size();
   1081        WPRIdx != WPREnd; ++WPRIdx) {
   1082     MCWriteProcResEntry &WPREntry = SchedTables.WriteProcResources[WPRIdx];
   1083     OS << "  {" << format("%2d", WPREntry.ProcResourceIdx) << ", "
   1084        << format("%2d", WPREntry.Cycles) << "}";
   1085     if (WPRIdx + 1 < WPREnd)
   1086       OS << ',';
   1087     OS << " // #" << WPRIdx << '\n';
   1088   }
   1089   OS << "}; // " << Target << "WriteProcResTable\n";
   1090 
   1091   // Emit global WriteLatencyTable.
   1092   OS << "\n// {Cycles, WriteResourceID}\n"
   1093      << "extern const llvm::MCWriteLatencyEntry "
   1094      << Target << "WriteLatencyTable[] = {\n"
   1095      << "  { 0,  0}, // Invalid\n";
   1096   for (unsigned WLIdx = 1, WLEnd = SchedTables.WriteLatencies.size();
   1097        WLIdx != WLEnd; ++WLIdx) {
   1098     MCWriteLatencyEntry &WLEntry = SchedTables.WriteLatencies[WLIdx];
   1099     OS << "  {" << format("%2d", WLEntry.Cycles) << ", "
   1100        << format("%2d", WLEntry.WriteResourceID) << "}";
   1101     if (WLIdx + 1 < WLEnd)
   1102       OS << ',';
   1103     OS << " // #" << WLIdx << " " << SchedTables.WriterNames[WLIdx] << '\n';
   1104   }
   1105   OS << "}; // " << Target << "WriteLatencyTable\n";
   1106 
   1107   // Emit global ReadAdvanceTable.
   1108   OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"
   1109      << "extern const llvm::MCReadAdvanceEntry "
   1110      << Target << "ReadAdvanceTable[] = {\n"
   1111      << "  {0,  0,  0}, // Invalid\n";
   1112   for (unsigned RAIdx = 1, RAEnd = SchedTables.ReadAdvanceEntries.size();
   1113        RAIdx != RAEnd; ++RAIdx) {
   1114     MCReadAdvanceEntry &RAEntry = SchedTables.ReadAdvanceEntries[RAIdx];
   1115     OS << "  {" << RAEntry.UseIdx << ", "
   1116        << format("%2d", RAEntry.WriteResourceID) << ", "
   1117        << format("%2d", RAEntry.Cycles) << "}";
   1118     if (RAIdx + 1 < RAEnd)
   1119       OS << ',';
   1120     OS << " // #" << RAIdx << '\n';
   1121   }
   1122   OS << "}; // " << Target << "ReadAdvanceTable\n";
   1123 
   1124   // Emit a SchedClass table for each processor.
   1125   for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
   1126          PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
   1127     if (!PI->hasInstrSchedModel())
   1128       continue;
   1129 
   1130     std::vector<MCSchedClassDesc> &SCTab =
   1131       SchedTables.ProcSchedClasses[1 + (PI - SchedModels.procModelBegin())];
   1132 
   1133     OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup,"
   1134        << " WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}\n";
   1135     OS << "static const llvm::MCSchedClassDesc "
   1136        << PI->ModelName << "SchedClasses[] = {\n";
   1137 
   1138     // The first class is always invalid. We no way to distinguish it except by
   1139     // name and position.
   1140     assert(SchedModels.getSchedClass(0).Name == "NoInstrModel"
   1141            && "invalid class not first");
   1142     OS << "  {DBGFIELD(\"InvalidSchedClass\")  "
   1143        << MCSchedClassDesc::InvalidNumMicroOps
   1144        << ", 0, 0,  0, 0,  0, 0,  0, 0},\n";
   1145 
   1146     for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) {
   1147       MCSchedClassDesc &MCDesc = SCTab[SCIdx];
   1148       const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx);
   1149       OS << "  {DBGFIELD(\"" << SchedClass.Name << "\") ";
   1150       if (SchedClass.Name.size() < 18)
   1151         OS.indent(18 - SchedClass.Name.size());
   1152       OS << MCDesc.NumMicroOps
   1153          << ", " << MCDesc.BeginGroup << ", " << MCDesc.EndGroup
   1154          << ", " << format("%2d", MCDesc.WriteProcResIdx)
   1155          << ", " << MCDesc.NumWriteProcResEntries
   1156          << ", " << format("%2d", MCDesc.WriteLatencyIdx)
   1157          << ", " << MCDesc.NumWriteLatencyEntries
   1158          << ", " << format("%2d", MCDesc.ReadAdvanceIdx)
   1159          << ", " << MCDesc.NumReadAdvanceEntries << "}";
   1160       if (SCIdx + 1 < SCEnd)
   1161         OS << ',';
   1162       OS << " // #" << SCIdx << '\n';
   1163     }
   1164     OS << "}; // " << PI->ModelName << "SchedClasses\n";
   1165   }
   1166 }
   1167 
   1168 void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
   1169   // For each processor model.
   1170   for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
   1171          PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
   1172     // Emit processor resource table.
   1173     if (PI->hasInstrSchedModel())
   1174       EmitProcessorResources(*PI, OS);
   1175     else if(!PI->ProcResourceDefs.empty())
   1176       PrintFatalError(PI->ModelDef->getLoc(), "SchedMachineModel defines "
   1177                     "ProcResources without defining WriteRes SchedWriteRes");
   1178 
   1179     // Begin processor itinerary properties
   1180     OS << "\n";
   1181     OS << "static const llvm::MCSchedModel " << PI->ModelName << "(\n";
   1182     EmitProcessorProp(OS, PI->ModelDef, "IssueWidth", ',');
   1183     EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ',');
   1184     EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ',');
   1185     EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ',');
   1186     EmitProcessorProp(OS, PI->ModelDef, "ILPWindow", ',');
   1187     EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ',');
   1188     OS << "  " << PI->Index << ", // Processor ID\n";
   1189     if (PI->hasInstrSchedModel())
   1190       OS << "  " << PI->ModelName << "ProcResources" << ",\n"
   1191          << "  " << PI->ModelName << "SchedClasses" << ",\n"
   1192          << "  " << PI->ProcResourceDefs.size()+1 << ",\n"
   1193          << "  " << (SchedModels.schedClassEnd()
   1194                      - SchedModels.schedClassBegin()) << ",\n";
   1195     else
   1196       OS << "  0, 0, 0, 0, // No instruction-level machine model.\n";
   1197     if (SchedModels.hasItineraries())
   1198       OS << "  " << PI->ItinsDef->getName() << ");\n";
   1199     else
   1200       OS << "  0); // No Itinerary\n";
   1201   }
   1202 }
   1203 
   1204 //
   1205 // EmitProcessorLookup - generate cpu name to itinerary lookup table.
   1206 //
   1207 void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
   1208   // Gather and sort processor information
   1209   std::vector<Record*> ProcessorList =
   1210                           Records.getAllDerivedDefinitions("Processor");
   1211   std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
   1212 
   1213   // Begin processor table
   1214   OS << "\n";
   1215   OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
   1216      << "extern const llvm::SubtargetInfoKV "
   1217      << Target << "ProcSchedKV[] = {\n";
   1218 
   1219   // For each processor
   1220   for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
   1221     // Next processor
   1222     Record *Processor = ProcessorList[i];
   1223 
   1224     const std::string &Name = Processor->getValueAsString("Name");
   1225     const std::string &ProcModelName =
   1226       SchedModels.getModelForProc(Processor).ModelName;
   1227 
   1228     // Emit as { "cpu", procinit },
   1229     OS << "  { \"" << Name << "\", (const void *)&" << ProcModelName << " }";
   1230 
   1231     // Depending on ''if more in the list'' emit comma
   1232     if (++i < N) OS << ",";
   1233 
   1234     OS << "\n";
   1235   }
   1236 
   1237   // End processor table
   1238   OS << "};\n";
   1239 }
   1240 
   1241 //
   1242 // EmitSchedModel - Emits all scheduling model tables, folding common patterns.
   1243 //
   1244 void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
   1245   OS << "#ifdef DBGFIELD\n"
   1246      << "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n"
   1247      << "#endif\n"
   1248      << "#ifndef NDEBUG\n"
   1249      << "#define DBGFIELD(x) x,\n"
   1250      << "#else\n"
   1251      << "#define DBGFIELD(x)\n"
   1252      << "#endif\n";
   1253 
   1254   if (SchedModels.hasItineraries()) {
   1255     std::vector<std::vector<InstrItinerary> > ProcItinLists;
   1256     // Emit the stage data
   1257     EmitStageAndOperandCycleData(OS, ProcItinLists);
   1258     EmitItineraries(OS, ProcItinLists);
   1259   }
   1260   OS << "\n// ===============================================================\n"
   1261      << "// Data tables for the new per-operand machine model.\n";
   1262 
   1263   SchedClassTables SchedTables;
   1264   for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
   1265          PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
   1266     GenSchedClassTables(*PI, SchedTables);
   1267   }
   1268   EmitSchedClassTables(SchedTables, OS);
   1269 
   1270   // Emit the processor machine model
   1271   EmitProcessorModels(OS);
   1272   // Emit the processor lookup data
   1273   EmitProcessorLookup(OS);
   1274 
   1275   OS << "#undef DBGFIELD";
   1276 }
   1277 
   1278 void SubtargetEmitter::EmitSchedModelHelpers(std::string ClassName,
   1279                                              raw_ostream &OS) {
   1280   OS << "unsigned " << ClassName
   1281      << "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,"
   1282      << " const TargetSchedModel *SchedModel) const {\n";
   1283 
   1284   std::vector<Record*> Prologs = Records.getAllDerivedDefinitions("PredicateProlog");
   1285   std::sort(Prologs.begin(), Prologs.end(), LessRecord());
   1286   for (std::vector<Record*>::const_iterator
   1287          PI = Prologs.begin(), PE = Prologs.end(); PI != PE; ++PI) {
   1288     OS << (*PI)->getValueAsString("Code") << '\n';
   1289   }
   1290   IdxVec VariantClasses;
   1291   for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(),
   1292          SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) {
   1293     if (SCI->Transitions.empty())
   1294       continue;
   1295     VariantClasses.push_back(SCI->Index);
   1296   }
   1297   if (!VariantClasses.empty()) {
   1298     OS << "  switch (SchedClass) {\n";
   1299     for (IdxIter VCI = VariantClasses.begin(), VCE = VariantClasses.end();
   1300          VCI != VCE; ++VCI) {
   1301       const CodeGenSchedClass &SC = SchedModels.getSchedClass(*VCI);
   1302       OS << "  case " << *VCI << ": // " << SC.Name << '\n';
   1303       IdxVec ProcIndices;
   1304       for (std::vector<CodeGenSchedTransition>::const_iterator
   1305              TI = SC.Transitions.begin(), TE = SC.Transitions.end();
   1306            TI != TE; ++TI) {
   1307         IdxVec PI;
   1308         std::set_union(TI->ProcIndices.begin(), TI->ProcIndices.end(),
   1309                        ProcIndices.begin(), ProcIndices.end(),
   1310                        std::back_inserter(PI));
   1311         ProcIndices.swap(PI);
   1312       }
   1313       for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end();
   1314            PI != PE; ++PI) {
   1315         OS << "    ";
   1316         if (*PI != 0)
   1317           OS << "if (SchedModel->getProcessorID() == " << *PI << ") ";
   1318         OS << "{ // " << (SchedModels.procModelBegin() + *PI)->ModelName
   1319            << '\n';
   1320         for (std::vector<CodeGenSchedTransition>::const_iterator
   1321                TI = SC.Transitions.begin(), TE = SC.Transitions.end();
   1322              TI != TE; ++TI) {
   1323           OS << "      if (";
   1324           if (*PI != 0 && !std::count(TI->ProcIndices.begin(),
   1325                                       TI->ProcIndices.end(), *PI)) {
   1326               continue;
   1327           }
   1328           for (RecIter RI = TI->PredTerm.begin(), RE = TI->PredTerm.end();
   1329                RI != RE; ++RI) {
   1330             if (RI != TI->PredTerm.begin())
   1331               OS << "\n          && ";
   1332             OS << "(" << (*RI)->getValueAsString("Predicate") << ")";
   1333           }
   1334           OS << ")\n"
   1335              << "        return " << TI->ToClassIdx << "; // "
   1336              << SchedModels.getSchedClass(TI->ToClassIdx).Name << '\n';
   1337         }
   1338         OS << "    }\n";
   1339         if (*PI == 0)
   1340           break;
   1341       }
   1342       if (SC.isInferred())
   1343         OS << "    return " << SC.Index << ";\n";
   1344       OS << "    break;\n";
   1345     }
   1346     OS << "  };\n";
   1347   }
   1348   OS << "  report_fatal_error(\"Expected a variant SchedClass\");\n"
   1349      << "} // " << ClassName << "::resolveSchedClass\n";
   1350 }
   1351 
   1352 //
   1353 // ParseFeaturesFunction - Produces a subtarget specific function for parsing
   1354 // the subtarget features string.
   1355 //
   1356 void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
   1357                                              unsigned NumFeatures,
   1358                                              unsigned NumProcs) {
   1359   std::vector<Record*> Features =
   1360                        Records.getAllDerivedDefinitions("SubtargetFeature");
   1361   std::sort(Features.begin(), Features.end(), LessRecord());
   1362 
   1363   OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
   1364      << "// subtarget options.\n"
   1365      << "void llvm::";
   1366   OS << Target;
   1367   OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n"
   1368      << "  DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
   1369      << "  DEBUG(dbgs() << \"\\nCPU:\" << CPU << \"\\n\\n\");\n";
   1370 
   1371   if (Features.empty()) {
   1372     OS << "}\n";
   1373     return;
   1374   }
   1375 
   1376   OS << "  InitMCProcessorInfo(CPU, FS);\n"
   1377      << "  uint64_t Bits = getFeatureBits();\n";
   1378 
   1379   for (unsigned i = 0; i < Features.size(); i++) {
   1380     // Next record
   1381     Record *R = Features[i];
   1382     const std::string &Instance = R->getName();
   1383     const std::string &Value = R->getValueAsString("Value");
   1384     const std::string &Attribute = R->getValueAsString("Attribute");
   1385 
   1386     if (Value=="true" || Value=="false")
   1387       OS << "  if ((Bits & " << Target << "::"
   1388          << Instance << ") != 0) "
   1389          << Attribute << " = " << Value << ";\n";
   1390     else
   1391       OS << "  if ((Bits & " << Target << "::"
   1392          << Instance << ") != 0 && "
   1393          << Attribute << " < " << Value << ") "
   1394          << Attribute << " = " << Value << ";\n";
   1395   }
   1396 
   1397   OS << "}\n";
   1398 }
   1399 
   1400 //
   1401 // SubtargetEmitter::run - Main subtarget enumeration emitter.
   1402 //
   1403 void SubtargetEmitter::run(raw_ostream &OS) {
   1404   emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
   1405 
   1406   OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";
   1407   OS << "#undef GET_SUBTARGETINFO_ENUM\n";
   1408 
   1409   OS << "namespace llvm {\n";
   1410   Enumeration(OS, "SubtargetFeature", true);
   1411   OS << "} // End llvm namespace \n";
   1412   OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
   1413 
   1414   OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
   1415   OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";
   1416 
   1417   OS << "namespace llvm {\n";
   1418 #if 0
   1419   OS << "namespace {\n";
   1420 #endif
   1421   unsigned NumFeatures = FeatureKeyValues(OS);
   1422   OS << "\n";
   1423   unsigned NumProcs = CPUKeyValues(OS);
   1424   OS << "\n";
   1425   EmitSchedModel(OS);
   1426   OS << "\n";
   1427 #if 0
   1428   OS << "}\n";
   1429 #endif
   1430 
   1431   // MCInstrInfo initialization routine.
   1432   OS << "static inline void Init" << Target
   1433      << "MCSubtargetInfo(MCSubtargetInfo *II, "
   1434      << "StringRef TT, StringRef CPU, StringRef FS) {\n";
   1435   OS << "  II->InitMCSubtargetInfo(TT, CPU, FS, ";
   1436   if (NumFeatures)
   1437     OS << Target << "FeatureKV, ";
   1438   else
   1439     OS << "0, ";
   1440   if (NumProcs)
   1441     OS << Target << "SubTypeKV, ";
   1442   else
   1443     OS << "0, ";
   1444   OS << '\n'; OS.indent(22);
   1445   OS << Target << "ProcSchedKV, "
   1446      << Target << "WriteProcResTable, "
   1447      << Target << "WriteLatencyTable, "
   1448      << Target << "ReadAdvanceTable, ";
   1449   if (SchedModels.hasItineraries()) {
   1450     OS << '\n'; OS.indent(22);
   1451     OS << Target << "Stages, "
   1452        << Target << "OperandCycles, "
   1453        << Target << "ForwardingPaths, ";
   1454   } else
   1455     OS << "0, 0, 0, ";
   1456   OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
   1457 
   1458   OS << "} // End llvm namespace \n";
   1459 
   1460   OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n";
   1461 
   1462   OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n";
   1463   OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n";
   1464 
   1465   OS << "#include \"llvm/Support/Debug.h\"\n";
   1466   OS << "#include \"llvm/Support/raw_ostream.h\"\n";
   1467   ParseFeaturesFunction(OS, NumFeatures, NumProcs);
   1468 
   1469   OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
   1470 
   1471   // Create a TargetSubtargetInfo subclass to hide the MC layer initialization.
   1472   OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
   1473   OS << "#undef GET_SUBTARGETINFO_HEADER\n";
   1474 
   1475   std::string ClassName = Target + "GenSubtargetInfo";
   1476   OS << "namespace llvm {\n";
   1477   OS << "class DFAPacketizer;\n";
   1478   OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
   1479      << "  explicit " << ClassName << "(StringRef TT, StringRef CPU, "
   1480      << "StringRef FS);\n"
   1481      << "public:\n"
   1482      << "  unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI,"
   1483      << " const TargetSchedModel *SchedModel) const;\n"
   1484      << "  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
   1485      << " const;\n"
   1486      << "};\n";
   1487   OS << "} // End llvm namespace \n";
   1488 
   1489   OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
   1490 
   1491   OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
   1492   OS << "#undef GET_SUBTARGETINFO_CTOR\n";
   1493 
   1494   OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n";
   1495   OS << "namespace llvm {\n";
   1496   OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
   1497   OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n";
   1498   OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n";
   1499   OS << "extern const llvm::MCWriteProcResEntry "
   1500      << Target << "WriteProcResTable[];\n";
   1501   OS << "extern const llvm::MCWriteLatencyEntry "
   1502      << Target << "WriteLatencyTable[];\n";
   1503   OS << "extern const llvm::MCReadAdvanceEntry "
   1504      << Target << "ReadAdvanceTable[];\n";
   1505 
   1506   if (SchedModels.hasItineraries()) {
   1507     OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
   1508     OS << "extern const unsigned " << Target << "OperandCycles[];\n";
   1509     OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
   1510   }
   1511 
   1512   OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, "
   1513      << "StringRef FS)\n"
   1514      << "  : TargetSubtargetInfo() {\n"
   1515      << "  InitMCSubtargetInfo(TT, CPU, FS, ";
   1516   if (NumFeatures)
   1517     OS << Target << "FeatureKV, ";
   1518   else
   1519     OS << "0, ";
   1520   if (NumProcs)
   1521     OS << Target << "SubTypeKV, ";
   1522   else
   1523     OS << "0, ";
   1524   OS << '\n'; OS.indent(22);
   1525   OS << Target << "ProcSchedKV, "
   1526      << Target << "WriteProcResTable, "
   1527      << Target << "WriteLatencyTable, "
   1528      << Target << "ReadAdvanceTable, ";
   1529   OS << '\n'; OS.indent(22);
   1530   if (SchedModels.hasItineraries()) {
   1531     OS << Target << "Stages, "
   1532        << Target << "OperandCycles, "
   1533        << Target << "ForwardingPaths, ";
   1534   } else
   1535     OS << "0, 0, 0, ";
   1536   OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
   1537 
   1538   EmitSchedModelHelpers(ClassName, OS);
   1539 
   1540   OS << "} // End llvm namespace \n";
   1541 
   1542   OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
   1543 }
   1544 
   1545 namespace llvm {
   1546 
   1547 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) {
   1548   CodeGenTarget CGTarget(RK);
   1549   SubtargetEmitter(RK, CGTarget).run(OS);
   1550 }
   1551 
   1552 } // End llvm namespace
   1553