1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, kevink (at) mips.com and Carsten Langgaard, carstenl (at) mips.com 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 12 */ 13 #ifndef _ASM_MIPSREGS_H 14 #define _ASM_MIPSREGS_H 15 16 #include <linux/linkage.h> 17 #include <asm/hazards.h> 18 #include <asm/war.h> 19 20 /* 21 * The following macros are especially useful for __asm__ 22 * inline assembler. 23 */ 24 #ifndef __STR 25 #define __STR(x) #x 26 #endif 27 #ifndef STR 28 #define STR(x) __STR(x) 29 #endif 30 31 /* 32 * Configure language 33 */ 34 #ifdef __ASSEMBLY__ 35 #define _ULCAST_ 36 #else 37 #define _ULCAST_ (unsigned long) 38 #endif 39 40 /* 41 * Coprocessor 0 register names 42 */ 43 #define CP0_INDEX $0 44 #define CP0_RANDOM $1 45 #define CP0_ENTRYLO0 $2 46 #define CP0_ENTRYLO1 $3 47 #define CP0_CONF $3 48 #define CP0_CONTEXT $4 49 #define CP0_PAGEMASK $5 50 #define CP0_WIRED $6 51 #define CP0_INFO $7 52 #define CP0_BADVADDR $8 53 #define CP0_COUNT $9 54 #define CP0_ENTRYHI $10 55 #define CP0_COMPARE $11 56 #define CP0_STATUS $12 57 #define CP0_CAUSE $13 58 #define CP0_EPC $14 59 #define CP0_PRID $15 60 #define CP0_CONFIG $16 61 #define CP0_LLADDR $17 62 #define CP0_WATCHLO $18 63 #define CP0_WATCHHI $19 64 #define CP0_XCONTEXT $20 65 #define CP0_FRAMEMASK $21 66 #define CP0_DIAGNOSTIC $22 67 #define CP0_DEBUG $23 68 #define CP0_DEPC $24 69 #define CP0_PERFORMANCE $25 70 #define CP0_ECC $26 71 #define CP0_CACHEERR $27 72 #define CP0_TAGLO $28 73 #define CP0_TAGHI $29 74 #define CP0_ERROREPC $30 75 #define CP0_DESAVE $31 76 77 /* 78 * R4640/R4650 cp0 register names. These registers are listed 79 * here only for completeness; without MMU these CPUs are not useable 80 * by Linux. A future ELKS port might take make Linux run on them 81 * though ... 82 */ 83 #define CP0_IBASE $0 84 #define CP0_IBOUND $1 85 #define CP0_DBASE $2 86 #define CP0_DBOUND $3 87 #define CP0_CALG $17 88 #define CP0_IWATCH $18 89 #define CP0_DWATCH $19 90 91 /* 92 * Coprocessor 0 Set 1 register names 93 */ 94 #define CP0_S1_DERRADDR0 $26 95 #define CP0_S1_DERRADDR1 $27 96 #define CP0_S1_INTCONTROL $20 97 98 /* 99 * Coprocessor 0 Set 2 register names 100 */ 101 #define CP0_S2_SRSCTL $12 /* MIPSR2 */ 102 103 /* 104 * Coprocessor 0 Set 3 register names 105 */ 106 #define CP0_S3_SRSMAP $12 /* MIPSR2 */ 107 108 /* 109 * TX39 Series 110 */ 111 #define CP0_TX39_CACHE $7 112 113 /* 114 * Coprocessor 1 (FPU) register names 115 */ 116 #define CP1_REVISION $0 117 #define CP1_STATUS $31 118 119 /* 120 * FPU Status Register Values 121 */ 122 /* 123 * Status Register Values 124 */ 125 126 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 127 #define FPU_CSR_COND 0x00800000 /* $fcc0 */ 128 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 129 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 130 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 131 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 132 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 133 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 134 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 135 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 136 137 /* 138 * X the exception cause indicator 139 * E the exception enable 140 * S the sticky/flag bit 141 */ 142 #define FPU_CSR_ALL_X 0x0003f000 143 #define FPU_CSR_UNI_X 0x00020000 144 #define FPU_CSR_INV_X 0x00010000 145 #define FPU_CSR_DIV_X 0x00008000 146 #define FPU_CSR_OVF_X 0x00004000 147 #define FPU_CSR_UDF_X 0x00002000 148 #define FPU_CSR_INE_X 0x00001000 149 150 #define FPU_CSR_ALL_E 0x00000f80 151 #define FPU_CSR_INV_E 0x00000800 152 #define FPU_CSR_DIV_E 0x00000400 153 #define FPU_CSR_OVF_E 0x00000200 154 #define FPU_CSR_UDF_E 0x00000100 155 #define FPU_CSR_INE_E 0x00000080 156 157 #define FPU_CSR_ALL_S 0x0000007c 158 #define FPU_CSR_INV_S 0x00000040 159 #define FPU_CSR_DIV_S 0x00000020 160 #define FPU_CSR_OVF_S 0x00000010 161 #define FPU_CSR_UDF_S 0x00000008 162 #define FPU_CSR_INE_S 0x00000004 163 164 /* rounding mode */ 165 #define FPU_CSR_RN 0x0 /* nearest */ 166 #define FPU_CSR_RZ 0x1 /* towards zero */ 167 #define FPU_CSR_RU 0x2 /* towards +Infinity */ 168 #define FPU_CSR_RD 0x3 /* towards -Infinity */ 169 170 171 /* 172 * Values for PageMask register 173 */ 174 #ifdef CONFIG_CPU_VR41XX 175 176 /* Why doesn't stupidity hurt ... */ 177 178 #define PM_1K 0x00000000 179 #define PM_4K 0x00001800 180 #define PM_16K 0x00007800 181 #define PM_64K 0x0001f800 182 #define PM_256K 0x0007f800 183 184 #else 185 186 #define PM_4K 0x00000000 187 #define PM_16K 0x00006000 188 #define PM_64K 0x0001e000 189 #define PM_256K 0x0007e000 190 #define PM_1M 0x001fe000 191 #define PM_4M 0x007fe000 192 #define PM_16M 0x01ffe000 193 #define PM_64M 0x07ffe000 194 #define PM_256M 0x1fffe000 195 196 #endif 197 198 /* 199 * Default page size for a given kernel configuration 200 */ 201 #ifdef CONFIG_PAGE_SIZE_4KB 202 #define PM_DEFAULT_MASK PM_4K 203 #elif defined(CONFIG_PAGE_SIZE_16KB) 204 #define PM_DEFAULT_MASK PM_16K 205 #elif defined(CONFIG_PAGE_SIZE_64KB) 206 #define PM_DEFAULT_MASK PM_64K 207 #else 208 #error Bad page size configuration! 209 #endif 210 211 212 /* 213 * Values used for computation of new tlb entries 214 */ 215 #define PL_4K 12 216 #define PL_16K 14 217 #define PL_64K 16 218 #define PL_256K 18 219 #define PL_1M 20 220 #define PL_4M 22 221 #define PL_16M 24 222 #define PL_64M 26 223 #define PL_256M 28 224 225 /* 226 * R4x00 interrupt enable / cause bits 227 */ 228 #define IE_SW0 (_ULCAST_(1) << 8) 229 #define IE_SW1 (_ULCAST_(1) << 9) 230 #define IE_IRQ0 (_ULCAST_(1) << 10) 231 #define IE_IRQ1 (_ULCAST_(1) << 11) 232 #define IE_IRQ2 (_ULCAST_(1) << 12) 233 #define IE_IRQ3 (_ULCAST_(1) << 13) 234 #define IE_IRQ4 (_ULCAST_(1) << 14) 235 #define IE_IRQ5 (_ULCAST_(1) << 15) 236 237 /* 238 * R4x00 interrupt cause bits 239 */ 240 #define C_SW0 (_ULCAST_(1) << 8) 241 #define C_SW1 (_ULCAST_(1) << 9) 242 #define C_IRQ0 (_ULCAST_(1) << 10) 243 #define C_IRQ1 (_ULCAST_(1) << 11) 244 #define C_IRQ2 (_ULCAST_(1) << 12) 245 #define C_IRQ3 (_ULCAST_(1) << 13) 246 #define C_IRQ4 (_ULCAST_(1) << 14) 247 #define C_IRQ5 (_ULCAST_(1) << 15) 248 249 /* 250 * Bitfields in the R4xx0 cp0 status register 251 */ 252 #define ST0_IE 0x00000001 253 #define ST0_EXL 0x00000002 254 #define ST0_ERL 0x00000004 255 #define ST0_KSU 0x00000018 256 # define KSU_USER 0x00000010 257 # define KSU_SUPERVISOR 0x00000008 258 # define KSU_KERNEL 0x00000000 259 #define ST0_UX 0x00000020 260 #define ST0_SX 0x00000040 261 #define ST0_KX 0x00000080 262 #define ST0_DE 0x00010000 263 #define ST0_CE 0x00020000 264 265 /* 266 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 267 * cacheops in userspace. This bit exists only on RM7000 and RM9000 268 * processors. 269 */ 270 #define ST0_CO 0x08000000 271 272 /* 273 * Bitfields in the R[23]000 cp0 status register. 274 */ 275 #define ST0_IEC 0x00000001 276 #define ST0_KUC 0x00000002 277 #define ST0_IEP 0x00000004 278 #define ST0_KUP 0x00000008 279 #define ST0_IEO 0x00000010 280 #define ST0_KUO 0x00000020 281 /* bits 6 & 7 are reserved on R[23]000 */ 282 #define ST0_ISC 0x00010000 283 #define ST0_SWC 0x00020000 284 #define ST0_CM 0x00080000 285 286 /* 287 * Bits specific to the R4640/R4650 288 */ 289 #define ST0_UM (_ULCAST_(1) << 4) 290 #define ST0_IL (_ULCAST_(1) << 23) 291 #define ST0_DL (_ULCAST_(1) << 24) 292 293 /* 294 * Enable the MIPS MDMX and DSP ASEs 295 */ 296 #define ST0_MX 0x01000000 297 298 /* 299 * Bitfields in the TX39 family CP0 Configuration Register 3 300 */ 301 #define TX39_CONF_ICS_SHIFT 19 302 #define TX39_CONF_ICS_MASK 0x00380000 303 #define TX39_CONF_ICS_1KB 0x00000000 304 #define TX39_CONF_ICS_2KB 0x00080000 305 #define TX39_CONF_ICS_4KB 0x00100000 306 #define TX39_CONF_ICS_8KB 0x00180000 307 #define TX39_CONF_ICS_16KB 0x00200000 308 309 #define TX39_CONF_DCS_SHIFT 16 310 #define TX39_CONF_DCS_MASK 0x00070000 311 #define TX39_CONF_DCS_1KB 0x00000000 312 #define TX39_CONF_DCS_2KB 0x00010000 313 #define TX39_CONF_DCS_4KB 0x00020000 314 #define TX39_CONF_DCS_8KB 0x00030000 315 #define TX39_CONF_DCS_16KB 0x00040000 316 317 #define TX39_CONF_CWFON 0x00004000 318 #define TX39_CONF_WBON 0x00002000 319 #define TX39_CONF_RF_SHIFT 10 320 #define TX39_CONF_RF_MASK 0x00000c00 321 #define TX39_CONF_DOZE 0x00000200 322 #define TX39_CONF_HALT 0x00000100 323 #define TX39_CONF_LOCK 0x00000080 324 #define TX39_CONF_ICE 0x00000020 325 #define TX39_CONF_DCE 0x00000010 326 #define TX39_CONF_IRSIZE_SHIFT 2 327 #define TX39_CONF_IRSIZE_MASK 0x0000000c 328 #define TX39_CONF_DRSIZE_SHIFT 0 329 #define TX39_CONF_DRSIZE_MASK 0x00000003 330 331 /* 332 * Status register bits available in all MIPS CPUs. 333 */ 334 #define ST0_IM 0x0000ff00 335 #define STATUSB_IP0 8 336 #define STATUSF_IP0 (_ULCAST_(1) << 8) 337 #define STATUSB_IP1 9 338 #define STATUSF_IP1 (_ULCAST_(1) << 9) 339 #define STATUSB_IP2 10 340 #define STATUSF_IP2 (_ULCAST_(1) << 10) 341 #define STATUSB_IP3 11 342 #define STATUSF_IP3 (_ULCAST_(1) << 11) 343 #define STATUSB_IP4 12 344 #define STATUSF_IP4 (_ULCAST_(1) << 12) 345 #define STATUSB_IP5 13 346 #define STATUSF_IP5 (_ULCAST_(1) << 13) 347 #define STATUSB_IP6 14 348 #define STATUSF_IP6 (_ULCAST_(1) << 14) 349 #define STATUSB_IP7 15 350 #define STATUSF_IP7 (_ULCAST_(1) << 15) 351 #define STATUSB_IP8 0 352 #define STATUSF_IP8 (_ULCAST_(1) << 0) 353 #define STATUSB_IP9 1 354 #define STATUSF_IP9 (_ULCAST_(1) << 1) 355 #define STATUSB_IP10 2 356 #define STATUSF_IP10 (_ULCAST_(1) << 2) 357 #define STATUSB_IP11 3 358 #define STATUSF_IP11 (_ULCAST_(1) << 3) 359 #define STATUSB_IP12 4 360 #define STATUSF_IP12 (_ULCAST_(1) << 4) 361 #define STATUSB_IP13 5 362 #define STATUSF_IP13 (_ULCAST_(1) << 5) 363 #define STATUSB_IP14 6 364 #define STATUSF_IP14 (_ULCAST_(1) << 6) 365 #define STATUSB_IP15 7 366 #define STATUSF_IP15 (_ULCAST_(1) << 7) 367 #define ST0_CH 0x00040000 368 #define ST0_SR 0x00100000 369 #define ST0_TS 0x00200000 370 #define ST0_BEV 0x00400000 371 #define ST0_RE 0x02000000 372 #define ST0_FR 0x04000000 373 #define ST0_CU 0xf0000000 374 #define ST0_CU0 0x10000000 375 #define ST0_CU1 0x20000000 376 #define ST0_CU2 0x40000000 377 #define ST0_CU3 0x80000000 378 #define ST0_XX 0x80000000 /* MIPS IV naming */ 379 380 /* 381 * Bitfields and bit numbers in the coprocessor 0 cause register. 382 * 383 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 384 */ 385 #define CAUSEB_EXCCODE 2 386 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 387 #define CAUSEB_IP 8 388 #define CAUSEF_IP (_ULCAST_(255) << 8) 389 #define CAUSEB_IP0 8 390 #define CAUSEF_IP0 (_ULCAST_(1) << 8) 391 #define CAUSEB_IP1 9 392 #define CAUSEF_IP1 (_ULCAST_(1) << 9) 393 #define CAUSEB_IP2 10 394 #define CAUSEF_IP2 (_ULCAST_(1) << 10) 395 #define CAUSEB_IP3 11 396 #define CAUSEF_IP3 (_ULCAST_(1) << 11) 397 #define CAUSEB_IP4 12 398 #define CAUSEF_IP4 (_ULCAST_(1) << 12) 399 #define CAUSEB_IP5 13 400 #define CAUSEF_IP5 (_ULCAST_(1) << 13) 401 #define CAUSEB_IP6 14 402 #define CAUSEF_IP6 (_ULCAST_(1) << 14) 403 #define CAUSEB_IP7 15 404 #define CAUSEF_IP7 (_ULCAST_(1) << 15) 405 #define CAUSEB_IV 23 406 #define CAUSEF_IV (_ULCAST_(1) << 23) 407 #define CAUSEB_CE 28 408 #define CAUSEF_CE (_ULCAST_(3) << 28) 409 #define CAUSEB_BD 31 410 #define CAUSEF_BD (_ULCAST_(1) << 31) 411 412 /* 413 * Bits in the coprocessor 0 config register. 414 */ 415 /* Generic bits. */ 416 #define CONF_CM_CACHABLE_NO_WA 0 417 #define CONF_CM_CACHABLE_WA 1 418 #define CONF_CM_UNCACHED 2 419 #define CONF_CM_CACHABLE_NONCOHERENT 3 420 #define CONF_CM_CACHABLE_CE 4 421 #define CONF_CM_CACHABLE_COW 5 422 #define CONF_CM_CACHABLE_CUW 6 423 #define CONF_CM_CACHABLE_ACCELERATED 7 424 #define CONF_CM_CMASK 7 425 #define CONF_BE (_ULCAST_(1) << 15) 426 427 /* Bits common to various processors. */ 428 #define CONF_CU (_ULCAST_(1) << 3) 429 #define CONF_DB (_ULCAST_(1) << 4) 430 #define CONF_IB (_ULCAST_(1) << 5) 431 #define CONF_DC (_ULCAST_(7) << 6) 432 #define CONF_IC (_ULCAST_(7) << 9) 433 #define CONF_EB (_ULCAST_(1) << 13) 434 #define CONF_EM (_ULCAST_(1) << 14) 435 #define CONF_SM (_ULCAST_(1) << 16) 436 #define CONF_SC (_ULCAST_(1) << 17) 437 #define CONF_EW (_ULCAST_(3) << 18) 438 #define CONF_EP (_ULCAST_(15)<< 24) 439 #define CONF_EC (_ULCAST_(7) << 28) 440 #define CONF_CM (_ULCAST_(1) << 31) 441 442 /* Bits specific to the R4xx0. */ 443 #define R4K_CONF_SW (_ULCAST_(1) << 20) 444 #define R4K_CONF_SS (_ULCAST_(1) << 21) 445 #define R4K_CONF_SB (_ULCAST_(3) << 22) 446 447 /* Bits specific to the R5000. */ 448 #define R5K_CONF_SE (_ULCAST_(1) << 12) 449 #define R5K_CONF_SS (_ULCAST_(3) << 20) 450 451 /* Bits specific to the RM7000. */ 452 #define RM7K_CONF_SE (_ULCAST_(1) << 3) 453 #define RM7K_CONF_TE (_ULCAST_(1) << 12) 454 #define RM7K_CONF_CLK (_ULCAST_(1) << 16) 455 #define RM7K_CONF_TC (_ULCAST_(1) << 17) 456 #define RM7K_CONF_SI (_ULCAST_(3) << 20) 457 #define RM7K_CONF_SC (_ULCAST_(1) << 31) 458 459 /* Bits specific to the R10000. */ 460 #define R10K_CONF_DN (_ULCAST_(3) << 3) 461 #define R10K_CONF_CT (_ULCAST_(1) << 5) 462 #define R10K_CONF_PE (_ULCAST_(1) << 6) 463 #define R10K_CONF_PM (_ULCAST_(3) << 7) 464 #define R10K_CONF_EC (_ULCAST_(15)<< 9) 465 #define R10K_CONF_SB (_ULCAST_(1) << 13) 466 #define R10K_CONF_SK (_ULCAST_(1) << 14) 467 #define R10K_CONF_SS (_ULCAST_(7) << 16) 468 #define R10K_CONF_SC (_ULCAST_(7) << 19) 469 #define R10K_CONF_DC (_ULCAST_(7) << 26) 470 #define R10K_CONF_IC (_ULCAST_(7) << 29) 471 472 /* Bits specific to the VR41xx. */ 473 #define VR41_CONF_CS (_ULCAST_(1) << 12) 474 #define VR41_CONF_P4K (_ULCAST_(1) << 13) 475 #define VR41_CONF_BP (_ULCAST_(1) << 16) 476 #define VR41_CONF_M16 (_ULCAST_(1) << 20) 477 #define VR41_CONF_AD (_ULCAST_(1) << 23) 478 479 /* Bits specific to the R30xx. */ 480 #define R30XX_CONF_FDM (_ULCAST_(1) << 19) 481 #define R30XX_CONF_REV (_ULCAST_(1) << 22) 482 #define R30XX_CONF_AC (_ULCAST_(1) << 23) 483 #define R30XX_CONF_RF (_ULCAST_(1) << 24) 484 #define R30XX_CONF_HALT (_ULCAST_(1) << 25) 485 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 486 #define R30XX_CONF_DBR (_ULCAST_(1) << 29) 487 #define R30XX_CONF_SB (_ULCAST_(1) << 30) 488 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 489 490 /* Bits specific to the TX49. */ 491 #define TX49_CONF_DC (_ULCAST_(1) << 16) 492 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 493 #define TX49_CONF_HALT (_ULCAST_(1) << 18) 494 #define TX49_CONF_CWFON (_ULCAST_(1) << 27) 495 496 /* Bits specific to the MIPS32/64 PRA. */ 497 #define MIPS_CONF_MT (_ULCAST_(7) << 7) 498 #define MIPS_CONF_AR (_ULCAST_(7) << 10) 499 #define MIPS_CONF_AT (_ULCAST_(3) << 13) 500 #define MIPS_CONF_M (_ULCAST_(1) << 31) 501 502 /* 503 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 504 */ 505 #define MIPS_CONF1_FP (_ULCAST_(1) << 0) 506 #define MIPS_CONF1_EP (_ULCAST_(1) << 1) 507 #define MIPS_CONF1_CA (_ULCAST_(1) << 2) 508 #define MIPS_CONF1_WR (_ULCAST_(1) << 3) 509 #define MIPS_CONF1_PC (_ULCAST_(1) << 4) 510 #define MIPS_CONF1_MD (_ULCAST_(1) << 5) 511 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 512 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) 513 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) 514 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) 515 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 516 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 517 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 518 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) 519 520 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 521 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 522 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 523 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 524 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 525 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 526 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 527 #define MIPS_CONF2_TU (_ULCAST_(7) << 28) 528 529 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 530 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 531 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 532 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 533 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 534 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 535 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 536 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 537 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 538 539 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 540 541 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 542 543 544 /* 545 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 546 */ 547 #define MIPS_FPIR_S (_ULCAST_(1) << 16) 548 #define MIPS_FPIR_D (_ULCAST_(1) << 17) 549 #define MIPS_FPIR_PS (_ULCAST_(1) << 18) 550 #define MIPS_FPIR_3D (_ULCAST_(1) << 19) 551 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 552 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 553 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 554 555 #ifndef __ASSEMBLY__ 556 557 /* 558 * Functions to access the R10000 performance counters. These are basically 559 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 560 * performance counter number encoded into bits 1 ... 5 of the instruction. 561 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 562 * disassembler these will look like an access to sel 0 or 1. 563 */ 564 #define read_r10k_perf_cntr(counter) \ 565 ({ \ 566 unsigned int __res; \ 567 __asm__ __volatile__( \ 568 "mfpc\t%0, %1" \ 569 : "=r" (__res) \ 570 : "i" (counter)); \ 571 \ 572 __res; \ 573 }) 574 575 #define write_r10k_perf_cntr(counter,val) \ 576 do { \ 577 __asm__ __volatile__( \ 578 "mtpc\t%0, %1" \ 579 : \ 580 : "r" (val), "i" (counter)); \ 581 } while (0) 582 583 #define read_r10k_perf_event(counter) \ 584 ({ \ 585 unsigned int __res; \ 586 __asm__ __volatile__( \ 587 "mfps\t%0, %1" \ 588 : "=r" (__res) \ 589 : "i" (counter)); \ 590 \ 591 __res; \ 592 }) 593 594 #define write_r10k_perf_cntl(counter,val) \ 595 do { \ 596 __asm__ __volatile__( \ 597 "mtps\t%0, %1" \ 598 : \ 599 : "r" (val), "i" (counter)); \ 600 } while (0) 601 602 603 /* 604 * Macros to access the system control coprocessor 605 */ 606 607 #define __read_32bit_c0_register(source, sel) \ 608 ({ int __res; \ 609 if (sel == 0) \ 610 __asm__ __volatile__( \ 611 "mfc0\t%0, " #source "\n\t" \ 612 : "=r" (__res)); \ 613 else \ 614 __asm__ __volatile__( \ 615 ".set\tmips32\n\t" \ 616 "mfc0\t%0, " #source ", " #sel "\n\t" \ 617 ".set\tmips0\n\t" \ 618 : "=r" (__res)); \ 619 __res; \ 620 }) 621 622 #define __read_64bit_c0_register(source, sel) \ 623 ({ unsigned long long __res; \ 624 if (sizeof(unsigned long) == 4) \ 625 __res = __read_64bit_c0_split(source, sel); \ 626 else if (sel == 0) \ 627 __asm__ __volatile__( \ 628 ".set\tmips3\n\t" \ 629 "dmfc0\t%0, " #source "\n\t" \ 630 ".set\tmips0" \ 631 : "=r" (__res)); \ 632 else \ 633 __asm__ __volatile__( \ 634 ".set\tmips64\n\t" \ 635 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 636 ".set\tmips0" \ 637 : "=r" (__res)); \ 638 __res; \ 639 }) 640 641 #define __write_32bit_c0_register(register, sel, value) \ 642 do { \ 643 if (sel == 0) \ 644 __asm__ __volatile__( \ 645 "mtc0\t%z0, " #register "\n\t" \ 646 : : "Jr" ((unsigned int)(value))); \ 647 else \ 648 __asm__ __volatile__( \ 649 ".set\tmips32\n\t" \ 650 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 651 ".set\tmips0" \ 652 : : "Jr" ((unsigned int)(value))); \ 653 } while (0) 654 655 #define __write_64bit_c0_register(register, sel, value) \ 656 do { \ 657 if (sizeof(unsigned long) == 4) \ 658 __write_64bit_c0_split(register, sel, value); \ 659 else if (sel == 0) \ 660 __asm__ __volatile__( \ 661 ".set\tmips3\n\t" \ 662 "dmtc0\t%z0, " #register "\n\t" \ 663 ".set\tmips0" \ 664 : : "Jr" (value)); \ 665 else \ 666 __asm__ __volatile__( \ 667 ".set\tmips64\n\t" \ 668 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 669 ".set\tmips0" \ 670 : : "Jr" (value)); \ 671 } while (0) 672 673 #define __read_ulong_c0_register(reg, sel) \ 674 ((sizeof(unsigned long) == 4) ? \ 675 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 676 (unsigned long) __read_64bit_c0_register(reg, sel)) 677 678 #define __write_ulong_c0_register(reg, sel, val) \ 679 do { \ 680 if (sizeof(unsigned long) == 4) \ 681 __write_32bit_c0_register(reg, sel, val); \ 682 else \ 683 __write_64bit_c0_register(reg, sel, val); \ 684 } while (0) 685 686 /* 687 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 688 */ 689 #define __read_32bit_c0_ctrl_register(source) \ 690 ({ int __res; \ 691 __asm__ __volatile__( \ 692 "cfc0\t%0, " #source "\n\t" \ 693 : "=r" (__res)); \ 694 __res; \ 695 }) 696 697 #define __write_32bit_c0_ctrl_register(register, value) \ 698 do { \ 699 __asm__ __volatile__( \ 700 "ctc0\t%z0, " #register "\n\t" \ 701 : : "Jr" ((unsigned int)(value))); \ 702 } while (0) 703 704 /* 705 * These versions are only needed for systems with more than 38 bits of 706 * physical address space running the 32-bit kernel. That's none atm :-) 707 */ 708 #define __read_64bit_c0_split(source, sel) \ 709 ({ \ 710 unsigned long long __val; \ 711 unsigned long __flags; \ 712 \ 713 local_irq_save(__flags); \ 714 if (sel == 0) \ 715 __asm__ __volatile__( \ 716 ".set\tmips64\n\t" \ 717 "dmfc0\t%M0, " #source "\n\t" \ 718 "dsll\t%L0, %M0, 32\n\t" \ 719 "dsrl\t%M0, %M0, 32\n\t" \ 720 "dsrl\t%L0, %L0, 32\n\t" \ 721 ".set\tmips0" \ 722 : "=r" (__val)); \ 723 else \ 724 __asm__ __volatile__( \ 725 ".set\tmips64\n\t" \ 726 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 727 "dsll\t%L0, %M0, 32\n\t" \ 728 "dsrl\t%M0, %M0, 32\n\t" \ 729 "dsrl\t%L0, %L0, 32\n\t" \ 730 ".set\tmips0" \ 731 : "=r" (__val)); \ 732 local_irq_restore(__flags); \ 733 \ 734 __val; \ 735 }) 736 737 #define __write_64bit_c0_split(source, sel, val) \ 738 do { \ 739 unsigned long __flags; \ 740 \ 741 local_irq_save(__flags); \ 742 if (sel == 0) \ 743 __asm__ __volatile__( \ 744 ".set\tmips64\n\t" \ 745 "dsll\t%L0, %L0, 32\n\t" \ 746 "dsrl\t%L0, %L0, 32\n\t" \ 747 "dsll\t%M0, %M0, 32\n\t" \ 748 "or\t%L0, %L0, %M0\n\t" \ 749 "dmtc0\t%L0, " #source "\n\t" \ 750 ".set\tmips0" \ 751 : : "r" (val)); \ 752 else \ 753 __asm__ __volatile__( \ 754 ".set\tmips64\n\t" \ 755 "dsll\t%L0, %L0, 32\n\t" \ 756 "dsrl\t%L0, %L0, 32\n\t" \ 757 "dsll\t%M0, %M0, 32\n\t" \ 758 "or\t%L0, %L0, %M0\n\t" \ 759 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 760 ".set\tmips0" \ 761 : : "r" (val)); \ 762 local_irq_restore(__flags); \ 763 } while (0) 764 765 #define read_c0_index() __read_32bit_c0_register($0, 0) 766 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 767 768 #define read_c0_random() __read_32bit_c0_register($1, 0) 769 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 770 771 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 772 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 773 774 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 775 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 776 777 #define read_c0_conf() __read_32bit_c0_register($3, 0) 778 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 779 780 #define read_c0_context() __read_ulong_c0_register($4, 0) 781 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 782 783 #define read_c0_userlocal() __read_ulong_c0_register($4, 2) 784 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 785 786 #define read_c0_pagemask() __read_32bit_c0_register($5, 0) 787 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 788 789 #define read_c0_wired() __read_32bit_c0_register($6, 0) 790 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 791 792 #define read_c0_info() __read_32bit_c0_register($7, 0) 793 794 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 795 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 796 797 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 798 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 799 800 #define read_c0_count() __read_32bit_c0_register($9, 0) 801 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 802 803 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 804 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 805 806 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 807 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 808 809 #define read_c0_entryhi() __read_ulong_c0_register($10, 0) 810 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 811 812 #define read_c0_compare() __read_32bit_c0_register($11, 0) 813 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 814 815 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 816 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 817 818 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 819 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 820 821 #define read_c0_status() __read_32bit_c0_register($12, 0) 822 #ifdef CONFIG_MIPS_MT_SMTC 823 #define write_c0_status(val) \ 824 do { \ 825 __write_32bit_c0_register($12, 0, val); \ 826 __ehb(); \ 827 } while (0) 828 #else 829 /* 830 * Legacy non-SMTC code, which may be hazardous 831 * but which might not support EHB 832 */ 833 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 834 #endif /* CONFIG_MIPS_MT_SMTC */ 835 836 #define read_c0_cause() __read_32bit_c0_register($13, 0) 837 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 838 839 #define read_c0_epc() __read_ulong_c0_register($14, 0) 840 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 841 842 #define read_c0_prid() __read_32bit_c0_register($15, 0) 843 844 #define read_c0_config() __read_32bit_c0_register($16, 0) 845 #define read_c0_config1() __read_32bit_c0_register($16, 1) 846 #define read_c0_config2() __read_32bit_c0_register($16, 2) 847 #define read_c0_config3() __read_32bit_c0_register($16, 3) 848 #define read_c0_config4() __read_32bit_c0_register($16, 4) 849 #define read_c0_config5() __read_32bit_c0_register($16, 5) 850 #define read_c0_config6() __read_32bit_c0_register($16, 6) 851 #define read_c0_config7() __read_32bit_c0_register($16, 7) 852 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 853 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 854 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 855 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 856 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 857 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 858 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 859 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 860 861 /* 862 * The WatchLo register. There may be upto 8 of them. 863 */ 864 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 865 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 866 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 867 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 868 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 869 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 870 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 871 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 872 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 873 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 874 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 875 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 876 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 877 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 878 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 879 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 880 881 /* 882 * The WatchHi register. There may be upto 8 of them. 883 */ 884 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 885 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 886 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 887 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 888 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 889 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 890 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 891 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 892 893 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 894 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 895 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 896 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 897 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 898 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 899 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 900 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 901 902 #define read_c0_xcontext() __read_ulong_c0_register($20, 0) 903 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 904 905 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 906 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 907 908 #define read_c0_framemask() __read_32bit_c0_register($21, 0) 909 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 910 911 /* RM9000 PerfControl performance counter control register */ 912 #define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) 913 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) 914 915 #define read_c0_diag() __read_32bit_c0_register($22, 0) 916 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 917 918 #define read_c0_diag1() __read_32bit_c0_register($22, 1) 919 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 920 921 #define read_c0_diag2() __read_32bit_c0_register($22, 2) 922 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 923 924 #define read_c0_diag3() __read_32bit_c0_register($22, 3) 925 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 926 927 #define read_c0_diag4() __read_32bit_c0_register($22, 4) 928 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 929 930 #define read_c0_diag5() __read_32bit_c0_register($22, 5) 931 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 932 933 #define read_c0_debug() __read_32bit_c0_register($23, 0) 934 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 935 936 #define read_c0_depc() __read_ulong_c0_register($24, 0) 937 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 938 939 /* 940 * MIPS32 / MIPS64 performance counters 941 */ 942 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 943 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 944 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 945 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 946 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 947 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 948 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 949 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 950 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 951 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 952 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 953 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 954 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 955 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 956 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 957 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 958 959 /* RM9000 PerfCount performance counter register */ 960 #define read_c0_perfcount() __read_64bit_c0_register($25, 0) 961 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) 962 963 #define read_c0_ecc() __read_32bit_c0_register($26, 0) 964 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 965 966 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 967 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 968 969 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 970 971 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 972 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 973 974 #define read_c0_taglo() __read_32bit_c0_register($28, 0) 975 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 976 977 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 978 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 979 980 #define read_c0_taghi() __read_32bit_c0_register($29, 0) 981 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 982 983 #define read_c0_errorepc() __read_ulong_c0_register($30, 0) 984 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 985 986 /* MIPSR2 */ 987 #define read_c0_hwrena() __read_32bit_c0_register($7, 0) 988 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 989 990 #define read_c0_intctl() __read_32bit_c0_register($12, 1) 991 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 992 993 #define read_c0_srsctl() __read_32bit_c0_register($12, 2) 994 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 995 996 #define read_c0_srsmap() __read_32bit_c0_register($12, 3) 997 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 998 999 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1000 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1001 1002 /* 1003 * Macros to access the floating point coprocessor control registers 1004 */ 1005 #define read_32bit_cp1_register(source) \ 1006 ({ int __res; \ 1007 __asm__ __volatile__( \ 1008 ".set\tpush\n\t" \ 1009 ".set\treorder\n\t" \ 1010 "cfc1\t%0,"STR(source)"\n\t" \ 1011 ".set\tpop" \ 1012 : "=r" (__res)); \ 1013 __res;}) 1014 1015 #define rddsp(mask) \ 1016 ({ \ 1017 unsigned int __res; \ 1018 \ 1019 __asm__ __volatile__( \ 1020 " .set push \n" \ 1021 " .set noat \n" \ 1022 " # rddsp $1, %x1 \n" \ 1023 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1024 " move %0, $1 \n" \ 1025 " .set pop \n" \ 1026 : "=r" (__res) \ 1027 : "i" (mask)); \ 1028 __res; \ 1029 }) 1030 1031 #define wrdsp(val, mask) \ 1032 do { \ 1033 __asm__ __volatile__( \ 1034 " .set push \n" \ 1035 " .set noat \n" \ 1036 " move $1, %0 \n" \ 1037 " # wrdsp $1, %x1 \n" \ 1038 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1039 " .set pop \n" \ 1040 : \ 1041 : "r" (val), "i" (mask)); \ 1042 } while (0) 1043 1044 #if 0 /* Need DSP ASE capable assembler ... */ 1045 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) 1046 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) 1047 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) 1048 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;}) 1049 1050 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;}) 1051 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;}) 1052 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;}) 1053 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;}) 1054 1055 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x)) 1056 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x)) 1057 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x)) 1058 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x)) 1059 1060 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x)) 1061 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x)) 1062 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x)) 1063 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x)) 1064 1065 #else 1066 1067 #define mfhi0() \ 1068 ({ \ 1069 unsigned long __treg; \ 1070 \ 1071 __asm__ __volatile__( \ 1072 " .set push \n" \ 1073 " .set noat \n" \ 1074 " # mfhi %0, $ac0 \n" \ 1075 " .word 0x00000810 \n" \ 1076 " move %0, $1 \n" \ 1077 " .set pop \n" \ 1078 : "=r" (__treg)); \ 1079 __treg; \ 1080 }) 1081 1082 #define mfhi1() \ 1083 ({ \ 1084 unsigned long __treg; \ 1085 \ 1086 __asm__ __volatile__( \ 1087 " .set push \n" \ 1088 " .set noat \n" \ 1089 " # mfhi %0, $ac1 \n" \ 1090 " .word 0x00200810 \n" \ 1091 " move %0, $1 \n" \ 1092 " .set pop \n" \ 1093 : "=r" (__treg)); \ 1094 __treg; \ 1095 }) 1096 1097 #define mfhi2() \ 1098 ({ \ 1099 unsigned long __treg; \ 1100 \ 1101 __asm__ __volatile__( \ 1102 " .set push \n" \ 1103 " .set noat \n" \ 1104 " # mfhi %0, $ac2 \n" \ 1105 " .word 0x00400810 \n" \ 1106 " move %0, $1 \n" \ 1107 " .set pop \n" \ 1108 : "=r" (__treg)); \ 1109 __treg; \ 1110 }) 1111 1112 #define mfhi3() \ 1113 ({ \ 1114 unsigned long __treg; \ 1115 \ 1116 __asm__ __volatile__( \ 1117 " .set push \n" \ 1118 " .set noat \n" \ 1119 " # mfhi %0, $ac3 \n" \ 1120 " .word 0x00600810 \n" \ 1121 " move %0, $1 \n" \ 1122 " .set pop \n" \ 1123 : "=r" (__treg)); \ 1124 __treg; \ 1125 }) 1126 1127 #define mflo0() \ 1128 ({ \ 1129 unsigned long __treg; \ 1130 \ 1131 __asm__ __volatile__( \ 1132 " .set push \n" \ 1133 " .set noat \n" \ 1134 " # mflo %0, $ac0 \n" \ 1135 " .word 0x00000812 \n" \ 1136 " move %0, $1 \n" \ 1137 " .set pop \n" \ 1138 : "=r" (__treg)); \ 1139 __treg; \ 1140 }) 1141 1142 #define mflo1() \ 1143 ({ \ 1144 unsigned long __treg; \ 1145 \ 1146 __asm__ __volatile__( \ 1147 " .set push \n" \ 1148 " .set noat \n" \ 1149 " # mflo %0, $ac1 \n" \ 1150 " .word 0x00200812 \n" \ 1151 " move %0, $1 \n" \ 1152 " .set pop \n" \ 1153 : "=r" (__treg)); \ 1154 __treg; \ 1155 }) 1156 1157 #define mflo2() \ 1158 ({ \ 1159 unsigned long __treg; \ 1160 \ 1161 __asm__ __volatile__( \ 1162 " .set push \n" \ 1163 " .set noat \n" \ 1164 " # mflo %0, $ac2 \n" \ 1165 " .word 0x00400812 \n" \ 1166 " move %0, $1 \n" \ 1167 " .set pop \n" \ 1168 : "=r" (__treg)); \ 1169 __treg; \ 1170 }) 1171 1172 #define mflo3() \ 1173 ({ \ 1174 unsigned long __treg; \ 1175 \ 1176 __asm__ __volatile__( \ 1177 " .set push \n" \ 1178 " .set noat \n" \ 1179 " # mflo %0, $ac3 \n" \ 1180 " .word 0x00600812 \n" \ 1181 " move %0, $1 \n" \ 1182 " .set pop \n" \ 1183 : "=r" (__treg)); \ 1184 __treg; \ 1185 }) 1186 1187 #define mthi0(x) \ 1188 do { \ 1189 __asm__ __volatile__( \ 1190 " .set push \n" \ 1191 " .set noat \n" \ 1192 " move $1, %0 \n" \ 1193 " # mthi $1, $ac0 \n" \ 1194 " .word 0x00200011 \n" \ 1195 " .set pop \n" \ 1196 : \ 1197 : "r" (x)); \ 1198 } while (0) 1199 1200 #define mthi1(x) \ 1201 do { \ 1202 __asm__ __volatile__( \ 1203 " .set push \n" \ 1204 " .set noat \n" \ 1205 " move $1, %0 \n" \ 1206 " # mthi $1, $ac1 \n" \ 1207 " .word 0x00200811 \n" \ 1208 " .set pop \n" \ 1209 : \ 1210 : "r" (x)); \ 1211 } while (0) 1212 1213 #define mthi2(x) \ 1214 do { \ 1215 __asm__ __volatile__( \ 1216 " .set push \n" \ 1217 " .set noat \n" \ 1218 " move $1, %0 \n" \ 1219 " # mthi $1, $ac2 \n" \ 1220 " .word 0x00201011 \n" \ 1221 " .set pop \n" \ 1222 : \ 1223 : "r" (x)); \ 1224 } while (0) 1225 1226 #define mthi3(x) \ 1227 do { \ 1228 __asm__ __volatile__( \ 1229 " .set push \n" \ 1230 " .set noat \n" \ 1231 " move $1, %0 \n" \ 1232 " # mthi $1, $ac3 \n" \ 1233 " .word 0x00201811 \n" \ 1234 " .set pop \n" \ 1235 : \ 1236 : "r" (x)); \ 1237 } while (0) 1238 1239 #define mtlo0(x) \ 1240 do { \ 1241 __asm__ __volatile__( \ 1242 " .set push \n" \ 1243 " .set noat \n" \ 1244 " move $1, %0 \n" \ 1245 " # mtlo $1, $ac0 \n" \ 1246 " .word 0x00200013 \n" \ 1247 " .set pop \n" \ 1248 : \ 1249 : "r" (x)); \ 1250 } while (0) 1251 1252 #define mtlo1(x) \ 1253 do { \ 1254 __asm__ __volatile__( \ 1255 " .set push \n" \ 1256 " .set noat \n" \ 1257 " move $1, %0 \n" \ 1258 " # mtlo $1, $ac1 \n" \ 1259 " .word 0x00200813 \n" \ 1260 " .set pop \n" \ 1261 : \ 1262 : "r" (x)); \ 1263 } while (0) 1264 1265 #define mtlo2(x) \ 1266 do { \ 1267 __asm__ __volatile__( \ 1268 " .set push \n" \ 1269 " .set noat \n" \ 1270 " move $1, %0 \n" \ 1271 " # mtlo $1, $ac2 \n" \ 1272 " .word 0x00201013 \n" \ 1273 " .set pop \n" \ 1274 : \ 1275 : "r" (x)); \ 1276 } while (0) 1277 1278 #define mtlo3(x) \ 1279 do { \ 1280 __asm__ __volatile__( \ 1281 " .set push \n" \ 1282 " .set noat \n" \ 1283 " move $1, %0 \n" \ 1284 " # mtlo $1, $ac3 \n" \ 1285 " .word 0x00201813 \n" \ 1286 " .set pop \n" \ 1287 : \ 1288 : "r" (x)); \ 1289 } while (0) 1290 1291 #endif 1292 1293 /* 1294 * TLB operations. 1295 * 1296 * It is responsibility of the caller to take care of any TLB hazards. 1297 */ 1298 static inline void tlb_probe(void) 1299 { 1300 __asm__ __volatile__( 1301 ".set noreorder\n\t" 1302 "tlbp\n\t" 1303 ".set reorder"); 1304 } 1305 1306 static inline void tlb_read(void) 1307 { 1308 #if MIPS34K_MISSED_ITLB_WAR 1309 int res = 0; 1310 1311 __asm__ __volatile__( 1312 " .set push \n" 1313 " .set noreorder \n" 1314 " .set noat \n" 1315 " .set mips32r2 \n" 1316 " .word 0x41610001 # dvpe $1 \n" 1317 " move %0, $1 \n" 1318 " ehb \n" 1319 " .set pop \n" 1320 : "=r" (res)); 1321 1322 instruction_hazard(); 1323 #endif 1324 1325 __asm__ __volatile__( 1326 ".set noreorder\n\t" 1327 "tlbr\n\t" 1328 ".set reorder"); 1329 1330 #if MIPS34K_MISSED_ITLB_WAR 1331 if ((res & _ULCAST_(1))) 1332 __asm__ __volatile__( 1333 " .set push \n" 1334 " .set noreorder \n" 1335 " .set noat \n" 1336 " .set mips32r2 \n" 1337 " .word 0x41600021 # evpe \n" 1338 " ehb \n" 1339 " .set pop \n"); 1340 #endif 1341 } 1342 1343 static inline void tlb_write_indexed(void) 1344 { 1345 __asm__ __volatile__( 1346 ".set noreorder\n\t" 1347 "tlbwi\n\t" 1348 ".set reorder"); 1349 } 1350 1351 static inline void tlb_write_random(void) 1352 { 1353 __asm__ __volatile__( 1354 ".set noreorder\n\t" 1355 "tlbwr\n\t" 1356 ".set reorder"); 1357 } 1358 1359 /* 1360 * Manipulate bits in a c0 register. 1361 */ 1362 #ifndef CONFIG_MIPS_MT_SMTC 1363 /* 1364 * SMTC Linux requires shutting-down microthread scheduling 1365 * during CP0 register read-modify-write sequences. 1366 */ 1367 #define __BUILD_SET_C0(name) \ 1368 static inline unsigned int \ 1369 set_c0_##name(unsigned int set) \ 1370 { \ 1371 unsigned int res; \ 1372 \ 1373 res = read_c0_##name(); \ 1374 res |= set; \ 1375 write_c0_##name(res); \ 1376 \ 1377 return res; \ 1378 } \ 1379 \ 1380 static inline unsigned int \ 1381 clear_c0_##name(unsigned int clear) \ 1382 { \ 1383 unsigned int res; \ 1384 \ 1385 res = read_c0_##name(); \ 1386 res &= ~clear; \ 1387 write_c0_##name(res); \ 1388 \ 1389 return res; \ 1390 } \ 1391 \ 1392 static inline unsigned int \ 1393 change_c0_##name(unsigned int change, unsigned int new) \ 1394 { \ 1395 unsigned int res; \ 1396 \ 1397 res = read_c0_##name(); \ 1398 res &= ~change; \ 1399 res |= (new & change); \ 1400 write_c0_##name(res); \ 1401 \ 1402 return res; \ 1403 } 1404 1405 #else /* SMTC versions that manage MT scheduling */ 1406 1407 #include <linux/irqflags.h> 1408 1409 /* 1410 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with 1411 * header file recursion. 1412 */ 1413 static inline unsigned int __dmt(void) 1414 { 1415 int res; 1416 1417 __asm__ __volatile__( 1418 " .set push \n" 1419 " .set mips32r2 \n" 1420 " .set noat \n" 1421 " .word 0x41610BC1 # dmt $1 \n" 1422 " ehb \n" 1423 " move %0, $1 \n" 1424 " .set pop \n" 1425 : "=r" (res)); 1426 1427 instruction_hazard(); 1428 1429 return res; 1430 } 1431 1432 #define __VPECONTROL_TE_SHIFT 15 1433 #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT) 1434 1435 #define __EMT_ENABLE __VPECONTROL_TE 1436 1437 static inline void __emt(unsigned int previous) 1438 { 1439 if ((previous & __EMT_ENABLE)) 1440 __asm__ __volatile__( 1441 " .set mips32r2 \n" 1442 " .word 0x41600be1 # emt \n" 1443 " ehb \n" 1444 " .set mips0 \n"); 1445 } 1446 1447 static inline void __ehb(void) 1448 { 1449 __asm__ __volatile__( 1450 " .set mips32r2 \n" 1451 " ehb \n" " .set mips0 \n"); 1452 } 1453 1454 /* 1455 * Note that local_irq_save/restore affect TC-specific IXMT state, 1456 * not Status.IE as in non-SMTC kernel. 1457 */ 1458 1459 #define __BUILD_SET_C0(name) \ 1460 static inline unsigned int \ 1461 set_c0_##name(unsigned int set) \ 1462 { \ 1463 unsigned int res; \ 1464 unsigned int omt; \ 1465 unsigned long flags; \ 1466 \ 1467 local_irq_save(flags); \ 1468 omt = __dmt(); \ 1469 res = read_c0_##name(); \ 1470 res |= set; \ 1471 write_c0_##name(res); \ 1472 __emt(omt); \ 1473 local_irq_restore(flags); \ 1474 \ 1475 return res; \ 1476 } \ 1477 \ 1478 static inline unsigned int \ 1479 clear_c0_##name(unsigned int clear) \ 1480 { \ 1481 unsigned int res; \ 1482 unsigned int omt; \ 1483 unsigned long flags; \ 1484 \ 1485 local_irq_save(flags); \ 1486 omt = __dmt(); \ 1487 res = read_c0_##name(); \ 1488 res &= ~clear; \ 1489 write_c0_##name(res); \ 1490 __emt(omt); \ 1491 local_irq_restore(flags); \ 1492 \ 1493 return res; \ 1494 } \ 1495 \ 1496 static inline unsigned int \ 1497 change_c0_##name(unsigned int change, unsigned int new) \ 1498 { \ 1499 unsigned int res; \ 1500 unsigned int omt; \ 1501 unsigned long flags; \ 1502 \ 1503 local_irq_save(flags); \ 1504 \ 1505 omt = __dmt(); \ 1506 res = read_c0_##name(); \ 1507 res &= ~change; \ 1508 res |= (new & change); \ 1509 write_c0_##name(res); \ 1510 __emt(omt); \ 1511 local_irq_restore(flags); \ 1512 \ 1513 return res; \ 1514 } 1515 #endif 1516 1517 __BUILD_SET_C0(status) 1518 __BUILD_SET_C0(cause) 1519 __BUILD_SET_C0(config) 1520 __BUILD_SET_C0(intcontrol) 1521 __BUILD_SET_C0(intctl) 1522 __BUILD_SET_C0(srsmap) 1523 1524 #endif /* !__ASSEMBLY__ */ 1525 1526 #endif /* _ASM_MIPSREGS_H */ 1527
