| /external/llvm/lib/Target/XCore/ |
| XCoreSubtarget.cpp | 26 XCoreSubtarget::XCoreSubtarget(const std::string &TT,
28 : XCoreGenSubtargetInfo(TT, CPU, FS)
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64Subtarget.cpp | 28 AArch64Subtarget::AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS)
29 : AArch64GenSubtargetInfo(TT, CPU, FS)
32 , TargetTriple(TT) {
|
| /external/llvm/lib/Target/CppBackend/TargetInfo/ |
| CppBackendTargetInfo.cpp | 17 static unsigned CppBackend_TripleMatchQuality(const std::string &TT) {
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCAsmInfo.h | 25 explicit HexagonMCAsmInfo(const Target &T, StringRef TT);
|
| HexagonMCTargetDesc.cpp | 43 static MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT) {
49 static MCSubtargetInfo *createHexagonMCSubtargetInfo(StringRef TT,
53 InitHexagonMCSubtargetInfo(X, TT, CPU, FS);
57 static MCAsmInfo *createHexagonMCAsmInfo(const Target &T, StringRef TT) {
58 MCAsmInfo *MAI = new HexagonMCAsmInfo(T, TT);
68 static MCCodeGenInfo *createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM,
|
| /external/llvm/lib/Target/MSP430/MCTargetDesc/ |
| MSP430MCAsmInfo.h | 26 explicit MSP430MCAsmInfo(const Target &T, StringRef TT);
|
| MSP430MCAsmInfo.cpp | 20 MSP430MCAsmInfo::MSP430MCAsmInfo(const Target &T, StringRef TT) {
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCAsmInfo.h | 26 explicit MipsMCAsmInfo(const Target &T, StringRef TT);
|
| /external/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| NVPTXMCAsmInfo.h | 26 explicit NVPTXMCAsmInfo(const Target &T, const StringRef &TT);
|
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCAsmInfo.h | 26 explicit SparcELFMCAsmInfo(const Target &T, StringRef TT);
|
| SparcMCAsmInfo.cpp | 21 SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Target &T, StringRef TT) {
23 Triple TheTriple(TT);
|
| /external/llvm/lib/Target/XCore/MCTargetDesc/ |
| XCoreMCAsmInfo.h | 26 explicit XCoreMCAsmInfo(const Target &T, StringRef TT);
|
| XCoreMCAsmInfo.cpp | 16 XCoreMCAsmInfo::XCoreMCAsmInfo(const Target &T, StringRef TT) {
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430Subtarget.cpp | 26 MSP430Subtarget::MSP430Subtarget(const std::string &TT,
29 MSP430GenSubtargetInfo(TT, CPU, FS) {
|
| /external/clang/test/SemaCXX/ |
| redeclared-alias-template.cpp | 16 template<template<typename> class> struct TT;
19 TT<A> f(); // expected-note {{previous declaration is here}}
22 TT<A> f(); // expected-error {{functions that differ only in their return type cannot be overloaded}}
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.cpp | 40 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
41 Triple triple(TT);
45 unsigned Len = TT.size();
50 if (Len >= 5 && TT.substr(0, 4) == "armv")
52 else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
54 if (Len >= 7 && TT[5] == 'v')
61 unsigned SubVer = TT[Idx];
63 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
70 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm')
[all...] |
| ARMMCTargetDesc.h | 35 std::string ParseARMTriple(StringRef TT, StringRef CPU);
40 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
49 MCAsmBackend *createARMAsmBackend(const Target &T, StringRef TT, StringRef CPU);
|
| /external/clang/test/CXX/temp/temp.decls/temp.alias/ |
| p2.cpp | 30 template<template<class> class TT>
31 void f(TT<int>); // expected-note {{candidate template ignored}}
33 template<template<class,class> class TT>
34 void g(TT<int, Alloc<int>>);
38 g(v); // OK: TT = vector
|
| /external/clang/test/CXX/temp/temp.param/ |
| p9.cpp | 21 template<template<int> class TT = X0> // expected-error{{not permitted on a friend template}}
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| AMDGPUMCAsmInfo.h | 25 explicit AMDGPUMCAsmInfo(const Target &T, StringRef &TT);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcSubtarget.cpp | 26 SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU,
28 SparcGenSubtargetInfo(TT, CPU, FS),
|
| SparcTargetMachine.cpp | 28 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS, is64bit),
79 StringRef TT, StringRef CPU,
85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
91 StringRef TT, StringRef CPU,
97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXTargetMachine.cpp | 63 StringRef TT,
71 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
72 Subtarget(TT, CPU, FS, is64bit),
82 NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, StringRef TT,
87 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
92 NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, StringRef TT,
97 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
|
| /external/clang/test/SemaTemplate/ |
| temp_class_spec_neg.cpp | 30 template<typename T, int N, template<typename X> class TT>
34 template<typename T, int N, template<typename X> class TT>
35 struct Test0<T, N, TT>; // expected-error{{does not specialize}}
40 template<typename X> class TT = ::vector> // expected-error{{default template argument}}
41 struct Test0<T*, N, TT> { };
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCTargetDesc.h | 51 std::string ParseX86Triple(StringRef TT);
65 unsigned getDwarfRegFlavour(StringRef TT, bool isEH);
72 MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
81 MCAsmBackend *createX86_32AsmBackend(const Target &T, StringRef TT, StringRef CPU);
82 MCAsmBackend *createX86_64AsmBackend(const Target &T, StringRef TT, StringRef CPU);
|
