1 //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides X86 specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef X86MCTARGETDESC_H 15 #define X86MCTARGETDESC_H 16 17 #include "llvm/Support/DataTypes.h" 18 #include <string> 19 20 namespace llvm { 21 class MCAsmBackend; 22 class MCCodeEmitter; 23 class MCContext; 24 class MCInstrInfo; 25 class MCObjectWriter; 26 class MCRegisterInfo; 27 class MCSubtargetInfo; 28 class Target; 29 class StringRef; 30 class raw_ostream; 31 32 extern Target TheX86_32Target, TheX86_64Target; 33 34 /// DWARFFlavour - Flavour of dwarf regnumbers 35 /// 36 namespace DWARFFlavour { 37 enum { 38 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 39 }; 40 } 41 42 /// N86 namespace - Native X86 register numbers 43 /// 44 namespace N86 { 45 enum { 46 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 47 }; 48 } 49 50 namespace X86_MC { 51 std::string ParseX86Triple(StringRef TT); 52 53 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in 54 /// the specified arguments. If we can't run cpuid on the host, return true. 55 bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, 56 unsigned *rEBX, unsigned *rECX, unsigned *rEDX); 57 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 58 /// the 4 values in the specified arguments. If we can't run cpuid on the 59 /// host, return true. 60 bool GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX, 61 unsigned *rEBX, unsigned *rECX, unsigned *rEDX); 62 63 void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model); 64 65 unsigned getDwarfRegFlavour(StringRef TT, bool isEH); 66 67 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI); 68 69 /// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance. 70 /// This is exposed so Asm parser, etc. do not need to go through 71 /// TargetRegistry. 72 MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, 73 StringRef FS); 74 } 75 76 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, 77 const MCRegisterInfo &MRI, 78 const MCSubtargetInfo &STI, 79 MCContext &Ctx); 80 81 MCAsmBackend *createX86_32AsmBackend(const Target &T, StringRef TT, StringRef CPU); 82 MCAsmBackend *createX86_64AsmBackend(const Target &T, StringRef TT, StringRef CPU); 83 84 /// createX86MachObjectWriter - Construct an X86 Mach-O object writer. 85 MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS, 86 bool Is64Bit, 87 uint32_t CPUType, 88 uint32_t CPUSubtype); 89 90 /// createX86ELFObjectWriter - Construct an X86 ELF object writer. 91 MCObjectWriter *createX86ELFObjectWriter(raw_ostream &OS, 92 bool IsELF64, 93 uint8_t OSABI, 94 uint16_t EMachine); 95 /// createX86WinCOFFObjectWriter - Construct an X86 Win COFF object writer. 96 MCObjectWriter *createX86WinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit); 97 } // End llvm namespace 98 99 100 // Defines symbolic names for X86 registers. This defines a mapping from 101 // register name to register number. 102 // 103 #define GET_REGINFO_ENUM 104 #include "X86GenRegisterInfo.inc" 105 106 // Defines symbolic names for the X86 instructions. 107 // 108 #define GET_INSTRINFO_ENUM 109 #include "X86GenInstrInfo.inc" 110 111 #define GET_SUBTARGETINFO_ENUM 112 #include "X86GenSubtargetInfo.inc" 113 114 #endif 115
