| /external/srec/srec/Semproc/src/ |
| ExpressionEvaluator.c | 39 ESR_ReturnCode EE_concat(LCHAR* name, LCHAR** operands, size_t opCount, void* data, LCHAR* resultBuf, size_t* resultLen)
44 if (operands == NULL || resultBuf == NULL || resultLen == NULL)
52 opLen = LSTRLEN(operands[i]);
54 LSTRCAT(resultBuf, operands[i]);
62 ESR_ReturnCode EE_conditional(LCHAR* name, LCHAR** operands, size_t opCount, void* data, LCHAR* resultBuf, size_t* resultLen)
64 if (operands == NULL || resultBuf == NULL || resultLen == NULL)
70 if (!LSTRCMP(operands[0], UNDEFINED_SYMBOL) || !operands[0] ||
71 !LSTRCMP(operands[0], FALSE_SYMBOL))
73 if (strlen(operands[2]) >= *resultLen
[all...] |
| /external/llvm/utils/TableGen/ |
| X86DisassemblerShared.h | 17 struct OperandSpecifier operands[X86_MAX_OPERANDS]; \
28 memset(operands, 0, sizeof(operands)); \
|
| /dalvik/vm/compiler/codegen/mips/ |
| GlobalOptimizations.cpp | 163 savedLIR[i]->useMask &= ~(1 << thisLIR->operands[0]);
164 savedLIR[i]->useMask |= 1 << thisLIR->operands[1];
166 savedLIR[i]->operands[0] == thisLIR->operands[0])
167 savedLIR[i]->operands[0] = thisLIR->operands[1];
169 savedLIR[i]->operands[1] == thisLIR->operands[0])
170 savedLIR[i]->operands[1] = thisLIR->operands[1]
[all...] |
| CodegenCommon.cpp | 87 if (DOUBLEREG(lir->operands[0])) {
172 setupRegMask(&lir->defMask, lir->operands[0]);
176 setupRegMask(&lir->defMask, lir->operands[1]);
188 lir->defMask |= ENCODE_REG_LIST(lir->operands[0]);
192 lir->defMask |= ENCODE_REG_LIST(lir->operands[1]);
209 setupRegMask(&lir->useMask, lir->operands[i]);
223 lir->useMask |= ENCODE_REG_LIST(lir->operands[0]);
227 lir->useMask |= ENCODE_REG_LIST(lir->operands[1]);
258 setupRegMask(&lir->useMask, lir->operands[i]);
270 * operands
[all...] |
| ArchUtility.cpp | 53 operand = lir->operands[nc-'0'];
127 int offset_1 = lir->operands[0];
128 int offset_2 = NEXT_LIR(lir)->operands[0];
224 int dest = lir->operands[0];
270 (char *) lir->operands[1]);
281 lir->operands[1]);
334 ((CallsiteInfo *) mipsLIR->operands[0])->classDescriptor);
341 mipsLIR->operands[0]);
|
| LocalOptimizations.cpp | 24 /* Check RAW, WAR, and WAR dependency on the register operands */
108 int nativeRegId = thisLIR->operands[0];
160 REGTYPE(checkLIR->operands[0]) == REGTYPE(nativeRegId)){
165 if (checkLIR->operands[0] != nativeRegId) {
167 checkLIR->operands[0],
177 REGTYPE(checkLIR->operands[0]) ==
187 if (checkLIR->operands[0] !=
191 checkLIR->operands[0],
234 * their register operands have any RAW, WAR, and WAW
|
| /external/srec/srec/Semproc/include/ |
| SR_ExpressionEvaluator.h | 60 * @param operands array of strings holding operands to concatenate
61 * @param opCount number of operands
66 SREC_SEMPROC_API ESR_ReturnCode EE_concat(LCHAR* name, LCHAR** operands, size_t opCount, void* data, LCHAR* resultBuf, size_t* resultLen);
69 * Built-in function to support conditional expressions (with 3 operands only!!!)
71 * @param operands first op is the condition, second is the true val, third is the false val
72 * @param opCount number of operands
76 SREC_SEMPROC_API ESR_ReturnCode EE_conditional(LCHAR* name, LCHAR** operands, size_t opCount, void* data, LCHAR* resultBuf, size_t* resultLen);
81 * @param operands strings to interpret as integers and then add together
82 * @param opCount number of operands
[all...] |
| /dalvik/dx/src/com/android/dx/ssa/ |
| PhiInsn.java | 41 * {@code non-null;} operands of the instruction; built up by
44 private final ArrayList<Operand> operands = new ArrayList<Operand>(); field in class:PhiInsn
50 * Constructs a new phi insn with no operands.
82 * Updates the TypeBearers of all the sources (phi operands) to be
86 * Note that local association of operands are preserved in this step.
91 for (Operand o : operands) {
130 operands.add(new Operand(registerSpec, predBlock.getIndex(),
144 for (Operand o : operands) {
150 operands.removeAll(operandsToRemove);
164 return operands.get(sourcesIndex).blockIndex
[all...] |
| /dalvik/vm/compiler/template/armv5te/ |
| TEMPLATE_CMPL_DOUBLE.S | 10 * on what value we'd like to return when one of the operands is NaN.
17 push {r0-r3} @ save operands
24 add sp, #16 @ drop unused operands
31 pop {r2-r3} @ restore operands in reverse order
32 pop {r0-r1} @ restore operands in reverse order
|
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| PhiInsn.java | 41 * {@code non-null;} operands of the instruction; built up by
44 private final ArrayList<Operand> operands = new ArrayList<Operand>(); field in class:PhiInsn
50 * Constructs a new phi insn with no operands.
82 * Updates the TypeBearers of all the sources (phi operands) to be
86 * Note that local association of operands are preserved in this step.
91 for (Operand o : operands) {
130 operands.add(new Operand(registerSpec, predBlock.getIndex(),
144 for (Operand o : operands) {
150 operands.removeAll(operandsToRemove);
164 return operands.get(sourcesIndex).blockIndex
[all...] |
| /external/llvm/include/llvm/IR/ |
| OperandTraits.h | 12 // the operands in the most efficient manner.
38 static unsigned operands(const User*) { function in struct:llvm::FixedNumOperandTraits
47 /// OptionalOperandTraits - when the number of operands may change at runtime.
52 static unsigned operands(const User *U) { function in struct:llvm::OptionalOperandTraits
73 static unsigned operands(const User *U) { function in struct:llvm::VariadicOperandTraits
100 static unsigned operands(const User *U) { function in struct:llvm::HungoffOperandTraits
137 assert(i_nocapture < OperandTraits<CLASS>::operands(this) \
143 assert(i_nocapture < OperandTraits<CLASS>::operands(this) \
148 return OperandTraits<CLASS>::operands(this); \
|
| /dalvik/vm/compiler/codegen/arm/ |
| CodegenCommon.cpp | 84 if (DOUBLEREG(lir->operands[0])) {
154 setupRegMask(&lir->defMask, lir->operands[0]);
158 setupRegMask(&lir->defMask, lir->operands[1]);
170 lir->defMask |= ENCODE_REG_LIST(lir->operands[0]);
174 lir->defMask |= ENCODE_REG_LIST(lir->operands[1]);
191 setupRegMask(&lir->useMask, lir->operands[i]);
205 lir->useMask |= ENCODE_REG_LIST(lir->operands[0]);
209 lir->useMask |= ENCODE_REG_LIST(lir->operands[1]);
250 setupRegMask(&lir->useMask, lir->operands[i]);
262 * operands
[all...] |
| LocalOptimizations.cpp | 24 /* Check RAW, WAR, and WAR dependency on the register operands */
108 int nativeRegId = thisLIR->operands[0];
160 REGTYPE(checkLIR->operands[0]) == REGTYPE(nativeRegId)){
165 if (checkLIR->operands[0] != nativeRegId) {
167 checkLIR->operands[0],
177 REGTYPE(checkLIR->operands[0]) ==
187 if (checkLIR->operands[0] !=
191 checkLIR->operands[0],
234 * their register operands have any RAW, WAR, and WAW
|
| ArchUtility.cpp | 96 operand = lir->operands[nc-'0'];
204 int offset_1 = lir->operands[0];
205 int offset_2 = NEXT_LIR(lir)->operands[0];
301 int dest = lir->operands[0];
348 (char *) lir->operands[1]);
359 lir->operands[1]);
412 ((CallsiteInfo *) armLIR->operands[0])->classDescriptor);
419 armLIR->operands[0]);
|
| /external/antlr/antlr-3.4/tool/src/main/java/org/antlr/analysis/ |
| SemanticContext.java | 55 * July 7, 2006: TJP altered OR to be set of operands. the Binary tree
304 protected final Set<SemanticContext> operands = new HashSet<SemanticContext>(); field in class:SemanticContext.CommutativePredicate
310 operands.addAll(predicate.operands);
312 operands.add(a);
317 operands.addAll(predicate.operands);
319 operands.add(b);
329 operands.addAll(predicate.operands);
789 Collection<SemanticContext> operands = getOrOperands(((NOT)context).ctx); local
808 Collection<SemanticContext> operands = getAndOperands(((NOT)context).ctx); local
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.h | 40 // meanings of its operands.
49 // register, for instance). Given this information, the operands can be
53 // and operands into a format understandable by the client - in this case, an
78 uint16_t operands;
|
| /external/llvm/lib/IR/ |
| ConstantsContext.h | 55 // allocate space for exactly two operands
76 // allocate space for exactly three operands
97 // allocate space for exactly two operands
118 // allocate space for exactly three operands
140 // allocate space for exactly three operands
239 // allocate space for exactly two operands
323 operands(ops.begin(), ops.end()), indices(inds.begin(), inds.end()) {}
327 std::vector<Constant*> operands; member in struct:llvm::ExprMapKeyType
333 this->operands == that.operands &
[all...] |
| /external/clang/test/SemaCXX/ |
| null_in_arithmetic_ops.cpp | 31 expected-error {{invalid operands to binary expression ('long' and 'void (^)()')}} \
32 expected-error {{invalid operands to binary expression ('void (^)()' and 'long')}}
34 expected-error {{invalid operands to binary expression ('long' and 'void (X::*)()')}} \
35 expected-error {{invalid operands to binary expression ('void (X::*)()' and 'long')}}
|
| /external/elfutils/libcpu/ |
| i386_parse.y | 116 /* Operands. */
124 } operands[3];
787 if (instr->operands[n].str != NULL)
792 instr->operands[n].str = runp->str;
835 if (instr->operands[n].off1 == 0)
836 instr->operands[n].off1 = bitoff;
837 else if (instr->operands[n].off2 == 0)
838 instr->operands[n].off2 = bitoff;
839 else if (instr->operands[n].off3 == 0)
840 instr->operands[n].off3 = bitoff
[all...] |
| /dalvik/vm/compiler/codegen/x86/libenc/ |
| dec_base.h | 103 EncoderBase::Operand operands[3]; member in struct:Inst
|
| /external/llvm/test/MC/ARM/ |
| arm-memory-instructions.s | 29 @ label operands currently assert the show-encoding asm comment helper due
|
| diagnostics.s | 271 @ Out of order Rt/Rt2 operands for ldrexd/strexd
275 @ CHECK-ERRORS: error: destination operands must be sequential
278 @ CHECK-ERRORS: error: source operands must be sequential
327 @ Out of order Rt/Rt2 operands for ldrd
331 @ CHECK-ERRORS: error: destination operands must be sequential
334 @ CHECK-ERRORS: error: destination operands must be sequential
337 @ CHECK-ERRORS: error: destination operands must be sequential
365 @ Bad operands for msr
|
| /dalvik/vm/compiler/codegen/arm/Thumb2/ |
| Factory.cpp | 73 loadPcRel->operands[0] = rDest;
74 loadPcRel->operands[1] = r15pc;
77 loadPcRel->aliasInfo = dataTarget->operands[0];
181 loadPcRel->operands[0] = rDest;
184 loadPcRel->aliasInfo = dataTarget->operands[0];
192 if (dataTarget->operands[0] != value) {
193 opRegImm(cUnit, kOpAdd, rDest, value - dataTarget->operands[0]);
232 loadPcRel->operands[0] = rDest;
235 loadPcRel->aliasInfo = dataTarget->operands[0];
726 loadPcRel->operands[0] = targetReg
[all...] |
| /dalvik/vm/compiler/codegen/arm/Thumb/ |
| Factory.cpp | 79 loadPcRel->operands[0] = tDest;
82 loadPcRel->aliasInfo = dataTarget->operands[0];
90 if (dataTarget->operands[0] != value) {
91 newLIR2(cUnit, kThumbAddRI8, tDest, value - dataTarget->operands[0]);
134 loadPcRel->operands[0] = rDest;
137 loadPcRel->aliasInfo = dataTarget->operands[0];
853 res->operands[0] = rDest;
854 res->operands[1] = rSrc;
908 pushFP->operands[0] = 1 << r5FP;
915 pushLR->operands[0] = 1 << 8
[all...] |
| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| Factory.cpp | 49 res->operands[0] = rDest;
50 res->operands[1] = rSrc;
63 /* note the operands are swapped for the mtc1 instr */
65 res->operands[0] = rSrc;
66 res->operands[1] = rDest;
846 res->operands[0] = rDest;
847 res->operands[1] = rSrc;
875 /* note the operands are swapped for the mtc1 instr */
975 pushFP->operands[0] = 1 << r5FP;
982 pushLR->operands[0] = 1 << 8
[all...] |
