1 %default { "naninst":"mvn r0, #0" } 2 /* 3 * For the JIT: incoming arguments in r0-r1, r2-r3 4 * result in r0 5 * 6 * Compare two floating-point values. Puts 0, 1, or -1 into the 7 * destination register based on the results of the comparison. 8 * 9 * Provide a "naninst" instruction that puts 1 or -1 into r1 depending 10 * on what value we'd like to return when one of the operands is NaN. 11 * 12 * See OP_CMPL_FLOAT for an explanation. 13 * 14 * For: cmpl-double, cmpg-double 15 */ 16 /* op vAA, vBB, vCC */ 17 push {r0-r3} @ save operands 18 mov r11, lr @ save return address 19 ldr ip, .L__aeabi_cdcmple @ PIC way of "bl __aeabi_cdcmple" 20 blx ip 21 bhi .L${opcode}_gt_or_nan @ C set and Z clear, disambiguate 22 mvncc r0, #0 @ (less than) r1<- -1 23 moveq r0, #0 @ (equal) r1<- 0, trumps less than 24 add sp, #16 @ drop unused operands 25 bx r11 26 27 @ Test for NaN with a second comparison. EABI forbids testing bit 28 @ patterns, and we can't represent 0x7fc00000 in immediate form, so 29 @ make the library call. 30 .L${opcode}_gt_or_nan: 31 pop {r2-r3} @ restore operands in reverse order 32 pop {r0-r1} @ restore operands in reverse order 33 ldr ip, .L__aeabi_cdcmple @ r0<- Z set if eq, C clear if < 34 blx ip 35 movcc r0, #1 @ (greater than) r1<- 1 36 bxcc r11 37 $naninst @ r1<- 1 or -1 for NaN 38 bx r11 39
