| /external/llvm/lib/Target/R600/ |
| SIISelLowering.h | 50 virtual EVT getSetCCResultType(EVT VT) const;
51 virtual MVT getScalarShiftAmountTy(EVT VT) const;
|
| R600ISelLowering.cpp | 358 EVT VT = Op.getValueType();
365 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
399 return LowerImplicitParameter(DAG, VT, DL, 0);
401 return LowerImplicitParameter(DAG, VT, DL, 1);
403 return LowerImplicitParameter(DAG, VT, DL, 2);
405 return LowerImplicitParameter(DAG, VT, DL, 3);
407 return LowerImplicitParameter(DAG, VT, DL, 4);
409 return LowerImplicitParameter(DAG, VT, DL, 5);
411 return LowerImplicitParameter(DAG, VT, DL, 6);
413 return LowerImplicitParameter(DAG, VT, DL, 7)
[all...] |
| R600ISelLowering.h | 41 virtual EVT getSetCCResultType(EVT VT) const;
49 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
|
| SIISelLowering.cpp | 118 if (Arg.VT.isVector()) {
121 NewArg.VT = Arg.VT.getVectorElementType();
131 NewArg.PartOffset += NewArg.VT.getStoreSize();
163 MVT VT = VA.getLocVT();
165 if (VT == MVT::i64) {
170 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
174 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
177 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
180 if (Arg.VT.isVector())
[all...] |
| AMDGPUISelLowering.h | 37 unsigned Reg, EVT VT) const;
85 bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
88 bool ShouldShrinkFPConstant(EVT VT) const;
|
| R600RegisterInfo.cpp | 83 MVT VT) const {
84 switch(VT.SimpleTy) {
|
| /libcore/luni/src/main/java/java/util/ |
| MapEntry.java | 28 interface Type<RT, KT, VT> {
29 RT get(MapEntry<KT, VT> entry);
|
| IdentityHashMap.java | 129 static class IdentityHashMapIterator<E, KT, VT> implements Iterator<E> {
135 final IdentityHashMap<KT, VT> associatedMap;
139 final MapEntry.Type<E, KT, VT> type;
143 IdentityHashMapIterator(MapEntry.Type<E, KT, VT> value,
144 IdentityHashMap<KT, VT> hm) {
174 IdentityHashMapEntry<KT, VT> result = associatedMap
196 static class IdentityHashMapEntrySet<KT, VT> extends
197 AbstractSet<Map.Entry<KT, VT>> {
198 private final IdentityHashMap<KT, VT> associatedMap;
200 public IdentityHashMapEntrySet(IdentityHashMap<KT, VT> hm)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 93 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
95 if (VT != PromotedLdStVT) {
96 setOperationAction(ISD::LOAD, VT, Promote);
97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
99 setOperationAction(ISD::STORE, VT, Promote);
100 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
103 MVT ElemTy = VT.getVectorElementType();
105 setOperationAction(ISD::SETCC, VT, Custom);
106 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
107 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom)
[all...] |
| ARMFastISel.cpp | 178 bool isTypeLegal(Type *Ty, MVT &VT);
179 bool isLoadTypeLegal(Type *Ty, MVT &VT);
182 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
185 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
188 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
193 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
194 unsigned ARMMaterializeInt(const Constant *C, MVT VT);
195 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
196 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
197 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg)
[all...] |
| ARMSelectionDAGInfo.cpp | 52 EVT VT = MVT::i32;
66 Loads[i] = DAG.getLoad(VT, dl, Chain,
98 VT = MVT::i16;
101 VT = MVT::i8;
105 Loads[i] = DAG.getLoad(VT, dl, Chain,
121 VT = MVT::i16;
124 VT = MVT::i8;
|
| ARMISelLowering.h | 273 virtual EVT getSetCCResultType(EVT VT) const;
285 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
290 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
304 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
352 EVT VT) const;
369 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const;
382 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
388 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
395 findRepresentativeClass(MVT VT) const;
410 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 97 MVT VT = ScegN->getSimpleValueType(i);
98 if (TLI->isTypeLegal(VT)
99 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
135 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
136 if (TLI->isTypeLegal(VT)
137 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
335 MVT VT = SU->getNode()->getSimpleValueType(i);
336 if (TLI->isTypeLegal(VT)
337 && TLI->getRegClassFor(VT)
338 && TLI->getRegClassFor(VT)->getID() == RCId
[all...] |
| LegalizeIntegerTypes.cpp | 284 EVT VT = N->getValueType(0);
289 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
291 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
607 // Truncate to NVT instead of VT
705 EVT VT = N->getValueType(0);
708 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
709 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 517 virtual bool isSafeMemOpType(MVT VT) const;
522 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
541 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
559 virtual EVT getSetCCResultType(EVT VT) const;
606 EVT VT) const;
656 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
663 EVT VT) const;
670 EVT VT) const;
675 virtual bool ShouldShrinkFPConstant(EVT VT) const {
679 return !X86ScalarSSEf64 || VT == MVT::f80
[all...] |
| X86FastISel.cpp | 83 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT);
85 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
87 bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM);
88 bool X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM);
137 bool isScalarFPTypeInSSEReg(EVT VT) const {
138 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
139 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
142 bool isTypeLegal(Type *Ty, MVT &VT, bool AllowI1 = false);
152 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) {
158 VT = evt.getSimpleVT()
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 468 MVT::SimpleValueType VT;
473 VT = OverloadedVTs[MatchTy];
479 VT == MVT::iAny || VT == MVT::vAny) &&
482 VT = getValueType(TyEl->getValueAsDef("VT"));
484 if (EVT(VT).isOverloaded()) {
485 OverloadedVTs.push_back(VT);
490 if (VT == MVT::isVoid)
493 IS.RetVTs.push_back(VT);
[all...] |
| DAGISelMatcher.h | 770 MVT::SimpleValueType VT;
772 EmitIntegerMatcher(int64_t val, MVT::SimpleValueType vt)
773 : Matcher(EmitInteger), Val(val), VT(vt) {}
776 MVT::SimpleValueType getVT() const { return VT; }
786 cast<EmitIntegerMatcher>(M)->VT == VT;
788 virtual unsigned getHashImpl() const { return (Val << 4) | VT; }
795 MVT::SimpleValueType VT;
797 EmitStringIntegerMatcher(const std::string &val, MVT::SimpleValueType vt)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.h | 105 EVT getSetCCResultType(EVT VT) const;
168 EVT VT) const;
175 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 255 EVT VT = N.getValueType();
258 AM.Base.Reg = CurDAG->getRegister(0, VT);
307 EVT VT = LD->getMemoryVT();
309 switch (VT.getSimpleVT().SimpleTy) {
334 MVT VT = LD->getMemoryVT().getSimpleVT();
337 switch (VT.SimpleTy) {
349 VT, MVT::i16, MVT::Other,
363 MVT VT = LD->getMemoryVT().getSimpleVT();
364 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
370 VT, MVT::i16, MVT::Other
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 631 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
635 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
636 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
640 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
641 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
759 /// VT must be a legal type.
760 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
761 assert(isTypeLegal(VT));
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | 354 static const EVT *getValueTypeList(EVT VT);
685 static SDVTList getSDVTList(EVT VT) {
686 SDVTList Ret = { getValueTypeList(VT), 1 };
902 // MemoryVT - VT of in-memory value.
[all...] |
| /external/clang/include/clang/AST/ |
| DeclContextInternals.h | 171 DeclsTy *VT = new DeclsTy();
172 VT->push_back(OldD);
173 Data = VT;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 141 virtual EVT getSetCCResultType(EVT VT) const {
152 EVT VT) const;
163 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 270 EVT AArch64TargetLowering::getSetCCResultType(EVT VT) const {
274 if (!VT.isVector()) return MVT::i32;
275 return VT.changeVectorElementTypeToInteger();
[all...] |
