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      1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 /// \file
     11 /// \brief Interface definition of the TargetLowering class that is common
     12 /// to all AMD GPUs.
     13 //
     14 //===----------------------------------------------------------------------===//
     15 
     16 #ifndef AMDGPUISELLOWERING_H
     17 #define AMDGPUISELLOWERING_H
     18 
     19 #include "llvm/Target/TargetLowering.h"
     20 
     21 namespace llvm {
     22 
     23 class MachineRegisterInfo;
     24 
     25 class AMDGPUTargetLowering : public TargetLowering {
     26 private:
     27   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
     28   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
     29 
     30 protected:
     31 
     32   /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
     33   /// MachineFunction.
     34   ///
     35   /// \returns a RegisterSDNode representing Reg.
     36   SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
     37                                                   unsigned Reg, EVT VT) const;
     38 
     39   bool isHWTrueValue(SDValue Op) const;
     40   bool isHWFalseValue(SDValue Op) const;
     41 
     42   void AnalyzeFormalArguments(CCState &State,
     43                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
     44 
     45 public:
     46   AMDGPUTargetLowering(TargetMachine &TM);
     47 
     48   virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
     49                               bool isVarArg,
     50                               const SmallVectorImpl<ISD::OutputArg> &Outs,
     51                               const SmallVectorImpl<SDValue> &OutVals,
     52                               DebugLoc DL, SelectionDAG &DAG) const;
     53   virtual SDValue LowerCall(CallLoweringInfo &CLI,
     54                             SmallVectorImpl<SDValue> &InVals) const {
     55     CLI.Callee.dump();
     56     llvm_unreachable("Undefined function");
     57   }
     58 
     59   virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
     60   SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
     61   SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
     62   SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
     63   virtual const char* getTargetNodeName(unsigned Opcode) const;
     64 
     65   virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const {
     66     return N;
     67   }
     68 
     69 // Functions defined in AMDILISelLowering.cpp
     70 public:
     71 
     72   /// \brief Determine which of the bits specified in \p Mask are known to be
     73   /// either zero or one and return them in the \p KnownZero and \p KnownOne
     74   /// bitsets.
     75   virtual void computeMaskedBitsForTargetNode(const SDValue Op,
     76                                               APInt &KnownZero,
     77                                               APInt &KnownOne,
     78                                               const SelectionDAG &DAG,
     79                                               unsigned Depth = 0) const;
     80 
     81   virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
     82                                   const CallInst &I, unsigned Intrinsic) const;
     83 
     84   /// We want to mark f32/f64 floating point values as legal.
     85   bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
     86 
     87   /// We don't want to shrink f64/f32 constants.
     88   bool ShouldShrinkFPConstant(EVT VT) const;
     89 
     90 private:
     91   void InitAMDILLowering();
     92   SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
     93   SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
     94   SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
     95   SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
     96   SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
     97   SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
     98   SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
     99   SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
    100   SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
    101   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
    102   EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
    103   SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
    104   SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
    105 };
    106 
    107 namespace AMDGPUISD {
    108 
    109 enum {
    110   // AMDIL ISD Opcodes
    111   FIRST_NUMBER = ISD::BUILTIN_OP_END,
    112   CALL,        // Function call based on a single integer
    113   UMUL,        // 32bit unsigned multiplication
    114   DIV_INF,      // Divide with infinity returned on zero divisor
    115   RET_FLAG,
    116   BRANCH_COND,
    117   // End AMDIL ISD Opcodes
    118   BITALIGN,
    119   DWORDADDR,
    120   FRACT,
    121   FMAX,
    122   SMAX,
    123   UMAX,
    124   FMIN,
    125   SMIN,
    126   UMIN,
    127   URECIP,
    128   EXPORT,
    129   CONST_ADDRESS,
    130   REGISTER_LOAD,
    131   REGISTER_STORE,
    132   LAST_AMDGPU_ISD_NUMBER
    133 };
    134 
    135 
    136 } // End namespace AMDGPUISD
    137 
    138 } // End namespace llvm
    139 
    140 #endif // AMDGPUISELLOWERING_H
    141