| /external/llvm/lib/CodeGen/ |
| AllocationOrder.h | 52 unsigned Reg = Order[Pos++];
53 if (!isHint(Reg))
54 return Reg;
|
| RegAllocBase.cpp | 71 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
72 if (MRI->reg_nodbg_empty(Reg))
74 enqueue(&LIS->getInterval(Reg));
85 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
88 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
90 LIS->removeInterval(VirtReg->reg);
101 << MRI->getRegClass(VirtReg->reg)->getName()
102 << ':' << PrintReg(VirtReg->reg) << ' ' << *VirtReg << '\n');
112 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg);
121 VRM->assignVirt2Phys(VirtReg->reg,
[all...] |
| DeadMachineInstructionElim.cpp | 69 unsigned Reg = MO.getReg();
70 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
72 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
75 if (!MRI->use_nodbg_empty(Reg))
127 unsigned Reg = MO.getReg();
128 if (!TargetRegisterInfo::isVirtualRegister(Reg))
131 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
155 unsigned Reg = MO.getReg();
156 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
[all...] |
| ProcessImplicitDefs.cpp | 78 unsigned Reg = MI->getOperand(0).getReg();
80 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
84 MRI->use_nodbg_begin(Reg),
110 !TRI->regsOverlap(Reg, UserReg))
112 // UserMI uses or redefines Reg. Set <undef> flags on all uses.
|
| AggressiveAntiDepBreaker.cpp | 60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
61 unsigned Node = GroupNodeIndices[Reg];
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
75 Regs.push_back(Reg);
82 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
[all...] |
| CalcSpillWeights.cpp | 50 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
51 if (MRI.reg_nodbg_empty(Reg))
53 VRAI.CalculateWeightAndHint(LIS.getInterval(Reg));
58 // Return the preferred allocation register for reg, given a COPY instruction.
59 static unsigned copyHint(const MachineInstr *mi, unsigned reg,
63 if (mi->getOperand(0).getReg() == reg) {
79 const TargetRegisterClass *rc = mri.getRegClass(reg);
85 // reg:sub should match the physreg hreg.
125 bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
130 for (MachineRegisterInfo::reg_iterator I = mri.reg_begin(li.reg);
[all...] |
| LiveRangeEdit.cpp | 155 void LiveRangeEdit::eraseVirtReg(unsigned Reg) {
156 if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
157 LIS.removeInterval(Reg);
165 for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(LI->reg),
204 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
213 DefMI->addRegisterDead(LI->reg, 0);
256 unsigned Reg = MOI->getReg();
257 if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
259 if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
[all...] |
| MachineCopyPropagation.cpp | 51 void SourceNoLongerAvailable(unsigned Reg,
65 MachineCopyPropagation::SourceNoLongerAvailable(unsigned Reg,
68 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
242 unsigned Reg = MO.getReg();
243 if (!Reg)
246 if (TargetRegisterInfo::isVirtualRegister(Reg))
251 Defs.push_back(Reg);
255 // If 'Reg' is defined by a copy, the copy is no longer a candidate
257 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
274 unsigned Reg = (*DI)->getOperand(0).getReg()
[all...] |
| MachineRegisterInfo.cpp | 39 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
41 VRegInfo[Reg].first = RC;
45 MachineRegisterInfo::constrainRegClass(unsigned Reg,
48 const TargetRegisterClass *OldRC = getRegClass(Reg);
56 setRegClass(Reg, NewRC);
61 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
63 const TargetRegisterClass *OldRC = getRegClass(Reg);
71 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
85 setRegClass(Reg, NewRC);
99 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs())
[all...] |
| RegisterScavenging.cpp | 17 #define DEBUG_TYPE "reg-scavenging"
33 void RegScavenger::setUsed(unsigned Reg) {
34 RegsAvailable.reset(Reg);
36 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
40 bool RegScavenger::isAliasUsed(unsigned Reg) const {
41 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
42 if (isUsed(*AI, *AI == Reg))
105 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
106 BV.set(Reg);
107 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs
[all...] |
| TargetRegisterInfo.cpp | 35 if (!Reg)
37 else if (TargetRegisterInfo::isStackSlot(Reg))
38 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
39 else if (TargetRegisterInfo::isVirtualRegister(Reg))
40 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
41 else if (TRI && Reg < TRI->getNumRegs())
42 OS << '%' << TRI->getName(Reg);
44 OS << "%physreg" << Reg;
101 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
102 assert(isPhysicalRegister(reg) && "reg must be a physical register")
[all...] |
| TargetSchedule.cpp | 290 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
293 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
|
| VirtRegMap.cpp | 119 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
120 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
121 OS << '[' << PrintReg(Reg, TRI) << " -> "
122 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
123 << MRI->getRegClass(Reg)->getName() << "\n";
128 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
129 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
130 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
131 << "] " << MRI->getRegClass(Reg)->getName() << "\n"
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 34 if (unsigned Reg = State.AllocateReg(RegList, 4))
35 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
49 if (unsigned Reg = State.AllocateReg(RegList, 4))
50 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
78 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
79 if (Reg == 0) {
93 if (HiRegList[i] == Reg)
100 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
123 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
124 if (Reg == 0
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 58 void Hexagon_CCState::MarkAllocated(unsigned Reg) {
59 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
101 unsigned Reg = Hexagon::R0;
102 addLoc(CCValAssign::getReg(0, MVT::i32, Reg, MVT::i32,
107 unsigned Reg = Hexagon::D0;
108 addLoc(CCValAssign::getReg(0, MVT::i64, Reg, MVT::i64,
|
| HexagonCallingConvLower.h | 74 bool isAllocated(unsigned Reg) const {
75 return UsedRegs[Reg/32] & (1 << (Reg&31));
121 unsigned AllocateReg(unsigned Reg) {
122 if (isAllocated(Reg)) return 0;
123 MarkAllocated(Reg);
124 return Reg;
128 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
129 if (isAllocated(Reg)) return 0;
130 MarkAllocated(Reg);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSERegisterInfo.cpp | 114 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm);
115 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
116 .addReg(Reg, RegState::Kill);
118 FrameReg = Reg;
|
| Mips16FrameLowering.cpp | 118 unsigned Reg = CSI[i].getReg();
119 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
122 EntryBlock->addLiveIn(Reg);
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 125 unsigned Reg = MO.getReg();
126 if (!Reg)
128 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
167 unsigned Reg = isSub
170 if (Reg) {
175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
295 unsigned Reg = II->first;
297 if (Reg == X86::EAX || Reg == X86::AX ||
298 Reg == X86::AH || Reg == X86::AL
[all...] |
| X86FloatingPoint.cpp | 1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
118 unsigned Reg = *I - X86::FP0;
119 if (Reg < 8)
120 Mask |= 1 << Reg;
227 void pushReg(unsigned Reg) {
228 assert(Reg < NumFPRegs && "Register number out of range!");
231 Stack[StackTop] = Reg;
232 RegMap[Reg] = StackTop++;
288 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
298 /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] i
[all...] |
| X86InstrBuilder.h | 44 unsigned Reg;
56 Base.Reg = 0;
64 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false,
90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
92 // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
103 /// [Reg + Offset], i.e., one with no scale or index, but with a
108 unsigned Reg, bool isKill, int Offset) {
109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
113 /// [Reg + Reg]
[all...] |
| /external/qemu/target-i386/ |
| ops_sse_header.h | 21 #define Reg MMXReg
24 #define Reg XMMReg
31 #define dh_ctype_Reg Reg *
38 DEF_HELPER_2(glue(psrlw, SUFFIX), void, Reg, Reg)
39 DEF_HELPER_2(glue(psraw, SUFFIX), void, Reg, Reg)
40 DEF_HELPER_2(glue(psllw, SUFFIX), void, Reg, Reg)
41 DEF_HELPER_2(glue(psrld, SUFFIX), void, Reg, Reg
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| FunctionLoweringInfo.h | 148 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
149 if (!LiveOutRegInfo.inBounds(Reg))
152 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
164 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
167 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
173 LiveOutRegInfo.grow(Reg);
174 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
192 unsigned Reg = It->second;
193 LiveOutRegInfo.grow(Reg);
194 LiveOutRegInfo[Reg].IsValid = false
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 42 unsigned Reg;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 98 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
174 // Create the reg, emit the copy.
199 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
200 if (TargetRegisterInfo::isVirtualRegister(Reg))
201 return Reg;
215 // If the specific node value is only used by a CopyToReg and the dest reg
236 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
237 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
238 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
240 VRBase = Reg;
[all...] |
