1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86FrameLowering.h" 15 #include "X86InstrBuilder.h" 16 #include "X86InstrInfo.h" 17 #include "X86MachineFunctionInfo.h" 18 #include "X86Subtarget.h" 19 #include "X86TargetMachine.h" 20 #include "llvm/ADT/SmallSet.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 24 #include "llvm/CodeGen/MachineModuleInfo.h" 25 #include "llvm/CodeGen/MachineRegisterInfo.h" 26 #include "llvm/IR/DataLayout.h" 27 #include "llvm/IR/Function.h" 28 #include "llvm/MC/MCAsmInfo.h" 29 #include "llvm/MC/MCSymbol.h" 30 #include "llvm/Support/CommandLine.h" 31 #include "llvm/Target/TargetOptions.h" 32 33 using namespace llvm; 34 35 // FIXME: completely move here. 36 extern cl::opt<bool> ForceStackAlign; 37 38 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { 39 return !MF.getFrameInfo()->hasVarSizedObjects(); 40 } 41 42 /// hasFP - Return true if the specified function should have a dedicated frame 43 /// pointer register. This is true if the function has variable sized allocas 44 /// or if frame pointer elimination is disabled. 45 bool X86FrameLowering::hasFP(const MachineFunction &MF) const { 46 const MachineFrameInfo *MFI = MF.getFrameInfo(); 47 const MachineModuleInfo &MMI = MF.getMMI(); 48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo(); 49 50 return (MF.getTarget().Options.DisableFramePointerElim(MF) || 51 RegInfo->needsStackRealignment(MF) || 52 MFI->hasVarSizedObjects() || 53 MFI->isFrameAddressTaken() || MF.hasMSInlineAsm() || 54 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() || 55 MMI.callsUnwindInit() || MMI.callsEHReturn()); 56 } 57 58 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) { 59 if (IsLP64) { 60 if (isInt<8>(Imm)) 61 return X86::SUB64ri8; 62 return X86::SUB64ri32; 63 } else { 64 if (isInt<8>(Imm)) 65 return X86::SUB32ri8; 66 return X86::SUB32ri; 67 } 68 } 69 70 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) { 71 if (IsLP64) { 72 if (isInt<8>(Imm)) 73 return X86::ADD64ri8; 74 return X86::ADD64ri32; 75 } else { 76 if (isInt<8>(Imm)) 77 return X86::ADD32ri8; 78 return X86::ADD32ri; 79 } 80 } 81 82 static unsigned getLEArOpcode(unsigned IsLP64) { 83 return IsLP64 ? X86::LEA64r : X86::LEA32r; 84 } 85 86 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live 87 /// when it reaches the "return" instruction. We can then pop a stack object 88 /// to this register without worry about clobbering it. 89 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, 90 MachineBasicBlock::iterator &MBBI, 91 const TargetRegisterInfo &TRI, 92 bool Is64Bit) { 93 const MachineFunction *MF = MBB.getParent(); 94 const Function *F = MF->getFunction(); 95 if (!F || MF->getMMI().callsEHReturn()) 96 return 0; 97 98 static const uint16_t CallerSavedRegs32Bit[] = { 99 X86::EAX, X86::EDX, X86::ECX, 0 100 }; 101 102 static const uint16_t CallerSavedRegs64Bit[] = { 103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI, 104 X86::R8, X86::R9, X86::R10, X86::R11, 0 105 }; 106 107 unsigned Opc = MBBI->getOpcode(); 108 switch (Opc) { 109 default: return 0; 110 case X86::RET: 111 case X86::RETI: 112 case X86::TCRETURNdi: 113 case X86::TCRETURNri: 114 case X86::TCRETURNmi: 115 case X86::TCRETURNdi64: 116 case X86::TCRETURNri64: 117 case X86::TCRETURNmi64: 118 case X86::EH_RETURN: 119 case X86::EH_RETURN64: { 120 SmallSet<uint16_t, 8> Uses; 121 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) { 122 MachineOperand &MO = MBBI->getOperand(i); 123 if (!MO.isReg() || MO.isDef()) 124 continue; 125 unsigned Reg = MO.getReg(); 126 if (!Reg) 127 continue; 128 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI) 129 Uses.insert(*AI); 130 } 131 132 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit; 133 for (; *CS; ++CS) 134 if (!Uses.count(*CS)) 135 return *CS; 136 } 137 } 138 139 return 0; 140 } 141 142 143 /// emitSPUpdate - Emit a series of instructions to increment / decrement the 144 /// stack pointer by a constant value. 145 static 146 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 147 unsigned StackPtr, int64_t NumBytes, 148 bool Is64Bit, bool IsLP64, bool UseLEA, 149 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) { 150 bool isSub = NumBytes < 0; 151 uint64_t Offset = isSub ? -NumBytes : NumBytes; 152 unsigned Opc; 153 if (UseLEA) 154 Opc = getLEArOpcode(IsLP64); 155 else 156 Opc = isSub 157 ? getSUBriOpcode(IsLP64, Offset) 158 : getADDriOpcode(IsLP64, Offset); 159 160 uint64_t Chunk = (1LL << 31) - 1; 161 DebugLoc DL = MBB.findDebugLoc(MBBI); 162 163 while (Offset) { 164 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset; 165 if (ThisVal == (Is64Bit ? 8 : 4)) { 166 // Use push / pop instead. 167 unsigned Reg = isSub 168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX) 169 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit); 170 if (Reg) { 171 Opc = isSub 172 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r) 173 : (Is64Bit ? X86::POP64r : X86::POP32r); 174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) 175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); 176 if (isSub) 177 MI->setFlag(MachineInstr::FrameSetup); 178 Offset -= ThisVal; 179 continue; 180 } 181 } 182 183 MachineInstr *MI = NULL; 184 185 if (UseLEA) { 186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), 187 StackPtr, false, isSub ? -ThisVal : ThisVal); 188 } else { 189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) 190 .addReg(StackPtr) 191 .addImm(ThisVal); 192 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead. 193 } 194 195 if (isSub) 196 MI->setFlag(MachineInstr::FrameSetup); 197 198 Offset -= ThisVal; 199 } 200 } 201 202 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator. 203 static 204 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 205 unsigned StackPtr, uint64_t *NumBytes = NULL) { 206 if (MBBI == MBB.begin()) return; 207 208 MachineBasicBlock::iterator PI = prior(MBBI); 209 unsigned Opc = PI->getOpcode(); 210 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || 211 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 || 212 Opc == X86::LEA32r || Opc == X86::LEA64_32r) && 213 PI->getOperand(0).getReg() == StackPtr) { 214 if (NumBytes) 215 *NumBytes += PI->getOperand(2).getImm(); 216 MBB.erase(PI); 217 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 218 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && 219 PI->getOperand(0).getReg() == StackPtr) { 220 if (NumBytes) 221 *NumBytes -= PI->getOperand(2).getImm(); 222 MBB.erase(PI); 223 } 224 } 225 226 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator. 227 static 228 void mergeSPUpdatesDown(MachineBasicBlock &MBB, 229 MachineBasicBlock::iterator &MBBI, 230 unsigned StackPtr, uint64_t *NumBytes = NULL) { 231 // FIXME: THIS ISN'T RUN!!! 232 return; 233 234 if (MBBI == MBB.end()) return; 235 236 MachineBasicBlock::iterator NI = llvm::next(MBBI); 237 if (NI == MBB.end()) return; 238 239 unsigned Opc = NI->getOpcode(); 240 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || 241 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && 242 NI->getOperand(0).getReg() == StackPtr) { 243 if (NumBytes) 244 *NumBytes -= NI->getOperand(2).getImm(); 245 MBB.erase(NI); 246 MBBI = NI; 247 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 248 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && 249 NI->getOperand(0).getReg() == StackPtr) { 250 if (NumBytes) 251 *NumBytes += NI->getOperand(2).getImm(); 252 MBB.erase(NI); 253 MBBI = NI; 254 } 255 } 256 257 /// mergeSPUpdates - Checks the instruction before/after the passed 258 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and the 259 /// stack adjustment is returned as a positive value for ADD/LEA and a negative for 260 /// SUB. 261 static int mergeSPUpdates(MachineBasicBlock &MBB, 262 MachineBasicBlock::iterator &MBBI, 263 unsigned StackPtr, 264 bool doMergeWithPrevious) { 265 if ((doMergeWithPrevious && MBBI == MBB.begin()) || 266 (!doMergeWithPrevious && MBBI == MBB.end())) 267 return 0; 268 269 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI; 270 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI); 271 unsigned Opc = PI->getOpcode(); 272 int Offset = 0; 273 274 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || 275 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 || 276 Opc == X86::LEA32r || Opc == X86::LEA64_32r) && 277 PI->getOperand(0).getReg() == StackPtr){ 278 Offset += PI->getOperand(2).getImm(); 279 MBB.erase(PI); 280 if (!doMergeWithPrevious) MBBI = NI; 281 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 282 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && 283 PI->getOperand(0).getReg() == StackPtr) { 284 Offset -= PI->getOperand(2).getImm(); 285 MBB.erase(PI); 286 if (!doMergeWithPrevious) MBBI = NI; 287 } 288 289 return Offset; 290 } 291 292 static bool isEAXLiveIn(MachineFunction &MF) { 293 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(), 294 EE = MF.getRegInfo().livein_end(); II != EE; ++II) { 295 unsigned Reg = II->first; 296 297 if (Reg == X86::EAX || Reg == X86::AX || 298 Reg == X86::AH || Reg == X86::AL) 299 return true; 300 } 301 302 return false; 303 } 304 305 void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF, 306 MCSymbol *Label, 307 unsigned FramePtr) const { 308 MachineFrameInfo *MFI = MF.getFrameInfo(); 309 MachineModuleInfo &MMI = MF.getMMI(); 310 311 // Add callee saved registers to move list. 312 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 313 if (CSI.empty()) return; 314 315 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 316 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 317 bool HasFP = hasFP(MF); 318 319 // Calculate amount of bytes used for return address storing. 320 int stackGrowth = -RegInfo->getSlotSize(); 321 322 // FIXME: This is dirty hack. The code itself is pretty mess right now. 323 // It should be rewritten from scratch and generalized sometimes. 324 325 // Determine maximum offset (minimum due to stack growth). 326 int64_t MaxOffset = 0; 327 for (std::vector<CalleeSavedInfo>::const_iterator 328 I = CSI.begin(), E = CSI.end(); I != E; ++I) 329 MaxOffset = std::min(MaxOffset, 330 MFI->getObjectOffset(I->getFrameIdx())); 331 332 // Calculate offsets. 333 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth; 334 for (std::vector<CalleeSavedInfo>::const_iterator 335 I = CSI.begin(), E = CSI.end(); I != E; ++I) { 336 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); 337 unsigned Reg = I->getReg(); 338 Offset = MaxOffset - Offset + saveAreaOffset; 339 340 // Don't output a new machine move if we're re-saving the frame 341 // pointer. This happens when the PrologEpilogInserter has inserted an extra 342 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically 343 // generates one when frame pointers are used. If we generate a "machine 344 // move" for this extra "PUSH", the linker will lose track of the fact that 345 // the frame pointer should have the value of the first "PUSH" when it's 346 // trying to unwind. 347 // 348 // FIXME: This looks inelegant. It's possibly correct, but it's covering up 349 // another bug. I.e., one where we generate a prolog like this: 350 // 351 // pushl %ebp 352 // movl %esp, %ebp 353 // pushl %ebp 354 // pushl %esi 355 // ... 356 // 357 // The immediate re-push of EBP is unnecessary. At the least, it's an 358 // optimization bug. EBP can be used as a scratch register in certain 359 // cases, but probably not when we have a frame pointer. 360 if (HasFP && FramePtr == Reg) 361 continue; 362 363 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 364 MachineLocation CSSrc(Reg); 365 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 366 } 367 } 368 369 /// getCompactUnwindRegNum - Get the compact unwind number for a given 370 /// register. The number corresponds to the enum lists in 371 /// compact_unwind_encoding.h. 372 static int getCompactUnwindRegNum(const uint16_t *CURegs, unsigned Reg) { 373 for (int Idx = 1; *CURegs; ++CURegs, ++Idx) 374 if (*CURegs == Reg) 375 return Idx; 376 377 return -1; 378 } 379 380 // Number of registers that can be saved in a compact unwind encoding. 381 #define CU_NUM_SAVED_REGS 6 382 383 /// encodeCompactUnwindRegistersWithoutFrame - Create the permutation encoding 384 /// used with frameless stacks. It is passed the number of registers to be saved 385 /// and an array of the registers saved. 386 static uint32_t 387 encodeCompactUnwindRegistersWithoutFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS], 388 unsigned RegCount, bool Is64Bit) { 389 // The saved registers are numbered from 1 to 6. In order to encode the order 390 // in which they were saved, we re-number them according to their place in the 391 // register order. The re-numbering is relative to the last re-numbered 392 // register. E.g., if we have registers {6, 2, 4, 5} saved in that order: 393 // 394 // Orig Re-Num 395 // ---- ------ 396 // 6 6 397 // 2 2 398 // 4 3 399 // 5 3 400 // 401 static const uint16_t CU32BitRegs[] = { 402 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0 403 }; 404 static const uint16_t CU64BitRegs[] = { 405 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 406 }; 407 const uint16_t *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs); 408 409 for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) { 410 int CUReg = getCompactUnwindRegNum(CURegs, SavedRegs[i]); 411 if (CUReg == -1) return ~0U; 412 SavedRegs[i] = CUReg; 413 } 414 415 // Reverse the list. 416 std::swap(SavedRegs[0], SavedRegs[5]); 417 std::swap(SavedRegs[1], SavedRegs[4]); 418 std::swap(SavedRegs[2], SavedRegs[3]); 419 420 uint32_t RenumRegs[CU_NUM_SAVED_REGS]; 421 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i) { 422 unsigned Countless = 0; 423 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j) 424 if (SavedRegs[j] < SavedRegs[i]) 425 ++Countless; 426 427 RenumRegs[i] = SavedRegs[i] - Countless - 1; 428 } 429 430 // Take the renumbered values and encode them into a 10-bit number. 431 uint32_t permutationEncoding = 0; 432 switch (RegCount) { 433 case 6: 434 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1] 435 + 6 * RenumRegs[2] + 2 * RenumRegs[3] 436 + RenumRegs[4]; 437 break; 438 case 5: 439 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2] 440 + 6 * RenumRegs[3] + 2 * RenumRegs[4] 441 + RenumRegs[5]; 442 break; 443 case 4: 444 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3] 445 + 3 * RenumRegs[4] + RenumRegs[5]; 446 break; 447 case 3: 448 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4] 449 + RenumRegs[5]; 450 break; 451 case 2: 452 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5]; 453 break; 454 case 1: 455 permutationEncoding |= RenumRegs[5]; 456 break; 457 } 458 459 assert((permutationEncoding & 0x3FF) == permutationEncoding && 460 "Invalid compact register encoding!"); 461 return permutationEncoding; 462 } 463 464 /// encodeCompactUnwindRegistersWithFrame - Return the registers encoded for a 465 /// compact encoding with a frame pointer. 466 static uint32_t 467 encodeCompactUnwindRegistersWithFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS], 468 bool Is64Bit) { 469 static const uint16_t CU32BitRegs[] = { 470 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0 471 }; 472 static const uint16_t CU64BitRegs[] = { 473 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 474 }; 475 const uint16_t *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs); 476 477 // Encode the registers in the order they were saved, 3-bits per register. The 478 // registers are numbered from 1 to CU_NUM_SAVED_REGS. 479 uint32_t RegEnc = 0; 480 for (int I = CU_NUM_SAVED_REGS - 1, Idx = 0; I != -1; --I) { 481 unsigned Reg = SavedRegs[I]; 482 if (Reg == 0) continue; 483 484 int CURegNum = getCompactUnwindRegNum(CURegs, Reg); 485 if (CURegNum == -1) return ~0U; 486 487 // Encode the 3-bit register number in order, skipping over 3-bits for each 488 // register. 489 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3); 490 } 491 492 assert((RegEnc & 0x3FFFF) == RegEnc && "Invalid compact register encoding!"); 493 return RegEnc; 494 } 495 496 uint32_t X86FrameLowering::getCompactUnwindEncoding(MachineFunction &MF) const { 497 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 498 unsigned FramePtr = RegInfo->getFrameRegister(MF); 499 unsigned StackPtr = RegInfo->getStackRegister(); 500 501 bool Is64Bit = STI.is64Bit(); 502 bool HasFP = hasFP(MF); 503 504 unsigned SavedRegs[CU_NUM_SAVED_REGS] = { 0, 0, 0, 0, 0, 0 }; 505 unsigned SavedRegIdx = 0; 506 507 unsigned OffsetSize = (Is64Bit ? 8 : 4); 508 509 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r); 510 unsigned PushInstrSize = 1; 511 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr); 512 unsigned MoveInstrSize = (Is64Bit ? 3 : 2); 513 unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2); 514 515 unsigned StackDivide = (Is64Bit ? 8 : 4); 516 517 unsigned InstrOffset = 0; 518 unsigned StackAdjust = 0; 519 unsigned StackSize = 0; 520 521 MachineBasicBlock &MBB = MF.front(); // Prologue is in entry BB. 522 bool ExpectEnd = false; 523 for (MachineBasicBlock::iterator 524 MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ++MBBI) { 525 MachineInstr &MI = *MBBI; 526 unsigned Opc = MI.getOpcode(); 527 if (Opc == X86::PROLOG_LABEL) continue; 528 if (!MI.getFlag(MachineInstr::FrameSetup)) break; 529 530 // We don't exect any more prolog instructions. 531 if (ExpectEnd) return 0; 532 533 if (Opc == PushInstr) { 534 // If there are too many saved registers, we cannot use compact encoding. 535 if (SavedRegIdx >= CU_NUM_SAVED_REGS) return 0; 536 537 SavedRegs[SavedRegIdx++] = MI.getOperand(0).getReg(); 538 StackAdjust += OffsetSize; 539 InstrOffset += PushInstrSize; 540 } else if (Opc == MoveInstr) { 541 unsigned SrcReg = MI.getOperand(1).getReg(); 542 unsigned DstReg = MI.getOperand(0).getReg(); 543 544 if (DstReg != FramePtr || SrcReg != StackPtr) 545 return 0; 546 547 StackAdjust = 0; 548 memset(SavedRegs, 0, sizeof(SavedRegs)); 549 SavedRegIdx = 0; 550 InstrOffset += MoveInstrSize; 551 } else if (Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 552 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) { 553 if (StackSize) 554 // We already have a stack size. 555 return 0; 556 557 if (!MI.getOperand(0).isReg() || 558 MI.getOperand(0).getReg() != MI.getOperand(1).getReg() || 559 MI.getOperand(0).getReg() != StackPtr || !MI.getOperand(2).isImm()) 560 // We need this to be a stack adjustment pointer. Something like: 561 // 562 // %RSP<def> = SUB64ri8 %RSP, 48 563 return 0; 564 565 StackSize = MI.getOperand(2).getImm() / StackDivide; 566 SubtractInstrIdx += InstrOffset; 567 ExpectEnd = true; 568 } 569 } 570 571 // Encode that we are using EBP/RBP as the frame pointer. 572 uint32_t CompactUnwindEncoding = 0; 573 StackAdjust /= StackDivide; 574 if (HasFP) { 575 if ((StackAdjust & 0xFF) != StackAdjust) 576 // Offset was too big for compact encoding. 577 return 0; 578 579 // Get the encoding of the saved registers when we have a frame pointer. 580 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit); 581 if (RegEnc == ~0U) return 0; 582 583 CompactUnwindEncoding |= 0x01000000; 584 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16; 585 CompactUnwindEncoding |= RegEnc & 0x7FFF; 586 } else { 587 ++StackAdjust; 588 uint32_t TotalStackSize = StackAdjust + StackSize; 589 if ((TotalStackSize & 0xFF) == TotalStackSize) { 590 // Frameless stack with a small stack size. 591 CompactUnwindEncoding |= 0x02000000; 592 593 // Encode the stack size. 594 CompactUnwindEncoding |= (TotalStackSize & 0xFF) << 16; 595 } else { 596 if ((StackAdjust & 0x7) != StackAdjust) 597 // The extra stack adjustments are too big for us to handle. 598 return 0; 599 600 // Frameless stack with an offset too large for us to encode compactly. 601 CompactUnwindEncoding |= 0x03000000; 602 603 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP' 604 // instruction. 605 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16; 606 607 // Encode any extra stack stack adjustments (done via push instructions). 608 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13; 609 } 610 611 // Encode the number of registers saved. 612 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10; 613 614 // Get the encoding of the saved registers when we don't have a frame 615 // pointer. 616 uint32_t RegEnc = 617 encodeCompactUnwindRegistersWithoutFrame(SavedRegs, SavedRegIdx, 618 Is64Bit); 619 if (RegEnc == ~0U) return 0; 620 621 // Encode the register encoding. 622 CompactUnwindEncoding |= RegEnc & 0x3FF; 623 } 624 625 return CompactUnwindEncoding; 626 } 627 628 /// usesTheStack - This function checks if any of the users of EFLAGS 629 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has 630 /// to use the stack, and if we don't adjust the stack we clobber the first 631 /// frame index. 632 /// See X86InstrInfo::copyPhysReg. 633 static bool usesTheStack(MachineFunction &MF) { 634 MachineRegisterInfo &MRI = MF.getRegInfo(); 635 636 for (MachineRegisterInfo::reg_iterator ri = MRI.reg_begin(X86::EFLAGS), 637 re = MRI.reg_end(); ri != re; ++ri) 638 if (ri->isCopy()) 639 return true; 640 641 return false; 642 } 643 644 /// emitPrologue - Push callee-saved registers onto the stack, which 645 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate 646 /// space for local variables. Also emit labels used by the exception handler to 647 /// generate the exception handling frames. 648 void X86FrameLowering::emitPrologue(MachineFunction &MF) const { 649 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB. 650 MachineBasicBlock::iterator MBBI = MBB.begin(); 651 MachineFrameInfo *MFI = MF.getFrameInfo(); 652 const Function *Fn = MF.getFunction(); 653 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 654 const X86InstrInfo &TII = *TM.getInstrInfo(); 655 MachineModuleInfo &MMI = MF.getMMI(); 656 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 657 bool needsFrameMoves = MMI.hasDebugInfo() || 658 Fn->needsUnwindTableEntry(); 659 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment. 660 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate. 661 bool HasFP = hasFP(MF); 662 bool Is64Bit = STI.is64Bit(); 663 bool IsLP64 = STI.isTarget64BitLP64(); 664 bool IsWin64 = STI.isTargetWin64(); 665 bool UseLEA = STI.useLeaForSP(); 666 unsigned StackAlign = getStackAlignment(); 667 unsigned SlotSize = RegInfo->getSlotSize(); 668 unsigned FramePtr = RegInfo->getFrameRegister(MF); 669 unsigned StackPtr = RegInfo->getStackRegister(); 670 unsigned BasePtr = RegInfo->getBaseRegister(); 671 DebugLoc DL; 672 673 // If we're forcing a stack realignment we can't rely on just the frame 674 // info, we need to know the ABI stack alignment as well in case we 675 // have a call out. Otherwise just make sure we have some alignment - we'll 676 // go with the minimum SlotSize. 677 if (ForceStackAlign) { 678 if (MFI->hasCalls()) 679 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign; 680 else if (MaxAlign < SlotSize) 681 MaxAlign = SlotSize; 682 } 683 684 // Add RETADDR move area to callee saved frame size. 685 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); 686 if (TailCallReturnAddrDelta < 0) 687 X86FI->setCalleeSavedFrameSize( 688 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta); 689 690 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf 691 // function, and use up to 128 bytes of stack space, don't have a frame 692 // pointer, calls, or dynamic alloca then we do not need to adjust the 693 // stack pointer (we fit in the Red Zone). We also check that we don't 694 // push and pop from the stack. 695 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 696 Attribute::NoRedZone) && 697 !RegInfo->needsStackRealignment(MF) && 698 !MFI->hasVarSizedObjects() && // No dynamic alloca. 699 !MFI->adjustsStack() && // No calls. 700 !IsWin64 && // Win64 has no Red Zone 701 !usesTheStack(MF) && // Don't push and pop. 702 !MF.getTarget().Options.EnableSegmentedStacks) { // Regular stack 703 uint64_t MinSize = X86FI->getCalleeSavedFrameSize(); 704 if (HasFP) MinSize += SlotSize; 705 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0); 706 MFI->setStackSize(StackSize); 707 } 708 709 // Insert stack pointer adjustment for later moving of return addr. Only 710 // applies to tail call optimized functions where the callee argument stack 711 // size is bigger than the callers. 712 if (TailCallReturnAddrDelta < 0) { 713 MachineInstr *MI = 714 BuildMI(MBB, MBBI, DL, 715 TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)), 716 StackPtr) 717 .addReg(StackPtr) 718 .addImm(-TailCallReturnAddrDelta) 719 .setMIFlag(MachineInstr::FrameSetup); 720 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead. 721 } 722 723 // Mapping for machine moves: 724 // 725 // DST: VirtualFP AND 726 // SRC: VirtualFP => DW_CFA_def_cfa_offset 727 // ELSE => DW_CFA_def_cfa 728 // 729 // SRC: VirtualFP AND 730 // DST: Register => DW_CFA_def_cfa_register 731 // 732 // ELSE 733 // OFFSET < 0 => DW_CFA_offset_extended_sf 734 // REG < 64 => DW_CFA_offset + Reg 735 // ELSE => DW_CFA_offset_extended 736 737 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 738 uint64_t NumBytes = 0; 739 int stackGrowth = -SlotSize; 740 741 if (HasFP) { 742 // Calculate required stack adjustment. 743 uint64_t FrameSize = StackSize - SlotSize; 744 if (RegInfo->needsStackRealignment(MF)) { 745 // Callee-saved registers are pushed on stack before the stack 746 // is realigned. 747 FrameSize -= X86FI->getCalleeSavedFrameSize(); 748 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign; 749 } else { 750 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize(); 751 } 752 753 // Get the offset of the stack slot for the EBP register, which is 754 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. 755 // Update the frame offset adjustment. 756 MFI->setOffsetAdjustment(-NumBytes); 757 758 // Save EBP/RBP into the appropriate stack slot. 759 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) 760 .addReg(FramePtr, RegState::Kill) 761 .setMIFlag(MachineInstr::FrameSetup); 762 763 if (needsFrameMoves) { 764 // Mark the place where EBP/RBP was saved. 765 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); 766 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)) 767 .addSym(FrameLabel); 768 769 // Define the current CFA rule to use the provided offset. 770 if (StackSize) { 771 MachineLocation SPDst(MachineLocation::VirtualFP); 772 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth); 773 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 774 } else { 775 MachineLocation SPDst(StackPtr); 776 MachineLocation SPSrc(StackPtr, stackGrowth); 777 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 778 } 779 780 // Change the rule for the FramePtr to be an "offset" rule. 781 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth); 782 MachineLocation FPSrc(FramePtr); 783 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 784 } 785 786 // Update EBP with the new base value. 787 BuildMI(MBB, MBBI, DL, 788 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) 789 .addReg(StackPtr) 790 .setMIFlag(MachineInstr::FrameSetup); 791 792 if (needsFrameMoves) { 793 // Mark effective beginning of when frame pointer becomes valid. 794 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); 795 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)) 796 .addSym(FrameLabel); 797 798 // Define the current CFA to use the EBP/RBP register. 799 MachineLocation FPDst(FramePtr); 800 MachineLocation FPSrc(MachineLocation::VirtualFP); 801 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 802 } 803 804 // Mark the FramePtr as live-in in every block except the entry. 805 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end(); 806 I != E; ++I) 807 I->addLiveIn(FramePtr); 808 } else { 809 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize(); 810 } 811 812 // Skip the callee-saved push instructions. 813 bool PushedRegs = false; 814 int StackOffset = 2 * stackGrowth; 815 816 while (MBBI != MBB.end() && 817 (MBBI->getOpcode() == X86::PUSH32r || 818 MBBI->getOpcode() == X86::PUSH64r)) { 819 PushedRegs = true; 820 MBBI->setFlag(MachineInstr::FrameSetup); 821 ++MBBI; 822 823 if (!HasFP && needsFrameMoves) { 824 // Mark callee-saved push instruction. 825 MCSymbol *Label = MMI.getContext().CreateTempSymbol(); 826 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label); 827 828 // Define the current CFA rule to use the provided offset. 829 unsigned Ptr = StackSize ? MachineLocation::VirtualFP : StackPtr; 830 MachineLocation SPDst(Ptr); 831 MachineLocation SPSrc(Ptr, StackOffset); 832 Moves.push_back(MachineMove(Label, SPDst, SPSrc)); 833 StackOffset += stackGrowth; 834 } 835 } 836 837 // Realign stack after we pushed callee-saved registers (so that we'll be 838 // able to calculate their offsets from the frame pointer). 839 840 // NOTE: We push the registers before realigning the stack, so 841 // vector callee-saved (xmm) registers may be saved w/o proper 842 // alignment in this way. However, currently these regs are saved in 843 // stack slots (see X86FrameLowering::spillCalleeSavedRegisters()), so 844 // this shouldn't be a problem. 845 if (RegInfo->needsStackRealignment(MF)) { 846 assert(HasFP && "There should be a frame pointer if stack is realigned."); 847 MachineInstr *MI = 848 BuildMI(MBB, MBBI, DL, 849 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr) 850 .addReg(StackPtr) 851 .addImm(-MaxAlign) 852 .setMIFlag(MachineInstr::FrameSetup); 853 854 // The EFLAGS implicit def is dead. 855 MI->getOperand(3).setIsDead(); 856 } 857 858 // If there is an SUB32ri of ESP immediately before this instruction, merge 859 // the two. This can be the case when tail call elimination is enabled and 860 // the callee has more arguments then the caller. 861 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true); 862 863 // If there is an ADD32ri or SUB32ri of ESP immediately after this 864 // instruction, merge the two instructions. 865 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes); 866 867 // Adjust stack pointer: ESP -= numbytes. 868 869 // Windows and cygwin/mingw require a prologue helper routine when allocating 870 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw 871 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the 872 // stack and adjust the stack pointer in one go. The 64-bit version of 873 // __chkstk is only responsible for probing the stack. The 64-bit prologue is 874 // responsible for adjusting the stack pointer. Touching the stack at 4K 875 // increments is necessary to ensure that the guard pages used by the OS 876 // virtual memory manager are allocated in correct sequence. 877 if (NumBytes >= 4096 && STI.isTargetCOFF() && !STI.isTargetEnvMacho()) { 878 const char *StackProbeSymbol; 879 bool isSPUpdateNeeded = false; 880 881 if (Is64Bit) { 882 if (STI.isTargetCygMing()) 883 StackProbeSymbol = "___chkstk"; 884 else { 885 StackProbeSymbol = "__chkstk"; 886 isSPUpdateNeeded = true; 887 } 888 } else if (STI.isTargetCygMing()) 889 StackProbeSymbol = "_alloca"; 890 else 891 StackProbeSymbol = "_chkstk"; 892 893 // Check whether EAX is livein for this function. 894 bool isEAXAlive = isEAXLiveIn(MF); 895 896 if (isEAXAlive) { 897 // Sanity check that EAX is not livein for this function. 898 // It should not be, so throw an assert. 899 assert(!Is64Bit && "EAX is livein in x64 case!"); 900 901 // Save EAX 902 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r)) 903 .addReg(X86::EAX, RegState::Kill) 904 .setMIFlag(MachineInstr::FrameSetup); 905 } 906 907 if (Is64Bit) { 908 // Handle the 64-bit Windows ABI case where we need to call __chkstk. 909 // Function prologue is responsible for adjusting the stack pointer. 910 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX) 911 .addImm(NumBytes) 912 .setMIFlag(MachineInstr::FrameSetup); 913 } else { 914 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive. 915 // We'll also use 4 already allocated bytes for EAX. 916 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) 917 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes) 918 .setMIFlag(MachineInstr::FrameSetup); 919 } 920 921 BuildMI(MBB, MBBI, DL, 922 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32)) 923 .addExternalSymbol(StackProbeSymbol) 924 .addReg(StackPtr, RegState::Define | RegState::Implicit) 925 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit) 926 .setMIFlag(MachineInstr::FrameSetup); 927 928 // MSVC x64's __chkstk needs to adjust %rsp. 929 // FIXME: %rax preserves the offset and should be available. 930 if (isSPUpdateNeeded) 931 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64, 932 UseLEA, TII, *RegInfo); 933 934 if (isEAXAlive) { 935 // Restore EAX 936 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), 937 X86::EAX), 938 StackPtr, false, NumBytes - 4); 939 MI->setFlag(MachineInstr::FrameSetup); 940 MBB.insert(MBBI, MI); 941 } 942 } else if (NumBytes) 943 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64, 944 UseLEA, TII, *RegInfo); 945 946 // If we need a base pointer, set it up here. It's whatever the value 947 // of the stack pointer is at this point. Any variable size objects 948 // will be allocated after this, so we can still use the base pointer 949 // to reference locals. 950 if (RegInfo->hasBasePointer(MF)) { 951 // Update the frame pointer with the current stack pointer. 952 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr; 953 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr) 954 .addReg(StackPtr) 955 .setMIFlag(MachineInstr::FrameSetup); 956 } 957 958 if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) { 959 // Mark end of stack pointer adjustment. 960 MCSymbol *Label = MMI.getContext().CreateTempSymbol(); 961 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)) 962 .addSym(Label); 963 964 if (!HasFP && NumBytes) { 965 // Define the current CFA rule to use the provided offset. 966 if (StackSize) { 967 MachineLocation SPDst(MachineLocation::VirtualFP); 968 MachineLocation SPSrc(MachineLocation::VirtualFP, 969 -StackSize + stackGrowth); 970 Moves.push_back(MachineMove(Label, SPDst, SPSrc)); 971 } else { 972 MachineLocation SPDst(StackPtr); 973 MachineLocation SPSrc(StackPtr, stackGrowth); 974 Moves.push_back(MachineMove(Label, SPDst, SPSrc)); 975 } 976 } 977 978 // Emit DWARF info specifying the offsets of the callee-saved registers. 979 if (PushedRegs) 980 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr); 981 } 982 983 // Darwin 10.7 and greater has support for compact unwind encoding. 984 if (STI.getTargetTriple().isMacOSX() && 985 !STI.getTargetTriple().isMacOSXVersionLT(10, 7)) 986 MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF)); 987 } 988 989 void X86FrameLowering::emitEpilogue(MachineFunction &MF, 990 MachineBasicBlock &MBB) const { 991 const MachineFrameInfo *MFI = MF.getFrameInfo(); 992 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 993 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 994 const X86InstrInfo &TII = *TM.getInstrInfo(); 995 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 996 assert(MBBI != MBB.end() && "Returning block has no instructions"); 997 unsigned RetOpcode = MBBI->getOpcode(); 998 DebugLoc DL = MBBI->getDebugLoc(); 999 bool Is64Bit = STI.is64Bit(); 1000 bool IsLP64 = STI.isTarget64BitLP64(); 1001 bool UseLEA = STI.useLeaForSP(); 1002 unsigned StackAlign = getStackAlignment(); 1003 unsigned SlotSize = RegInfo->getSlotSize(); 1004 unsigned FramePtr = RegInfo->getFrameRegister(MF); 1005 unsigned StackPtr = RegInfo->getStackRegister(); 1006 1007 switch (RetOpcode) { 1008 default: 1009 llvm_unreachable("Can only insert epilog into returning blocks"); 1010 case X86::RET: 1011 case X86::RETI: 1012 case X86::TCRETURNdi: 1013 case X86::TCRETURNri: 1014 case X86::TCRETURNmi: 1015 case X86::TCRETURNdi64: 1016 case X86::TCRETURNri64: 1017 case X86::TCRETURNmi64: 1018 case X86::EH_RETURN: 1019 case X86::EH_RETURN64: 1020 break; // These are ok 1021 } 1022 1023 // Get the number of bytes to allocate from the FrameInfo. 1024 uint64_t StackSize = MFI->getStackSize(); 1025 uint64_t MaxAlign = MFI->getMaxAlignment(); 1026 unsigned CSSize = X86FI->getCalleeSavedFrameSize(); 1027 uint64_t NumBytes = 0; 1028 1029 // If we're forcing a stack realignment we can't rely on just the frame 1030 // info, we need to know the ABI stack alignment as well in case we 1031 // have a call out. Otherwise just make sure we have some alignment - we'll 1032 // go with the minimum. 1033 if (ForceStackAlign) { 1034 if (MFI->hasCalls()) 1035 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign; 1036 else 1037 MaxAlign = MaxAlign ? MaxAlign : 4; 1038 } 1039 1040 if (hasFP(MF)) { 1041 // Calculate required stack adjustment. 1042 uint64_t FrameSize = StackSize - SlotSize; 1043 if (RegInfo->needsStackRealignment(MF)) { 1044 // Callee-saved registers were pushed on stack before the stack 1045 // was realigned. 1046 FrameSize -= CSSize; 1047 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign; 1048 } else { 1049 NumBytes = FrameSize - CSSize; 1050 } 1051 1052 // Pop EBP. 1053 BuildMI(MBB, MBBI, DL, 1054 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr); 1055 } else { 1056 NumBytes = StackSize - CSSize; 1057 } 1058 1059 // Skip the callee-saved pop instructions. 1060 while (MBBI != MBB.begin()) { 1061 MachineBasicBlock::iterator PI = prior(MBBI); 1062 unsigned Opc = PI->getOpcode(); 1063 1064 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE && 1065 !PI->isTerminator()) 1066 break; 1067 1068 --MBBI; 1069 } 1070 MachineBasicBlock::iterator FirstCSPop = MBBI; 1071 1072 DL = MBBI->getDebugLoc(); 1073 1074 // If there is an ADD32ri or SUB32ri of ESP immediately before this 1075 // instruction, merge the two instructions. 1076 if (NumBytes || MFI->hasVarSizedObjects()) 1077 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes); 1078 1079 // If dynamic alloca is used, then reset esp to point to the last callee-saved 1080 // slot before popping them off! Same applies for the case, when stack was 1081 // realigned. 1082 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) { 1083 if (RegInfo->needsStackRealignment(MF)) 1084 MBBI = FirstCSPop; 1085 if (CSSize != 0) { 1086 unsigned Opc = getLEArOpcode(IsLP64); 1087 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), 1088 FramePtr, false, -CSSize); 1089 } else { 1090 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr); 1091 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) 1092 .addReg(FramePtr); 1093 } 1094 } else if (NumBytes) { 1095 // Adjust stack pointer back: ESP += numbytes. 1096 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, IsLP64, UseLEA, 1097 TII, *RegInfo); 1098 } 1099 1100 // We're returning from function via eh_return. 1101 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) { 1102 MBBI = MBB.getLastNonDebugInstr(); 1103 MachineOperand &DestAddr = MBBI->getOperand(0); 1104 assert(DestAddr.isReg() && "Offset should be in register!"); 1105 BuildMI(MBB, MBBI, DL, 1106 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), 1107 StackPtr).addReg(DestAddr.getReg()); 1108 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi || 1109 RetOpcode == X86::TCRETURNmi || 1110 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 || 1111 RetOpcode == X86::TCRETURNmi64) { 1112 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64; 1113 // Tail call return: adjust the stack pointer and jump to callee. 1114 MBBI = MBB.getLastNonDebugInstr(); 1115 MachineOperand &JumpTarget = MBBI->getOperand(0); 1116 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1); 1117 assert(StackAdjust.isImm() && "Expecting immediate value."); 1118 1119 // Adjust stack pointer. 1120 int StackAdj = StackAdjust.getImm(); 1121 int MaxTCDelta = X86FI->getTCReturnAddrDelta(); 1122 int Offset = 0; 1123 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive"); 1124 1125 // Incoporate the retaddr area. 1126 Offset = StackAdj-MaxTCDelta; 1127 assert(Offset >= 0 && "Offset should never be negative"); 1128 1129 if (Offset) { 1130 // Check for possible merge with preceding ADD instruction. 1131 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true); 1132 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, IsLP64, 1133 UseLEA, TII, *RegInfo); 1134 } 1135 1136 // Jump to label or value in register. 1137 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) { 1138 MachineInstrBuilder MIB = 1139 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi) 1140 ? X86::TAILJMPd : X86::TAILJMPd64)); 1141 if (JumpTarget.isGlobal()) 1142 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 1143 JumpTarget.getTargetFlags()); 1144 else { 1145 assert(JumpTarget.isSymbol()); 1146 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 1147 JumpTarget.getTargetFlags()); 1148 } 1149 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) { 1150 MachineInstrBuilder MIB = 1151 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi) 1152 ? X86::TAILJMPm : X86::TAILJMPm64)); 1153 for (unsigned i = 0; i != 5; ++i) 1154 MIB.addOperand(MBBI->getOperand(i)); 1155 } else if (RetOpcode == X86::TCRETURNri64) { 1156 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)). 1157 addReg(JumpTarget.getReg(), RegState::Kill); 1158 } else { 1159 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)). 1160 addReg(JumpTarget.getReg(), RegState::Kill); 1161 } 1162 1163 MachineInstr *NewMI = prior(MBBI); 1164 NewMI->copyImplicitOps(MF, MBBI); 1165 1166 // Delete the pseudo instruction TCRETURN. 1167 MBB.erase(MBBI); 1168 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) && 1169 (X86FI->getTCReturnAddrDelta() < 0)) { 1170 // Add the return addr area delta back since we are not tail calling. 1171 int delta = -1*X86FI->getTCReturnAddrDelta(); 1172 MBBI = MBB.getLastNonDebugInstr(); 1173 1174 // Check for possible merge with preceding ADD instruction. 1175 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true); 1176 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, IsLP64, UseLEA, TII, 1177 *RegInfo); 1178 } 1179 } 1180 1181 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const { 1182 const X86RegisterInfo *RegInfo = 1183 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo()); 1184 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1185 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea(); 1186 uint64_t StackSize = MFI->getStackSize(); 1187 1188 if (RegInfo->hasBasePointer(MF)) { 1189 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!"); 1190 if (FI < 0) { 1191 // Skip the saved EBP. 1192 return Offset + RegInfo->getSlotSize(); 1193 } else { 1194 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0); 1195 return Offset + StackSize; 1196 } 1197 } else if (RegInfo->needsStackRealignment(MF)) { 1198 if (FI < 0) { 1199 // Skip the saved EBP. 1200 return Offset + RegInfo->getSlotSize(); 1201 } else { 1202 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0); 1203 return Offset + StackSize; 1204 } 1205 // FIXME: Support tail calls 1206 } else { 1207 if (!hasFP(MF)) 1208 return Offset + StackSize; 1209 1210 // Skip the saved EBP. 1211 Offset += RegInfo->getSlotSize(); 1212 1213 // Skip the RETADDR move area 1214 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1215 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); 1216 if (TailCallReturnAddrDelta < 0) 1217 Offset -= TailCallReturnAddrDelta; 1218 } 1219 1220 return Offset; 1221 } 1222 1223 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, 1224 unsigned &FrameReg) const { 1225 const X86RegisterInfo *RegInfo = 1226 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo()); 1227 // We can't calculate offset from frame pointer if the stack is realigned, 1228 // so enforce usage of stack/base pointer. The base pointer is used when we 1229 // have dynamic allocas in addition to dynamic realignment. 1230 if (RegInfo->hasBasePointer(MF)) 1231 FrameReg = RegInfo->getBaseRegister(); 1232 else if (RegInfo->needsStackRealignment(MF)) 1233 FrameReg = RegInfo->getStackRegister(); 1234 else 1235 FrameReg = RegInfo->getFrameRegister(MF); 1236 return getFrameIndexOffset(MF, FI); 1237 } 1238 1239 bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1240 MachineBasicBlock::iterator MI, 1241 const std::vector<CalleeSavedInfo> &CSI, 1242 const TargetRegisterInfo *TRI) const { 1243 if (CSI.empty()) 1244 return false; 1245 1246 DebugLoc DL = MBB.findDebugLoc(MI); 1247 1248 MachineFunction &MF = *MBB.getParent(); 1249 1250 unsigned SlotSize = STI.is64Bit() ? 8 : 4; 1251 unsigned FPReg = TRI->getFrameRegister(MF); 1252 unsigned CalleeFrameSize = 0; 1253 1254 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 1255 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1256 1257 // Push GPRs. It increases frame size. 1258 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r; 1259 for (unsigned i = CSI.size(); i != 0; --i) { 1260 unsigned Reg = CSI[i-1].getReg(); 1261 if (!X86::GR64RegClass.contains(Reg) && 1262 !X86::GR32RegClass.contains(Reg)) 1263 continue; 1264 // Add the callee-saved register as live-in. It's killed at the spill. 1265 MBB.addLiveIn(Reg); 1266 if (Reg == FPReg) 1267 // X86RegisterInfo::emitPrologue will handle spilling of frame register. 1268 continue; 1269 CalleeFrameSize += SlotSize; 1270 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill) 1271 .setMIFlag(MachineInstr::FrameSetup); 1272 } 1273 1274 X86FI->setCalleeSavedFrameSize(CalleeFrameSize); 1275 1276 // Make XMM regs spilled. X86 does not have ability of push/pop XMM. 1277 // It can be done by spilling XMMs to stack frame. 1278 // Note that only Win64 ABI might spill XMMs. 1279 for (unsigned i = CSI.size(); i != 0; --i) { 1280 unsigned Reg = CSI[i-1].getReg(); 1281 if (X86::GR64RegClass.contains(Reg) || 1282 X86::GR32RegClass.contains(Reg)) 1283 continue; 1284 // Add the callee-saved register as live-in. It's killed at the spill. 1285 MBB.addLiveIn(Reg); 1286 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1287 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), 1288 RC, TRI); 1289 } 1290 1291 return true; 1292 } 1293 1294 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1295 MachineBasicBlock::iterator MI, 1296 const std::vector<CalleeSavedInfo> &CSI, 1297 const TargetRegisterInfo *TRI) const { 1298 if (CSI.empty()) 1299 return false; 1300 1301 DebugLoc DL = MBB.findDebugLoc(MI); 1302 1303 MachineFunction &MF = *MBB.getParent(); 1304 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 1305 1306 // Reload XMMs from stack frame. 1307 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1308 unsigned Reg = CSI[i].getReg(); 1309 if (X86::GR64RegClass.contains(Reg) || 1310 X86::GR32RegClass.contains(Reg)) 1311 continue; 1312 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1313 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), 1314 RC, TRI); 1315 } 1316 1317 // POP GPRs. 1318 unsigned FPReg = TRI->getFrameRegister(MF); 1319 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r; 1320 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1321 unsigned Reg = CSI[i].getReg(); 1322 if (!X86::GR64RegClass.contains(Reg) && 1323 !X86::GR32RegClass.contains(Reg)) 1324 continue; 1325 if (Reg == FPReg) 1326 // X86RegisterInfo::emitEpilogue will handle restoring of frame register. 1327 continue; 1328 BuildMI(MBB, MI, DL, TII.get(Opc), Reg); 1329 } 1330 return true; 1331 } 1332 1333 void 1334 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1335 RegScavenger *RS) const { 1336 MachineFrameInfo *MFI = MF.getFrameInfo(); 1337 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 1338 unsigned SlotSize = RegInfo->getSlotSize(); 1339 1340 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1341 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); 1342 1343 if (TailCallReturnAddrDelta < 0) { 1344 // create RETURNADDR area 1345 // arg 1346 // arg 1347 // RETADDR 1348 // { ... 1349 // RETADDR area 1350 // ... 1351 // } 1352 // [EBP] 1353 MFI->CreateFixedObject(-TailCallReturnAddrDelta, 1354 (-1U*SlotSize)+TailCallReturnAddrDelta, true); 1355 } 1356 1357 if (hasFP(MF)) { 1358 assert((TailCallReturnAddrDelta <= 0) && 1359 "The Delta should always be zero or negative"); 1360 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering(); 1361 1362 // Create a frame entry for the EBP register that must be saved. 1363 int FrameIdx = MFI->CreateFixedObject(SlotSize, 1364 -(int)SlotSize + 1365 TFI.getOffsetOfLocalArea() + 1366 TailCallReturnAddrDelta, 1367 true); 1368 assert(FrameIdx == MFI->getObjectIndexBegin() && 1369 "Slot for EBP register must be last in order to be found!"); 1370 (void)FrameIdx; 1371 } 1372 1373 // Spill the BasePtr if it's used. 1374 if (RegInfo->hasBasePointer(MF)) 1375 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister()); 1376 } 1377 1378 static bool 1379 HasNestArgument(const MachineFunction *MF) { 1380 const Function *F = MF->getFunction(); 1381 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 1382 I != E; I++) { 1383 if (I->hasNestAttr()) 1384 return true; 1385 } 1386 return false; 1387 } 1388 1389 /// GetScratchRegister - Get a temp register for performing work in the 1390 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform 1391 /// and the properties of the function either one or two registers will be 1392 /// needed. Set primary to true for the first register, false for the second. 1393 static unsigned 1394 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) { 1395 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv(); 1396 1397 // Erlang stuff. 1398 if (CallingConvention == CallingConv::HiPE) { 1399 if (Is64Bit) 1400 return Primary ? X86::R14 : X86::R13; 1401 else 1402 return Primary ? X86::EBX : X86::EDI; 1403 } 1404 1405 if (Is64Bit) 1406 return Primary ? X86::R11 : X86::R12; 1407 1408 bool IsNested = HasNestArgument(&MF); 1409 1410 if (CallingConvention == CallingConv::X86_FastCall || 1411 CallingConvention == CallingConv::Fast) { 1412 if (IsNested) 1413 report_fatal_error("Segmented stacks does not support fastcall with " 1414 "nested function."); 1415 return Primary ? X86::EAX : X86::ECX; 1416 } 1417 if (IsNested) 1418 return Primary ? X86::EDX : X86::EAX; 1419 return Primary ? X86::ECX : X86::EAX; 1420 } 1421 1422 // The stack limit in the TCB is set to this many bytes above the actual stack 1423 // limit. 1424 static const uint64_t kSplitStackAvailable = 256; 1425 1426 void 1427 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const { 1428 MachineBasicBlock &prologueMBB = MF.front(); 1429 MachineFrameInfo *MFI = MF.getFrameInfo(); 1430 const X86InstrInfo &TII = *TM.getInstrInfo(); 1431 uint64_t StackSize; 1432 bool Is64Bit = STI.is64Bit(); 1433 unsigned TlsReg, TlsOffset; 1434 DebugLoc DL; 1435 1436 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true); 1437 assert(!MF.getRegInfo().isLiveIn(ScratchReg) && 1438 "Scratch register is live-in"); 1439 1440 if (MF.getFunction()->isVarArg()) 1441 report_fatal_error("Segmented stacks do not support vararg functions."); 1442 if (!STI.isTargetLinux() && !STI.isTargetDarwin() && 1443 !STI.isTargetWin32() && !STI.isTargetFreeBSD()) 1444 report_fatal_error("Segmented stacks not supported on this platform."); 1445 1446 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock(); 1447 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock(); 1448 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1449 bool IsNested = false; 1450 1451 // We need to know if the function has a nest argument only in 64 bit mode. 1452 if (Is64Bit) 1453 IsNested = HasNestArgument(&MF); 1454 1455 // The MOV R10, RAX needs to be in a different block, since the RET we emit in 1456 // allocMBB needs to be last (terminating) instruction. 1457 1458 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(), 1459 e = prologueMBB.livein_end(); i != e; i++) { 1460 allocMBB->addLiveIn(*i); 1461 checkMBB->addLiveIn(*i); 1462 } 1463 1464 if (IsNested) 1465 allocMBB->addLiveIn(X86::R10); 1466 1467 MF.push_front(allocMBB); 1468 MF.push_front(checkMBB); 1469 1470 // Eventually StackSize will be calculated by a link-time pass; which will 1471 // also decide whether checking code needs to be injected into this particular 1472 // prologue. 1473 StackSize = MFI->getStackSize(); 1474 1475 // When the frame size is less than 256 we just compare the stack 1476 // boundary directly to the value of the stack pointer, per gcc. 1477 bool CompareStackPointer = StackSize < kSplitStackAvailable; 1478 1479 // Read the limit off the current stacklet off the stack_guard location. 1480 if (Is64Bit) { 1481 if (STI.isTargetLinux()) { 1482 TlsReg = X86::FS; 1483 TlsOffset = 0x70; 1484 } else if (STI.isTargetDarwin()) { 1485 TlsReg = X86::GS; 1486 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90. 1487 } else if (STI.isTargetFreeBSD()) { 1488 TlsReg = X86::FS; 1489 TlsOffset = 0x18; 1490 } else { 1491 report_fatal_error("Segmented stacks not supported on this platform."); 1492 } 1493 1494 if (CompareStackPointer) 1495 ScratchReg = X86::RSP; 1496 else 1497 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP) 1498 .addImm(1).addReg(0).addImm(-StackSize).addReg(0); 1499 1500 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg) 1501 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg); 1502 } else { 1503 if (STI.isTargetLinux()) { 1504 TlsReg = X86::GS; 1505 TlsOffset = 0x30; 1506 } else if (STI.isTargetDarwin()) { 1507 TlsReg = X86::GS; 1508 TlsOffset = 0x48 + 90*4; 1509 } else if (STI.isTargetWin32()) { 1510 TlsReg = X86::FS; 1511 TlsOffset = 0x14; // pvArbitrary, reserved for application use 1512 } else if (STI.isTargetFreeBSD()) { 1513 report_fatal_error("Segmented stacks not supported on FreeBSD i386."); 1514 } else { 1515 report_fatal_error("Segmented stacks not supported on this platform."); 1516 } 1517 1518 if (CompareStackPointer) 1519 ScratchReg = X86::ESP; 1520 else 1521 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP) 1522 .addImm(1).addReg(0).addImm(-StackSize).addReg(0); 1523 1524 if (STI.isTargetLinux() || STI.isTargetWin32()) { 1525 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg) 1526 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg); 1527 } else if (STI.isTargetDarwin()) { 1528 1529 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register 1530 unsigned ScratchReg2; 1531 bool SaveScratch2; 1532 if (CompareStackPointer) { 1533 // The primary scratch register is available for holding the TLS offset 1534 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true); 1535 SaveScratch2 = false; 1536 } else { 1537 // Need to use a second register to hold the TLS offset 1538 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false); 1539 1540 // Unfortunately, with fastcc the second scratch register may hold an arg 1541 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2); 1542 } 1543 1544 // If Scratch2 is live-in then it needs to be saved 1545 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) && 1546 "Scratch register is live-in and not saved"); 1547 1548 if (SaveScratch2) 1549 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r)) 1550 .addReg(ScratchReg2, RegState::Kill); 1551 1552 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2) 1553 .addImm(TlsOffset); 1554 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)) 1555 .addReg(ScratchReg) 1556 .addReg(ScratchReg2).addImm(1).addReg(0) 1557 .addImm(0) 1558 .addReg(TlsReg); 1559 1560 if (SaveScratch2) 1561 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2); 1562 } 1563 } 1564 1565 // This jump is taken if SP >= (Stacklet Limit + Stack Space required). 1566 // It jumps to normal execution of the function body. 1567 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB); 1568 1569 // On 32 bit we first push the arguments size and then the frame size. On 64 1570 // bit, we pass the stack frame size in r10 and the argument size in r11. 1571 if (Is64Bit) { 1572 // Functions with nested arguments use R10, so it needs to be saved across 1573 // the call to _morestack 1574 1575 if (IsNested) 1576 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10); 1577 1578 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10) 1579 .addImm(StackSize); 1580 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11) 1581 .addImm(X86FI->getArgumentStackSize()); 1582 MF.getRegInfo().setPhysRegUsed(X86::R10); 1583 MF.getRegInfo().setPhysRegUsed(X86::R11); 1584 } else { 1585 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32)) 1586 .addImm(X86FI->getArgumentStackSize()); 1587 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32)) 1588 .addImm(StackSize); 1589 } 1590 1591 // __morestack is in libgcc 1592 if (Is64Bit) 1593 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32)) 1594 .addExternalSymbol("__morestack"); 1595 else 1596 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32)) 1597 .addExternalSymbol("__morestack"); 1598 1599 if (IsNested) 1600 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10)); 1601 else 1602 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET)); 1603 1604 allocMBB->addSuccessor(&prologueMBB); 1605 1606 checkMBB->addSuccessor(allocMBB); 1607 checkMBB->addSuccessor(&prologueMBB); 1608 1609 #ifdef XDEBUG 1610 MF.verify(); 1611 #endif 1612 } 1613 1614 /// Erlang programs may need a special prologue to handle the stack size they 1615 /// might need at runtime. That is because Erlang/OTP does not implement a C 1616 /// stack but uses a custom implementation of hybrid stack/heap architecture. 1617 /// (for more information see Eric Stenman's Ph.D. thesis: 1618 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf) 1619 /// 1620 /// CheckStack: 1621 /// temp0 = sp - MaxStack 1622 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart 1623 /// OldStart: 1624 /// ... 1625 /// IncStack: 1626 /// call inc_stack # doubles the stack space 1627 /// temp0 = sp - MaxStack 1628 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart 1629 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const { 1630 const X86InstrInfo &TII = *TM.getInstrInfo(); 1631 MachineFrameInfo *MFI = MF.getFrameInfo(); 1632 const unsigned SlotSize = TM.getRegisterInfo()->getSlotSize(); 1633 const bool Is64Bit = STI.is64Bit(); 1634 DebugLoc DL; 1635 // HiPE-specific values 1636 const unsigned HipeLeafWords = 24; 1637 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5; 1638 const unsigned Guaranteed = HipeLeafWords * SlotSize; 1639 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ? 1640 MF.getFunction()->arg_size() - CCRegisteredArgs : 0; 1641 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize; 1642 1643 assert(STI.isTargetLinux() && 1644 "HiPE prologue is only supported on Linux operating systems."); 1645 1646 // Compute the largest caller's frame that is needed to fit the callees' 1647 // frames. This 'MaxStack' is computed from: 1648 // 1649 // a) the fixed frame size, which is the space needed for all spilled temps, 1650 // b) outgoing on-stack parameter areas, and 1651 // c) the minimum stack space this function needs to make available for the 1652 // functions it calls (a tunable ABI property). 1653 if (MFI->hasCalls()) { 1654 unsigned MoreStackForCalls = 0; 1655 1656 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end(); 1657 MBBI != MBBE; ++MBBI) 1658 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end(); 1659 MI != ME; ++MI) { 1660 if (!MI->isCall()) 1661 continue; 1662 1663 // Get callee operand. 1664 const MachineOperand &MO = MI->getOperand(0); 1665 1666 // Only take account of global function calls (no closures etc.). 1667 if (!MO.isGlobal()) 1668 continue; 1669 1670 const Function *F = dyn_cast<Function>(MO.getGlobal()); 1671 if (!F) 1672 continue; 1673 1674 // Do not update 'MaxStack' for primitive and built-in functions 1675 // (encoded with names either starting with "erlang."/"bif_" or not 1676 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an 1677 // "_", such as the BIF "suspend_0") as they are executed on another 1678 // stack. 1679 if (F->getName().find("erlang.") != StringRef::npos || 1680 F->getName().find("bif_") != StringRef::npos || 1681 F->getName().find_first_of("._") == StringRef::npos) 1682 continue; 1683 1684 unsigned CalleeStkArity = 1685 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0; 1686 if (HipeLeafWords - 1 > CalleeStkArity) 1687 MoreStackForCalls = std::max(MoreStackForCalls, 1688 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize); 1689 } 1690 MaxStack += MoreStackForCalls; 1691 } 1692 1693 // If the stack frame needed is larger than the guaranteed then runtime checks 1694 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue. 1695 if (MaxStack > Guaranteed) { 1696 MachineBasicBlock &prologueMBB = MF.front(); 1697 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock(); 1698 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock(); 1699 1700 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(), 1701 E = prologueMBB.livein_end(); I != E; I++) { 1702 stackCheckMBB->addLiveIn(*I); 1703 incStackMBB->addLiveIn(*I); 1704 } 1705 1706 MF.push_front(incStackMBB); 1707 MF.push_front(stackCheckMBB); 1708 1709 unsigned ScratchReg, SPReg, PReg, SPLimitOffset; 1710 unsigned LEAop, CMPop, CALLop; 1711 if (Is64Bit) { 1712 SPReg = X86::RSP; 1713 PReg = X86::RBP; 1714 LEAop = X86::LEA64r; 1715 CMPop = X86::CMP64rm; 1716 CALLop = X86::CALL64pcrel32; 1717 SPLimitOffset = 0x90; 1718 } else { 1719 SPReg = X86::ESP; 1720 PReg = X86::EBP; 1721 LEAop = X86::LEA32r; 1722 CMPop = X86::CMP32rm; 1723 CALLop = X86::CALLpcrel32; 1724 SPLimitOffset = 0x4c; 1725 } 1726 1727 ScratchReg = GetScratchRegister(Is64Bit, MF, true); 1728 assert(!MF.getRegInfo().isLiveIn(ScratchReg) && 1729 "HiPE prologue scratch register is live-in"); 1730 1731 // Create new MBB for StackCheck: 1732 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg), 1733 SPReg, false, -MaxStack); 1734 // SPLimitOffset is in a fixed heap location (pointed by BP). 1735 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop)) 1736 .addReg(ScratchReg), PReg, false, SPLimitOffset); 1737 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB); 1738 1739 // Create new MBB for IncStack: 1740 BuildMI(incStackMBB, DL, TII.get(CALLop)). 1741 addExternalSymbol("inc_stack_0"); 1742 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg), 1743 SPReg, false, -MaxStack); 1744 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop)) 1745 .addReg(ScratchReg), PReg, false, SPLimitOffset); 1746 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB); 1747 1748 stackCheckMBB->addSuccessor(&prologueMBB, 99); 1749 stackCheckMBB->addSuccessor(incStackMBB, 1); 1750 incStackMBB->addSuccessor(&prologueMBB, 99); 1751 incStackMBB->addSuccessor(incStackMBB, 1); 1752 } 1753 #ifdef XDEBUG 1754 MF.verify(); 1755 #endif 1756 } 1757 1758 void X86FrameLowering:: 1759 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1760 MachineBasicBlock::iterator I) const { 1761 const X86InstrInfo &TII = *TM.getInstrInfo(); 1762 const X86RegisterInfo &RegInfo = *TM.getRegisterInfo(); 1763 unsigned StackPtr = RegInfo.getStackRegister(); 1764 bool reseveCallFrame = hasReservedCallFrame(MF); 1765 int Opcode = I->getOpcode(); 1766 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode(); 1767 bool IsLP64 = STI.isTarget64BitLP64(); 1768 DebugLoc DL = I->getDebugLoc(); 1769 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0; 1770 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0; 1771 I = MBB.erase(I); 1772 1773 if (!reseveCallFrame) { 1774 // If the stack pointer can be changed after prologue, turn the 1775 // adjcallstackup instruction into a 'sub ESP, <amt>' and the 1776 // adjcallstackdown instruction into 'add ESP, <amt>' 1777 // TODO: consider using push / pop instead of sub + store / add 1778 if (Amount == 0) 1779 return; 1780 1781 // We need to keep the stack aligned properly. To do this, we round the 1782 // amount of space needed for the outgoing arguments up to the next 1783 // alignment boundary. 1784 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 1785 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign; 1786 1787 MachineInstr *New = 0; 1788 if (Opcode == TII.getCallFrameSetupOpcode()) { 1789 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)), 1790 StackPtr) 1791 .addReg(StackPtr) 1792 .addImm(Amount); 1793 } else { 1794 assert(Opcode == TII.getCallFrameDestroyOpcode()); 1795 1796 // Factor out the amount the callee already popped. 1797 Amount -= CalleeAmt; 1798 1799 if (Amount) { 1800 unsigned Opc = getADDriOpcode(IsLP64, Amount); 1801 New = BuildMI(MF, DL, TII.get(Opc), StackPtr) 1802 .addReg(StackPtr).addImm(Amount); 1803 } 1804 } 1805 1806 if (New) { 1807 // The EFLAGS implicit def is dead. 1808 New->getOperand(3).setIsDead(); 1809 1810 // Replace the pseudo instruction with a new instruction. 1811 MBB.insert(I, New); 1812 } 1813 1814 return; 1815 } 1816 1817 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) { 1818 // If we are performing frame pointer elimination and if the callee pops 1819 // something off the stack pointer, add it back. We do this until we have 1820 // more advanced stack pointer tracking ability. 1821 unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt); 1822 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr) 1823 .addReg(StackPtr).addImm(CalleeAmt); 1824 1825 // The EFLAGS implicit def is dead. 1826 New->getOperand(3).setIsDead(); 1827 1828 // We are not tracking the stack pointer adjustment by the callee, so make 1829 // sure we restore the stack pointer immediately after the call, there may 1830 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions. 1831 MachineBasicBlock::iterator B = MBB.begin(); 1832 while (I != B && !llvm::prior(I)->isCall()) 1833 --I; 1834 MBB.insert(I, New); 1835 } 1836 } 1837 1838