| /external/qemu/target-i386/ |
| ops_sse_header.h | 21 #define Reg MMXReg
24 #define Reg XMMReg
31 #define dh_ctype_Reg Reg *
38 DEF_HELPER_2(glue(psrlw, SUFFIX), void, Reg, Reg)
39 DEF_HELPER_2(glue(psraw, SUFFIX), void, Reg, Reg)
40 DEF_HELPER_2(glue(psllw, SUFFIX), void, Reg, Reg)
41 DEF_HELPER_2(glue(psrld, SUFFIX), void, Reg, Reg
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcMachineFunctionInfo.h | 38 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
44 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.h | 74 bool isAllocated(unsigned Reg) const {
75 return UsedRegs[Reg/32] & (1 << (Reg&31));
121 unsigned AllocateReg(unsigned Reg) {
122 if (isAllocated(Reg)) return 0;
123 MarkAllocated(Reg);
124 return Reg;
128 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
129 if (isAllocated(Reg)) return 0;
130 MarkAllocated(Reg);
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineRegisterInfo.cpp | 39 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
41 VRegInfo[Reg].first = RC;
45 MachineRegisterInfo::constrainRegClass(unsigned Reg,
48 const TargetRegisterClass *OldRC = getRegClass(Reg);
56 setRegClass(Reg, NewRC);
61 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
63 const TargetRegisterClass *OldRC = getRegClass(Reg);
71 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
85 setRegClass(Reg, NewRC);
99 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs())
[all...] |
| MachineInstrBundle.cpp | 133 unsigned Reg = MO.getReg();
134 if (!Reg)
136 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
137 if (LocalDefSet.count(Reg)) {
141 KilledDefSet.insert(Reg);
143 if (ExternUseSet.insert(Reg)) {
144 ExternUses.push_back(Reg);
146 UndefUseSet.insert(Reg);
150 KilledUseSet.insert(Reg);
156 unsigned Reg = MO.getReg()
[all...] |
| AggressiveAntiDepBreaker.cpp | 60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
61 unsigned Node = GroupNodeIndices[Reg];
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
75 Regs.push_back(Reg);
82 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
[all...] |
| CriticalAntiDepBreaker.cpp | 66 unsigned Reg = *AI;
67 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
68 KillIndices[Reg] = BBSize;
69 DefIndices[Reg] = ~0u;
81 unsigned Reg = *AI;
82 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
83 KillIndices[Reg] = BBSize;
84 DefIndices[Reg] = ~0u;
100 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg)
[all...] |
| DeadMachineInstructionElim.cpp | 69 unsigned Reg = MO.getReg();
70 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
72 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
75 if (!MRI->use_nodbg_empty(Reg))
127 unsigned Reg = MO.getReg();
128 if (!TargetRegisterInfo::isVirtualRegister(Reg))
131 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
155 unsigned Reg = MO.getReg();
156 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
[all...] |
| LiveVariables.cpp | 131 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
133 assert(MRI->getVRegDef(reg) && "Register use before def!");
137 VarInfo& VRInfo = getVarInfo(reg);
168 if (MBB == MRI->getVRegDef(reg)->getParent()) return;
179 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
183 VarInfo &VRInfo = getVarInfo(Reg);
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
219 if (TRI->isSubRegister(Reg, DefReg))
[all...] |
| AllocationOrder.h | 52 unsigned Reg = Order[Pos++];
53 if (!isHint(Reg))
54 return Reg;
|
| RegisterScavenging.cpp | 17 #define DEBUG_TYPE "reg-scavenging"
33 void RegScavenger::setUsed(unsigned Reg) {
34 RegsAvailable.reset(Reg);
36 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
40 bool RegScavenger::isAliasUsed(unsigned Reg) const {
41 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
42 if (isUsed(*AI, *AI == Reg))
105 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
106 BV.set(Reg);
107 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs
[all...] |
| /external/llvm/lib/MC/ |
| MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
20 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const {
31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
|
| /external/llvm/include/llvm/CodeGen/ |
| RegisterPressure.h | 31 /// Map of max reg pressure indexed by pressure set ID, not class ID.
42 /// \param Reg is either a virtual register number or register unit number.
43 void increase(unsigned Reg, const TargetRegisterInfo *TRI,
49 /// \param Reg is either a virtual register number or register unit number.
50 void decrease(unsigned Reg, const TargetRegisterInfo *TRI,
134 bool contains(unsigned Reg) {
135 if (TargetRegisterInfo::isVirtualRegister(Reg))
136 return VirtRegs.count(Reg);
137 return PhysRegs.count(Reg);
140 bool insert(unsigned Reg) {
[all...] |
| LiveVariables.h | 108 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
109 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
112 unsigned Reg,
152 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
155 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
160 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
161 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
167 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
172 MachineInstr *FindLastPartialDef(unsigned Reg,
[all...] |
| RegisterScavenging.h | 127 void setUsed(unsigned Reg);
130 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
136 bool isUsed(unsigned Reg, bool CheckReserved = true) const {
137 return !RegsAvailable.test(Reg) || (CheckReserved && isReserved(Reg));
140 /// isAliasUsed - Is Reg or an alias currently in use?
141 bool isAliasUsed(unsigned Reg) const;
152 /// Add Reg and all its sub-registers to BV.
153 void addRegWithSubRegs(BitVector &BV, unsigned Reg);
[all...] |
| FunctionLoweringInfo.h | 148 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
149 if (!LiveOutRegInfo.inBounds(Reg))
152 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
164 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
167 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
173 LiveOutRegInfo.grow(Reg);
174 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
192 unsigned Reg = It->second;
193 LiveOutRegInfo.grow(Reg);
194 LiveOutRegInfo[Reg].IsValid = false
[all...] |
| MachineRegisterInfo.h | 77 return MO->Contents.Reg.Next;
190 /// Reg are Debug instructions.
269 MachineInstr *getVRegDef(unsigned Reg) const;
274 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
280 void clearKillFlags(unsigned Reg) const;
297 const TargetRegisterClass *getRegClass(unsigned Reg) const {
298 return VRegInfo[Reg].first;
303 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
312 const TargetRegisterClass *constrainRegClass(unsigned Reg,
316 /// recomputeRegClass - Try to find a legal super-class of Reg's registe
[all...] |
| CallingConvLower.h | 191 bool isAllocated(unsigned Reg) const {
192 return UsedRegs[Reg/32] & (1 << (Reg&31));
243 unsigned AllocateReg(unsigned Reg) {
244 if (isAllocated(Reg)) return 0;
245 MarkAllocated(Reg);
246 return Reg;
250 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
251 if (isAllocated(Reg)) return 0;
252 MarkAllocated(Reg);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsMachineFunction.h | 69 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
92 int getEhDataRegFI(unsigned Reg) const { return EhDataRegFI[Reg]; }
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 76 bool contains(unsigned Reg) const {
77 return MC->contains(Reg);
160 /// For all Reg in SuperRC:
161 /// this->contains(Reg:Idx)
225 // Pointer to array of lane masks, one per sub-reg index.
252 /// returns true if Reg is in the range used for stack slots.
258 static bool isStackSlot(unsigned Reg) {
259 return int(Reg) >= (1 << 30);
264 static int stackSlot2Index(unsigned Reg) {
265 assert(isStackSlot(Reg) && "Not a stack slot")
[all...] |
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 65 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
89 unsigned Reg = MI->getOperand(1).getReg();
90 if (TargetRegisterInfo::isPhysicalRegister(Reg))
94 MachineInstr *DefMI = MRI->getVRegDef(Reg);
99 Reg = DefMI->getOperand(1).getReg();
100 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
101 DefMI = MRI->getVRegDef(Reg);
105 Reg = DefMI->getOperand(2).getReg();
106 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
107 DefMI = MRI->getVRegDef(Reg);
[all...] |
| ARMCallingConv.h | 34 if (unsigned Reg = State.AllocateReg(RegList, 4))
35 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
49 if (unsigned Reg = State.AllocateReg(RegList, 4))
50 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
78 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
79 if (Reg == 0) {
93 if (HiRegList[i] == Reg)
100 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
123 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
124 if (Reg == 0
[all...] |
| ARMBaseRegisterInfo.h | 38 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
40 switch (Reg) {
53 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
55 switch (Reg) {
64 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
66 switch (Reg) {
120 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
148 bool isLowRegister(unsigned Reg) const;
|
| /external/llvm/include/llvm/MC/ |
| MCInstBuilder.h | 32 MCInstBuilder &addReg(unsigned Reg) {
33 Inst.addOperand(MCOperand::CreateReg(Reg));
|
| MCRegisterInfo.h | 71 bool contains(unsigned Reg) const {
72 unsigned InByte = Reg % 8;
73 unsigned Byte = Reg / 8;
113 uint32_t Name; // Printable name for the reg (for debugging)
143 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
323 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
326 /// Reg so its sub-register of index SubIdx is Reg.
327 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
423 /// MCSubRegIterator enumerates all sub-registers of Reg
[all...] |
