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      1 //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the base ARM implementation of TargetRegisterInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef ARMBASEREGISTERINFO_H
     15 #define ARMBASEREGISTERINFO_H
     16 
     17 #include "ARM.h"
     18 #include "llvm/Target/TargetRegisterInfo.h"
     19 
     20 #define GET_REGINFO_HEADER
     21 #include "ARMGenRegisterInfo.inc"
     22 
     23 namespace llvm {
     24   class ARMSubtarget;
     25   class ARMBaseInstrInfo;
     26   class Type;
     27 
     28 /// Register allocation hints.
     29 namespace ARMRI {
     30   enum {
     31     RegPairOdd  = 1,
     32     RegPairEven = 2
     33   };
     34 }
     35 
     36 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
     37 /// or a stack/pc register that we should push/pop.
     38 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
     39   using namespace ARM;
     40   switch (Reg) {
     41     case R0:  case R1:  case R2:  case R3:
     42     case R4:  case R5:  case R6:  case R7:
     43     case LR:  case SP:  case PC:
     44       return true;
     45     case R8:  case R9:  case R10: case R11:
     46       // For iOS we want r7 and lr to be next to each other.
     47       return !isIOS;
     48     default:
     49       return false;
     50   }
     51 }
     52 
     53 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
     54   using namespace ARM;
     55   switch (Reg) {
     56     case R8: case R9: case R10: case R11:
     57       // iOS has this second area.
     58       return isIOS;
     59     default:
     60       return false;
     61   }
     62 }
     63 
     64 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
     65   using namespace ARM;
     66   switch (Reg) {
     67     case D15: case D14: case D13: case D12:
     68     case D11: case D10: case D9:  case D8:
     69       return true;
     70     default:
     71       return false;
     72   }
     73 }
     74 
     75 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
     76 protected:
     77   const ARMBaseInstrInfo &TII;
     78   const ARMSubtarget &STI;
     79 
     80   /// FramePtr - ARM physical register used as frame ptr.
     81   unsigned FramePtr;
     82 
     83   /// BasePtr - ARM physical register used as a base ptr in complex stack
     84   /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
     85   /// variable size stack objects.
     86   unsigned BasePtr;
     87 
     88   // Can be only subclassed.
     89   explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
     90                                const ARMSubtarget &STI);
     91 
     92   // Return the opcode that implements 'Op', or 0 if no opcode
     93   unsigned getOpcode(int Op) const;
     94 
     95 public:
     96   /// Code Generation virtual methods...
     97   const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
     98   const uint32_t *getCallPreservedMask(CallingConv::ID) const;
     99   const uint32_t *getNoPreservedMask() const;
    100 
    101   BitVector getReservedRegs(const MachineFunction &MF) const;
    102 
    103   const TargetRegisterClass*
    104   getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
    105   const TargetRegisterClass*
    106   getCrossCopyRegClass(const TargetRegisterClass *RC) const;
    107 
    108   const TargetRegisterClass*
    109   getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
    110 
    111   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
    112                                MachineFunction &MF) const;
    113 
    114   void getRegAllocationHints(unsigned VirtReg,
    115                              ArrayRef<MCPhysReg> Order,
    116                              SmallVectorImpl<MCPhysReg> &Hints,
    117                              const MachineFunction &MF,
    118                              const VirtRegMap *VRM) const;
    119 
    120   void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
    121                           MachineFunction &MF) const;
    122 
    123   virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
    124 
    125   bool hasBasePointer(const MachineFunction &MF) const;
    126 
    127   bool canRealignStack(const MachineFunction &MF) const;
    128   bool needsStackRealignment(const MachineFunction &MF) const;
    129   int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
    130   bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
    131   void materializeFrameBaseRegister(MachineBasicBlock *MBB,
    132                                     unsigned BaseReg, int FrameIdx,
    133                                     int64_t Offset) const;
    134   void resolveFrameIndex(MachineBasicBlock::iterator I,
    135                          unsigned BaseReg, int64_t Offset) const;
    136   bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
    137 
    138   bool cannotEliminateFrame(const MachineFunction &MF) const;
    139 
    140   // Debug information queries.
    141   unsigned getFrameRegister(const MachineFunction &MF) const;
    142   unsigned getBaseRegister() const { return BasePtr; }
    143 
    144   // Exception handling queries.
    145   unsigned getEHExceptionRegister() const;
    146   unsigned getEHHandlerRegister() const;
    147 
    148   bool isLowRegister(unsigned Reg) const;
    149 
    150 
    151   /// emitLoadConstPool - Emits a load from constpool to materialize the
    152   /// specified immediate.
    153   virtual void emitLoadConstPool(MachineBasicBlock &MBB,
    154                                  MachineBasicBlock::iterator &MBBI,
    155                                  DebugLoc dl,
    156                                  unsigned DestReg, unsigned SubIdx,
    157                                  int Val,
    158                                  ARMCC::CondCodes Pred = ARMCC::AL,
    159                                  unsigned PredReg = 0,
    160                                  unsigned MIFlags = MachineInstr::NoFlags)const;
    161 
    162   /// Code Generation virtual methods...
    163   virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
    164 
    165   virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
    166 
    167   virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
    168 
    169   virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
    170 
    171   virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
    172                                    int SPAdj, unsigned FIOperandNum,
    173                                    RegScavenger *RS = NULL) const;
    174 };
    175 
    176 } // end namespace llvm
    177 
    178 #endif
    179