| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 335 virtual EVT getSetCCResultType(EVT VT) const;
407 EVT VT) const;
454 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast = 0) const;
460 virtual bool isFMAFasterThanMulAndAdd(EVT VT) const;
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| /external/llvm/utils/TableGen/ |
| DAGISelMatcher.cpp | 210 OS.indent(indent) << "EmitInteger " << Val << " VT=" << VT << '\n';
215 OS.indent(indent) << "EmitStringInteger " << Val << " VT=" << VT << '\n';
224 OS << " VT=" << VT << '\n';
293 return HashString(Val) ^ VT;
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| CallingConvEmitter.cpp | 88 Record *VT = VTs->getElementAsRecord(i);
90 O << "LocVT == " << getEnumName(getValueType(VT));
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| CodeGenDAGPatterns.cpp | 32 static inline bool isInteger(MVT::SimpleValueType VT) {
33 return EVT(VT).isInteger();
35 static inline bool isFloatingPoint(MVT::SimpleValueType VT) {
36 return EVT(VT).isFloatingPoint();
38 static inline bool isVector(MVT::SimpleValueType VT) {
39 return EVT(VT).isVector();
41 static inline bool isScalar(MVT::SimpleValueType VT) {
42 return !EVT(VT).isVector();
45 EEVT::TypeSet::TypeSet(MVT::SimpleValueType VT, TreePattern &TP) {
46 if (VT == MVT::iAny
[all...] |
| CodeGenDAGPatterns.h | 61 TypeSet(MVT::SimpleValueType VT, TreePattern &TP);
127 /// EnforceSmallerThan - 'this' must be a smaller VT than Other. Update
132 /// whose element is VT.
133 bool EnforceVectorEltTypeIs(EEVT::TypeSet &VT, TreePattern &TP);
136 /// be a vector type VT.
137 bool EnforceVectorSubVectorTypeIs(EEVT::TypeSet &VT, TreePattern &TP);
169 MVT::SimpleValueType VT;
452 /// UpdateNodeType - Set the node type of N to VT if VT contains
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 28 static RTLIB::Libcall GetFPLibCall(EVT VT,
35 VT == MVT::f32 ? Call_F32 :
36 VT == MVT::f64 ? Call_F64 :
37 VT == MVT::f80 ? Call_F80 :
38 VT == MVT::f128 ? Call_F128 :
39 VT == MVT::ppcf128 ? Call_PPCF128 :
498 EVT VT = N->getValueType(0);
499 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
523 return BitConvertToInteger(DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL));
549 EVT VT = N->getValueType(0)
[all...] |
| ScheduleDAGRRList.cpp | 280 MVT VT = RegDefPos.GetValue();
284 if (VT == MVT::Untyped) {
313 RegClass = TLI->getRepRegClassFor(VT)->getID();
314 Cost = TLI->getRepRegClassCostFor(VT);
[all...] |
| InstrEmitter.cpp | 102 MVT VT = Node->getSimpleValueType(ResNo);
105 if (TLI->isTypeLegal(VT))
106 UseRC = TLI->getRegClassFor(VT);
127 MVT VT = Node->getSimpleValueType(Op.getResNo());
128 if (VT == MVT::Other || VT == MVT::Glue)
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
163 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
166 DstRC = TLI->getRegClassFor(VT);
425 MVT VT, DebugLoc DL)
[all...] |
| SelectionDAGISel.cpp | [all...] |
| ScheduleDAGFast.cpp | 223 EVT VT = N->getValueType(i);
224 if (VT == MVT::Glue)
226 else if (VT == MVT::Other)
231 EVT VT = Op.getNode()->getValueType(Op.getResNo());
232 if (VT == MVT::Glue)
574 EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
576 TRI->getMinimalPhysRegClass(Reg, VT);
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| FunctionLoweringInfo.cpp | 172 EVT VT = ValueVTs[vti];
173 unsigned NumRegisters = TLI.getNumRegisters(Fn->getContext(), VT);
210 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
211 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
272 "PHIs with non-vector integer types should have a single VT.");
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| LegalizeTypes.cpp | [all...] |
| LegalizeTypes.h | 63 /// enum from TargetLowering. This can be queried with "getTypeAction(VT)".
67 TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const {
68 return TLI.getTypeAction(*DAG.getContext(), VT);
72 bool isTypeLegal(EVT VT) const {
73 return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
151 bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult);
152 bool CustomWidenLowerNode(SDNode *N, EVT VT);
167 SDValue PromoteTargetBoolean(SDValue Bool, EVT VT);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 405 EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
406 if (!VT.isVector())
408 return VT.changeVectorElementTypeToInteger();
[all...] |
| MipsSEISelLowering.cpp | 78 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
79 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
|
| MipsSEISelDAGToDAG.cpp | 212 EVT VT = LHS.getValueType();
214 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops, 2);
215 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
217 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 600 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
607 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
644 EVT VT;
649 VT = LD->getMemoryVT();
652 VT = ST->getMemoryVT();
661 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
664 int ShiftAmount = VT.getSizeInBits() / 16
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 169 EVT getSetCCResultType(EVT VT) const;
239 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 101 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
|
| /external/llvm/lib/Target/R600/ |
| AMDILPeepholeOptimizer.cpp | 130 size_t getTypeSize(VectorType * const VT, bool dereferencePtr = false);
474 const VectorType *VT = dyn_cast<VectorType>(aType);
475 numEle = VT->getNumElements();
677 const VectorType *VT = dyn_cast<VectorType>(aType);
678 numEle = VT->getNumElements();
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 782 EVT VT = N.getValueType();
785 SDValue NewMask = DAG.getConstant(0xff, VT);
786 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
787 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
789 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
830 EVT VT = N.getValueType();
832 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
833 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
834 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
[all...] |
| /external/clang/lib/Analysis/ |
| LiveVariables.cpp | 235 while (const ArrayType *VT = dyn_cast<ArrayType>(ty)) {
236 if (const VariableArrayType *VAT = dyn_cast<VariableArrayType>(VT))
240 ty = VT->getElementType().getTypePtr();
|
| /external/clang/lib/CodeGen/ |
| CodeGenTypes.cpp | 459 const VectorType *VT = cast<VectorType>(Ty);
460 ResultType = llvm::VectorType::get(ConvertType(VT->getElementType()),
461 VT->getNumElements());
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 195 EVT MBlazeTargetLowering::getSetCCResultType(EVT VT) const {
[all...] |
