| /external/v8/src/arm/ |
| ic-arm.cc | 99 __ ldr(elements, FieldMemOperand(receiver, JSObject::kPropertiesOffset));
100 __ ldr(t1, FieldMemOperand(elements, HeapObject::kMapOffset));
148 __ ldr(scratch1, FieldMemOperand(scratch2, kDetailsOffset));
153 __ ldr(result,
200 __ ldr(scratch1, FieldMemOperand(scratch2, kDetailsOffset));
274 __ ldr(map, FieldMemOperand(receiver, HeapObject::kMapOffset));
324 __ ldr(elements, FieldMemOperand(receiver, JSObject::kElementsOffset));
327 __ ldr(scratch1, FieldMemOperand(elements, HeapObject::kMapOffset));
335 __ ldr(scratch1, FieldMemOperand(elements, FixedArray::kLengthOffset));
342 __ ldr(scratch2
[all...] |
| regexp-macro-assembler-arm.cc | 165 __ ldr(r0, register_location(reg));
200 __ ldr(r0, MemOperand(frame_pointer(), kAtStart));
205 __ ldr(r1, MemOperand(frame_pointer(), kInputStart));
215 __ ldr(r0, MemOperand(frame_pointer(), kAtStart));
219 __ ldr(r1, MemOperand(frame_pointer(), kInputStart));
281 __ ldr(r0, MemOperand(backtrack_stackpointer(), 0));
293 __ ldr(r0, register_location(start_reg)); // Index of start of capture
294 __ ldr(r1, register_location(start_reg + 1)); // Index of end of capture
399 __ ldr(r0, register_location(start_reg));
400 __ ldr(r1, register_location(start_reg + 1))
[all...] |
| codegen-arm.cc | 114 __ ldr(r4, FieldMemOperand(r2, JSObject::kElementsOffset));
119 __ ldr(r5, FieldMemOperand(r4, FixedArray::kLengthOffset));
189 __ ldr(r9, MemOperand(r3, 4, PostIndex));
248 __ ldr(r4, FieldMemOperand(r2, JSObject::kElementsOffset));
254 __ ldr(r5, FieldMemOperand(r4, FixedArray::kLengthOffset));
291 __ ldr(r1, MemOperand(r4, 8, PostIndex));
300 __ ldr(r0, MemOperand(r4, 12, NegOffset));
354 __ ldr(result, FieldMemOperand(string, HeapObject::kMapOffset));
369 __ ldr(result, FieldMemOperand(string, SlicedString::kOffsetOffset));
370 __ ldr(string, FieldMemOperand(string, SlicedString::kParentOffset))
[all...] |
| /bionic/libc/arch-arm/bionic/ |
| memcmp.S | 151 ldr ip, [r1]
157 ldr r0, [r4], #4
158 ldr lr, [r1, #4]!
190 3: ldr r0, [r4], #4
191 ldr ip, [r1], #4
251 ldr lr, [r1], #4
256 ldr lr, [r1], #4
257 ldr r0, [r4], #4
306 ldr r7, [r1], #4
310 ldr r7, [r1], #
[all...] |
| memcmp16.S | 109 ldr ip, [r1]
116 ldr r0, [r3], #4
117 ldr lr, [r1, #4]!
149 3: ldr r0, [r3], #4
150 ldr ip, [r1], #4
192 ldr lr, [r1], #4
199 ldr lr, [r1], #4
200 ldr r0, [r3], #4
|
| strcmp.a15.S | 123 use LDR and a shift queue. Order of loads and comparisons matters,
237 ldr r2, [r0], #4
282 ldr r2, [r0], #4
283 ldr r4, [r1], #4
296 ldr r5, [r1], #4
322 ldr r5, [r1], #4
327 ldr r3, [r0], #4
335 ldr r5, [r1], #4
417 /* Use LDR whenever possible. */
436 ldr ip, [r0], #
[all...] |
| /external/libvpx/libvpx/vp8/common/arm/armv6/ |
| vp8_variance_halfpixvar16x16_hv_armv6.asm | 33 ldr r10, c80808080
40 ldr r4, [r0, #0] ; load source pixels a, row N
41 ldr r6, [r0, #1] ; load source pixels b, row N
42 ldr r5, [r9, #0] ; load source pixels c, row N+1
43 ldr r7, [r9, #1] ; load source pixels d, row N+1
56 ldr r5, [r2, #0] ; load 4 ref pixels
80 ldr r4, [r0, #4] ; load source pixels a, row N
81 ldr r6, [r0, #5] ; load source pixels b, row N
82 ldr r5, [r9, #4] ; load source pixels c, row N+1
86 ldr r7, [r9, #5] ; load source pixels d, row N+
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| logical_shifted_reg.s | 9 ldr w1, [x0, #:lo12:var1_32]
11 ldr w2, [x0, #:lo12:var2_32]
77 ldr x0, [x0, #:lo12:var1_64]
79 ldr x1, [x1, #:lo12:var2_64]
146 ldr x0, [x0, #:lo12:var1_64]
148 ldr x1, [x1, #:lo12:var2_64]
155 ldr x0, [sp, #8] // 8-byte Folded Reload
156 ldr x1, [sp] // 8-byte Folded Reload
161 ldr x0, [sp, #8] // 8-byte Folded Reload
162 ldr x1, [sp] // 8-byte Folded Reloa
[all...] |
| /frameworks/av/media/libstagefright/codecs/aacenc/src/asm/ARMV5E/ |
| Radix4FFT_v5.s | 59 ldr r8, [r12], #4 @ cosxsinx = csptr[0]@
83 ldr r8, [r12], #4 @ cosxsinx = csptr[1]@
95 ldr r8, [r12], #4 @ cosxsinx = csptr[1]@
115 ldr r2, [sp, #24]
116 ldr r3, [sp, #28]
142 ldr r11, [sp, #20]
147 ldr r10, [sp, #16]
148 ldr r3, [sp, #12]
149 ldr r2, [sp, #8]
157 ldr r0, [sp
[all...] |
| PrePostMDCT_v5.s | 37 ldr r8, [r2], #4
38 ldr r9, [r2], #4
52 ldr r8, [r2], #4
53 ldr r9, [r2], #4
91 ldr r8, [r2], #4
92 ldr r9, [r2], #4
106 ldr r8, [r2], #4 @
107 ldr r9, [r2], #4
|
| /dalvik/vm/compiler/template/armv5te/ |
| TEMPLATE_CMPL_DOUBLE.S | 19 ldr ip, .L__aeabi_cdcmple @ PIC way of "bl __aeabi_cdcmple"
33 ldr ip, .L__aeabi_cdcmple @ r0<- Z set if eq, C clear if <
|
| TEMPLATE_MEM_OP_DECODE.S | 11 ldr r2, .LdvmSelfVerificationMemOpDecode @ defined in footer.S
|
| /dalvik/vm/compiler/template/armv5te-vfp/ |
| TEMPLATE_MEM_OP_DECODE.S | 12 ldr r2, .LdvmSelfVerificationMemOpDecode @ defined in footer.S
|
| /dalvik/vm/mterp/armv5te/ |
| OP_ARRAY_LENGTH.S | 12 ldr r3, [r0, #offArrayObject_length] @ r3<- array length
|
| OP_GOTO_16.S | 15 ldr r0, [rSELF, #offThread_pJitProfTable]
|
| OP_MOVE_EXCEPTION.S | 4 ldr r3, [rSELF, #offThread_exception] @ r3<- dvmGetException bypass
|
| alt_stub.S | 11 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
|
| /dalvik/vm/mterp/armv6t2/ |
| OP_ARRAY_LENGTH.S | 11 ldr r3, [r0, #offArrayObject_length] @ r3<- array length
|
| /dalvik/vm/mterp/out/ |
| InterpAsm-armv7-a-neon.S | 83 #define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc]
85 #define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_curFrame]
186 #define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2]
301 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE
306 ldr r0, [rSELF, #offThread_pJitProfTable]
314 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state
316 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state
335 ldr r0, strBadEntryPoint
362 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP
538 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.
[all...] |
| InterpAsm-armv7-a.S | 83 #define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc]
85 #define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_curFrame]
186 #define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2]
301 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE
306 ldr r0, [rSELF, #offThread_pJitProfTable]
314 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state
316 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state
335 ldr r0, strBadEntryPoint
362 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP
538 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.
[all...] |
| InterpAsm-armv5te-vfp.S | 83 #define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc]
85 #define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_curFrame]
186 #define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2]
287 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE
292 ldr r0, [rSELF, #offThread_pJitProfTable]
300 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state
302 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state
321 ldr r0, strBadEntryPoint
348 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP
526 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.
[all...] |
| InterpAsm-armv5te.S | 83 #define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc]
85 #define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_curFrame]
186 #define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2]
287 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE
292 ldr r0, [rSELF, #offThread_pJitProfTable]
300 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state
302 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state
321 ldr r0, strBadEntryPoint
348 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP
526 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.
[all...] |
| /external/openssl/crypto/bn/asm/ |
| armv4-gf2m.S | 56 ldr r5,[sp,r8] @ tab[b & 0x7]
58 ldr r7,[sp,r9] @ tab[b >> 3 & 0x7]
60 ldr r6,[sp,r8] @ tab[b >> 6 & 0x7]
63 ldr r7,[sp,r9] @ tab[b >> 9 & 0x7]
68 ldr r6,[sp,r8] @ tab[b >> 12 & 0x7]
73 ldr r7,[sp,r9] @ tab[b >> 15 & 0x7]
78 ldr r6,[sp,r8] @ tab[b >> 18 & 0x7]
83 ldr r7,[sp,r9] @ tab[b >> 21 & 0x7]
88 ldr r6,[sp,r8] @ tab[b >> 24 & 0x7]
93 ldr r7,[sp,r9] @ tab[b >> 27 & 0x7
[all...] |
| armv4-gf2m.pl | 100 ldr $lo,[sp,$i0] @ tab[b & 0x7]
102 ldr $t1,[sp,$i1] @ tab[b >> 3 & 0x7]
104 ldr $t0,[sp,$i0] @ tab[b >> 6 & 0x7]
107 ldr $t1,[sp,$i1] @ tab[b >> 9 & 0x7]
112 ldr $t0,[sp,$i0] @ tab[b >> 12 & 0x7]
117 ldr $t1,[sp,$i1] @ tab[b >> 15 & 0x7]
122 ldr $t0,[sp,$i0] @ tab[b >> 18 & 0x7]
127 ldr $t1,[sp,$i1] @ tab[b >> 21 & 0x7]
132 ldr $t0,[sp,$i0] @ tab[b >> 24 & 0x7]
137 ldr $t1,[sp,$i1] @ tab[b >> 27 & 0x7
[all...] |
| /bionic/libc/arch-arm/cortex-a9/bionic/ |
| strcmp.S | 96 use LDR and a shift queue. Order of loads and comparisons matters,
205 ldr r2, [r0], #4
250 ldr r2, [r0], #4
251 ldr r4, [r1], #4
264 ldr r5, [r1], #4
288 ldr r5, [r1], #4
293 ldr r3, [r0], #4
301 ldr r5, [r1], #4
386 ldr w1, [wp1], #4
387 ldr w2, [wp2], #
[all...] |
