/external/qemu/ |
cache-utils.c | 47 unsigned cacheline; local 50 len = sizeof(cacheline); 51 if (sysctl(name, 2, &cacheline, &len, NULL, 0)) { 54 qemu_cache_conf.dcache_bsize = cacheline; 55 qemu_cache_conf.icache_bsize = cacheline; 71 unsigned cacheline; local 73 if (sysctlbyname ("machdep.cacheline_size", &cacheline, &len, NULL, 0)) { 79 qemu_cache_conf.dcache_bsize = cacheline; 80 qemu_cache_conf.icache_bsize = cacheline;
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/external/kernel-headers/original/asm-x86/ |
cache.h | 11 /* vSMP Internode cacheline shift */
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segment_32.h | 12 * 4 - unused <==== new cacheline 26 * 12 - kernel code segment <==== new cacheline
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/external/kernel-headers/original/linux/ |
cache.h | 47 * These could be inter-node cacheline sizes/L3 cacheline
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blkdev.h | 126 * try to put the fields that are referenced together in the same cacheline 319 * Together with queue_head for cacheline sharing
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mmzone.h | 258 * give them a chance of being in the same cacheline. 283 * Right now a zonelist takes up less than a cacheline. We never
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skbuff.h | 991 * perhaps setting it to a cacheline in size (since that will maintain 992 * cacheline alignment of the DMA). It must be a power of 2. [all...] |
/external/oprofile/events/arm/armv6/ |
events.h | 25 "data cache writeback, 1 event for every half cacheline"},
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events | 14 event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
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/external/oprofile/events/arm/xscale1/ |
events | 15 event:0x0c counters:1,2 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
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/external/oprofile/events/arm/xscale2/ |
events | 15 event:0x0c counters:1,2,3,4 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
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/external/stressapptest/ |
stressapptest.1 | 85 Number of times to increment the cacheline's member.
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/external/stressapptest/src/ |
os.h | 113 // Flushes cacheline. Used to distinguish read or write errors. 115 // Takes a pointer, and flushed the cacheline containing that pointer.
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worker.h | 362 // Report a mistagged cacheline. 648 cc_cacheline_data *cc_cacheline_data_; // Datstructure for each cacheline. 653 // of the cacheline datastructure.
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sat.cc | 1024 "cacheline's member\n" [all...] |
/external/valgrind/main/helgrind/ |
libhb_core.c | 87 # define CHECK_ZSM 1 /* do sanity-check CacheLine stuff */ 91 # define CHECK_ZSM 0 /* don't sanity-check CacheLine stuff */ 422 /* ------ CacheLine ------ */ 433 CacheLine; 473 CacheLine-sized chunks of SecMaps are copied into a Cache, being 529 /* Each tag is the address of the associated CacheLine, rounded down 530 to a CacheLine address boundary. A CacheLine size must be a power 538 CacheLine lyns0[N_WAY_NENT]; 545 a CacheLine. * [all...] |
/external/kernel-headers/original/asm-generic/bitops/ |
atomic.h | 15 * Since "a" is usually an address, use one spinlock per cacheline.
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/bionic/libc/arch-arm/bionic/ |
memcpy.a15.S | 106 than loads that cross cacheline boundary. 122 /* TODO: Align to cacheline (useful for PLD optimization). */
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/external/kernel-headers/original/linux/netfilter_ipv4/ |
ip_conntrack.h | 127 /* Traversed often, so hopefully in different cacheline to top */
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/external/llvm/lib/Target/R600/ |
AMDGPUInstrInfo.cpp | 195 // TODO: Make the loads schedule near if it fits in a cacheline
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/prebuilts/gcc/darwin-x86/host/i686-apple-darwin-4.2.1/include/gcc/darwin/4.2/ |
ppc_intrinsics.h | 312 * cacheline is 316 * of the cacheline to be operated on. 318 * Effective Address of cacheline to be manipulated =
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/external/webp/src/dec/ |
vp8i.h | 93 // With this layout, BPS (=Bytes Per Scan-line) is one cacheline size.
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/prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/asm/ |
unistd_64.h | 14 /* at least 8 syscall per cacheline */
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/prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/asm/ |
unistd_64.h | 14 /* at least 8 syscall per cacheline */
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/prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/asm/ |
unistd_64.h | 14 /* at least 8 syscall per cacheline */
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