1 // events from file arm/armv6/events 2 {0x00, CTR(0) | CTR(1), 0, "IFU_IFETCH_MISS", 3 "number of instruction fetch misses"}, 4 {0x01, CTR(0) | CTR(1), 0, "CYCLES_IFU_MEM_STALL", 5 "cycles instruction fetch pipe is stalled"}, 6 {0x02, CTR(0) | CTR(1), 0, "CYCLES_DATA_STALL", 7 "cycles stall occurs for due to data dependency"}, 8 {0x03, CTR(0) | CTR(1), 0, "ITLB_MISS", 9 "number of Instruction MicroTLB misses"}, 10 {0x04, CTR(0) | CTR(1), 0, "DTLB_MISS", 11 "number of Data MicroTLB misses"}, 12 {0x05, CTR(0) | CTR(1), 0, "BR_INST_EXECUTED", 13 "branch instruction executed w/ or w/o program flow change"}, 14 {0x06, CTR(0) | CTR(1), 0, "BR_INST_MISS_PRED", 15 "branch mispredicted"}, 16 {0x07, CTR(0) | CTR(1), 0, "INSN_EXECUTED", 17 "instructions executed"}, 18 {0x09, CTR(0) | CTR(1), 0, "DCACHE_ACCESS", 19 "data cache access, cacheable locations"}, 20 {0x0a, CTR(0) | CTR(1), 0, "DCACHE_ACCESS_ALL", 21 "data cache access, all locations"}, 22 {0x0b, CTR(0) | CTR(1), 0, "DCACHE_MISS", 23 "data cache miss"}, 24 {0x0c, CTR(0) | CTR(1), 0, "DCACHE_WB", 25 "data cache writeback, 1 event for every half cacheline"}, 26 {0x0d, CTR(0) | CTR(1), 0, "PC_CHANGE", 27 "number of times the program counter was changed without a mode switch"}, 28 {0x0f, CTR(0) | CTR(1), 0, "TLB_MISS", 29 "Main TLB miss"}, 30 {0x10, CTR(0) | CTR(1), 0, "EXP_EXTERNAL", 31 "Explict external data access"}, 32 {0x11, CTR(0) | CTR(1), 0, "LSU_STALL", 33 "cycles stalled because Load Store request queque is full"}, 34 {0x12, CTR(0) | CTR(1), 0, "WRITE_DRAIN", 35 "Times write buffer was drained"}, 36 {0x20, CTR(0) | CTR(1), 0, "ETMEXTOUT0", 37 "nuber of cycles ETMEXTOUT[0] signal was asserted"}, 38 {0x21, CTR(0) | CTR(1), 0, "ETMEXTOUT1", 39 "nuber of cycles ETMEXTOUT[1] signal was asserted"}, 40 {0x22, CTR(0) | CTR(1), 0, "ETMEXTOUT_BOTH", 41 "nuber of cycles both ETMEXTOUT [0] and [1] were asserted * 2"}, 42 {0xff, CTR(0) | CTR(1) | CTR(2), 0, "CPU_CYCLES", 43 "clock cycles counter"}, 44
