1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _LINUX_DSSCOMP_H 20 #define _LINUX_DSSCOMP_H 21 enum omap_plane { 22 OMAP_DSS_GFX = 0, 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 OMAP_DSS_VIDEO1 = 1, 25 OMAP_DSS_VIDEO2 = 2, 26 OMAP_DSS_VIDEO3 = 3, 27 OMAP_DSS_WB = 4, 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 }; 30 enum omap_channel { 31 OMAP_DSS_CHANNEL_LCD = 0, 32 OMAP_DSS_CHANNEL_DIGIT = 1, 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 OMAP_DSS_CHANNEL_LCD2 = 2, 35 }; 36 enum omap_color_mode { 37 OMAP_DSS_COLOR_CLUT1 = 1 << 0, 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 OMAP_DSS_COLOR_CLUT2 = 1 << 1, 40 OMAP_DSS_COLOR_CLUT4 = 1 << 2, 41 OMAP_DSS_COLOR_CLUT8 = 1 << 3, 42 OMAP_DSS_COLOR_RGB12U = 1 << 4, 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 OMAP_DSS_COLOR_ARGB16 = 1 << 5, 45 OMAP_DSS_COLOR_RGB16 = 1 << 6, 46 OMAP_DSS_COLOR_RGB24U = 1 << 7, 47 OMAP_DSS_COLOR_RGB24P = 1 << 8, 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 OMAP_DSS_COLOR_YUV2 = 1 << 9, 50 OMAP_DSS_COLOR_UYVY = 1 << 10, 51 OMAP_DSS_COLOR_ARGB32 = 1 << 11, 52 OMAP_DSS_COLOR_RGBA32 = 1 << 12, 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 OMAP_DSS_COLOR_RGBX24 = 1 << 13, 55 OMAP_DSS_COLOR_RGBX32 = 1 << 13, 56 OMAP_DSS_COLOR_NV12 = 1 << 14, 57 OMAP_DSS_COLOR_RGBA16 = 1 << 15, 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 OMAP_DSS_COLOR_RGBX12 = 1 << 16, 60 OMAP_DSS_COLOR_RGBX16 = 1 << 16, 61 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, 62 OMAP_DSS_COLOR_XRGB15 = 1 << 18, 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, 65 }; 66 enum omap_dss_trans_key_type { 67 OMAP_DSS_COLOR_KEY_GFX_DST = 0, 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 OMAP_DSS_COLOR_KEY_VID_SRC = 1, 70 }; 71 enum omap_dss_display_state { 72 OMAP_DSS_DISPLAY_DISABLED = 0, 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 OMAP_DSS_DISPLAY_ACTIVE, 75 OMAP_DSS_DISPLAY_SUSPENDED, 76 OMAP_DSS_DISPLAY_TRANSITION, 77 }; 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 struct omap_video_timings { 80 __u16 x_res; 81 __u16 y_res; 82 __u32 pixel_clock; 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 __u16 hsw; 85 __u16 hfp; 86 __u16 hbp; 87 __u16 vsw; 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 __u16 vfp; 90 __u16 vbp; 91 }; 92 struct omap_dss_cconv_coefs { 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 __s16 ry, rcr, rcb; 95 __s16 gy, gcr, gcb; 96 __s16 by, bcr, bcb; 97 __u16 full_range; 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 } __attribute__ ((aligned(4))); 100 struct omap_dss_cpr_coefs { 101 __s16 rr, rg, rb; 102 __s16 gr, gg, gb; 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 __s16 br, bg, bb; 105 }; 106 struct dsscomp_videomode { 107 const char *name; 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 __u32 refresh; 110 __u32 xres; 111 __u32 yres; 112 __u32 pixclock; 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 __u32 left_margin; 115 __u32 right_margin; 116 __u32 upper_margin; 117 __u32 lower_margin; 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 __u32 hsync_len; 120 __u32 vsync_len; 121 __u32 sync; 122 __u32 vmode; 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 __u32 flag; 125 }; 126 enum s3d_disp_type { 127 S3D_DISP_NONE = 0, 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 S3D_DISP_FRAME_SEQ, 130 S3D_DISP_ROW_IL, 131 S3D_DISP_COL_IL, 132 S3D_DISP_PIX_IL, 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 S3D_DISP_CHECKB, 135 S3D_DISP_OVERUNDER, 136 S3D_DISP_SIDEBYSIDE, 137 }; 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 enum s3d_disp_sub_sampling { 140 S3D_DISP_SUB_SAMPLE_NONE = 0, 141 S3D_DISP_SUB_SAMPLE_V, 142 S3D_DISP_SUB_SAMPLE_H, 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 }; 145 enum s3d_disp_order { 146 S3D_DISP_ORDER_L = 0, 147 S3D_DISP_ORDER_R = 1, 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 }; 150 enum s3d_disp_view { 151 S3D_DISP_VIEW_L = 0, 152 S3D_DISP_VIEW_R, 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 }; 155 struct s3d_disp_info { 156 enum s3d_disp_type type; 157 enum s3d_disp_sub_sampling sub_samp; 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 enum s3d_disp_order order; 160 unsigned int gap; 161 }; 162 enum omap_dss_ilace_mode { 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 OMAP_DSS_ILACE = (1 << 0), 165 OMAP_DSS_ILACE_SEQ = (1 << 1), 166 OMAP_DSS_ILACE_SWAP = (1 << 2), 167 OMAP_DSS_ILACE_NONE = 0, 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 OMAP_DSS_ILACE_IL_TB = OMAP_DSS_ILACE, 170 OMAP_DSS_ILACE_IL_BT = OMAP_DSS_ILACE | OMAP_DSS_ILACE_SWAP, 171 OMAP_DSS_ILACE_SEQ_TB = OMAP_DSS_ILACE_IL_TB | OMAP_DSS_ILACE_SEQ, 172 OMAP_DSS_ILACE_SEQ_BT = OMAP_DSS_ILACE_IL_BT | OMAP_DSS_ILACE_SEQ, 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 }; 175 struct dss2_vc1_range_map_info { 176 __u8 enable; 177 __u8 range_y; 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 __u8 range_uv; 180 } __attribute__ ((aligned(4))); 181 struct dss2_rect_t { 182 __s32 x; 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 __s32 y; 185 __u32 w; 186 __u32 h; 187 } __attribute__ ((aligned(4))); 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 struct dss2_decim { 190 __u8 min_x; 191 __u8 max_x; 192 __u8 min_y; 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 __u8 max_y; 195 } __attribute__ ((aligned(4))); 196 struct dss2_ovl_cfg { 197 __u16 width; 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 __u16 height; 200 __u32 stride; 201 enum omap_color_mode color_mode; 202 __u8 pre_mult_alpha; 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 __u8 global_alpha; 205 __u8 rotation; 206 __u8 mirror; 207 enum omap_dss_ilace_mode ilace; 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 struct dss2_rect_t win; 210 struct dss2_rect_t crop; 211 struct dss2_decim decim; 212 struct omap_dss_cconv_coefs cconv; 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 struct dss2_vc1_range_map_info vc1; 215 __u8 ix; 216 __u8 zorder; 217 __u8 enabled; 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 __u8 zonly; 220 __u8 mgr_ix; 221 } __attribute__ ((aligned(4))); 222 enum omapdss_buffer_type { 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 OMAP_DSS_BUFTYPE_SDMA, 225 OMAP_DSS_BUFTYPE_TILER_8BIT, 226 OMAP_DSS_BUFTYPE_TILER_16BIT, 227 OMAP_DSS_BUFTYPE_TILER_32BIT, 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 OMAP_DSS_BUFTYPE_TILER_PAGE, 230 }; 231 enum omapdss_buffer_addressing_type { 232 OMAP_DSS_BUFADDR_DIRECT, 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 OMAP_DSS_BUFADDR_BYTYPE, 235 OMAP_DSS_BUFADDR_ION, 236 OMAP_DSS_BUFADDR_GRALLOC, 237 OMAP_DSS_BUFADDR_OVL_IX, 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 OMAP_DSS_BUFADDR_LAYER_IX, 240 OMAP_DSS_BUFADDR_FB, 241 }; 242 struct dss2_ovl_info { 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 struct dss2_ovl_cfg cfg; 245 enum omapdss_buffer_addressing_type addressing; 246 union { 247 struct { 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 void *address; 250 void *uv_address; 251 }; 252 struct { 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 enum omapdss_buffer_type ba_type; 255 enum omapdss_buffer_type uv_type; 256 }; 257 struct { 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 __u32 ba; 260 __u32 uv; 261 }; 262 }; 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 }; 265 struct dss2_mgr_info { 266 __u32 ix; 267 __u32 default_color; 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 enum omap_dss_trans_key_type trans_key_type; 270 __u32 trans_key; 271 struct omap_dss_cpr_coefs cpr_coefs; 272 __u8 trans_enabled; 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 __u8 interlaced; 275 __u8 alpha_blending; 276 __u8 cpr_enabled; 277 __u8 swap_rb; 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 } __attribute__ ((aligned(4))); 280 enum dsscomp_setup_mode { 281 DSSCOMP_SETUP_MODE_APPLY = (1 << 0), 282 DSSCOMP_SETUP_MODE_DISPLAY = (1 << 1), 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 DSSCOMP_SETUP_MODE_CAPTURE = (1 << 2), 285 DSSCOMP_SETUP_APPLY = DSSCOMP_SETUP_MODE_APPLY, 286 DSSCOMP_SETUP_DISPLAY = 287 DSSCOMP_SETUP_MODE_APPLY | DSSCOMP_SETUP_MODE_DISPLAY, 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 DSSCOMP_SETUP_CAPTURE = 290 DSSCOMP_SETUP_MODE_APPLY | DSSCOMP_SETUP_MODE_CAPTURE, 291 DSSCOMP_SETUP_DISPLAY_CAPTURE = 292 DSSCOMP_SETUP_DISPLAY | DSSCOMP_SETUP_CAPTURE, 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 }; 295 struct dsscomp_setup_mgr_data { 296 __u32 sync_id; 297 struct dss2_rect_t win; 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 enum dsscomp_setup_mode mode; 300 __u16 num_ovls; 301 __u16 get_sync_obj; 302 struct dss2_mgr_info mgr; 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 struct dss2_ovl_info ovls[0]; 305 }; 306 struct dsscomp_check_ovl_data { 307 enum dsscomp_setup_mode mode; 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 struct dss2_mgr_info mgr; 310 struct dss2_ovl_info ovl; 311 }; 312 struct dsscomp_setup_dispc_data { 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 __u32 sync_id; 315 enum dsscomp_setup_mode mode; 316 __u16 num_ovls; 317 __u16 num_mgrs; 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 __u16 get_sync_obj; 320 struct dss2_mgr_info mgrs[3]; 321 struct dss2_ovl_info ovls[5]; 322 }; 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 struct dsscomp_wb_copy_data { 325 struct dss2_ovl_info ovl, wb; 326 }; 327 struct dsscomp_display_info { 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 __u32 ix; 330 __u32 overlays_available; 331 __u32 overlays_owned; 332 enum omap_channel channel; 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 enum omap_dss_display_state state; 335 __u8 enabled; 336 struct omap_video_timings timings; 337 struct s3d_disp_info s3d_info; 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 struct dss2_mgr_info mgr; 340 __u16 width_in_mm; 341 __u16 height_in_mm; 342 __u32 modedb_len; 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 struct dsscomp_videomode modedb[]; 345 }; 346 struct dsscomp_setup_display_data { 347 __u32 ix; 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 struct dsscomp_videomode mode; 350 }; 351 enum dsscomp_wait_phase { 352 DSSCOMP_WAIT_PROGRAMMED = 1, 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 DSSCOMP_WAIT_DISPLAYED, 355 DSSCOMP_WAIT_RELEASED, 356 }; 357 struct dsscomp_wait_data { 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 __u32 timeout_us; 360 enum dsscomp_wait_phase phase; 361 }; 362 #define DSSCIOC_SETUP_MGR _IOW('O', 128, struct dsscomp_setup_mgr_data) 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 #define DSSCIOC_CHECK_OVL _IOWR('O', 129, struct dsscomp_check_ovl_data) 365 #define DSSCIOC_WB_COPY _IOW('O', 130, struct dsscomp_wb_copy_data) 366 #define DSSCIOC_QUERY_DISPLAY _IOWR('O', 131, struct dsscomp_display_info) 367 #define DSSCIOC_WAIT _IOW('O', 132, struct dsscomp_wait_data) 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 #define DSSCIOC_SETUP_DISPC _IOW('O', 133, struct dsscomp_setup_dispc_data) 370 #define DSSCIOC_SETUP_DISPLAY _IOW('O', 134, struct dsscomp_setup_display_data) 371 #endif 372
