1 //===--- arm_neon.td - ARM NEON compiler interface ------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the TableGen definitions from which the ARM NEON header 11 // file will be generated. See ARM document DUI0348B. 12 // 13 //===----------------------------------------------------------------------===// 14 15 class Op; 16 17 def OP_NONE : Op; 18 def OP_UNAVAILABLE : Op; 19 def OP_ADD : Op; 20 def OP_ADDL : Op; 21 def OP_ADDW : Op; 22 def OP_SUB : Op; 23 def OP_SUBL : Op; 24 def OP_SUBW : Op; 25 def OP_MUL : Op; 26 def OP_MLA : Op; 27 def OP_MLAL : Op; 28 def OP_MLS : Op; 29 def OP_MLSL : Op; 30 def OP_MUL_N : Op; 31 def OP_MLA_N : Op; 32 def OP_MLS_N : Op; 33 def OP_MLAL_N : Op; 34 def OP_MLSL_N : Op; 35 def OP_MUL_LN: Op; 36 def OP_MULL_LN : Op; 37 def OP_MLA_LN: Op; 38 def OP_MLS_LN: Op; 39 def OP_MLAL_LN : Op; 40 def OP_MLSL_LN : Op; 41 def OP_QDMULL_LN : Op; 42 def OP_QDMLAL_LN : Op; 43 def OP_QDMLSL_LN : Op; 44 def OP_QDMULH_LN : Op; 45 def OP_QRDMULH_LN : Op; 46 def OP_EQ : Op; 47 def OP_GE : Op; 48 def OP_LE : Op; 49 def OP_GT : Op; 50 def OP_LT : Op; 51 def OP_NEG : Op; 52 def OP_NOT : Op; 53 def OP_AND : Op; 54 def OP_OR : Op; 55 def OP_XOR : Op; 56 def OP_ANDN : Op; 57 def OP_ORN : Op; 58 def OP_CAST : Op; 59 def OP_HI : Op; 60 def OP_LO : Op; 61 def OP_CONC : Op; 62 def OP_DUP : Op; 63 def OP_DUP_LN: Op; 64 def OP_SEL : Op; 65 def OP_REV64 : Op; 66 def OP_REV32 : Op; 67 def OP_REV16 : Op; 68 def OP_REINT : Op; 69 def OP_ABDL : Op; 70 def OP_ABA : Op; 71 def OP_ABAL : Op; 72 73 class Inst <string n, string p, string t, Op o> { 74 string Name = n; 75 string Prototype = p; 76 string Types = t; 77 Op Operand = o; 78 bit isShift = 0; 79 bit isVCVT_N = 0; 80 } 81 82 // Used to generate Builtins.def: 83 // SInst: Instruction with signed/unsigned suffix (e.g., "s8", "u8", "p8") 84 // IInst: Instruction with generic integer suffix (e.g., "i8") 85 // WInst: Instruction with only bit size suffix (e.g., "8") 86 class SInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 87 class IInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 88 class WInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 89 90 // prototype: return (arg, arg, ...) 91 // v: void 92 // t: best-fit integer (int/poly args) 93 // x: signed integer (int/float args) 94 // u: unsigned integer (int/float args) 95 // f: float (int args) 96 // d: default 97 // g: default, ignore 'Q' size modifier. 98 // w: double width elements, same num elts 99 // n: double width elements, half num elts 100 // h: half width elements, double num elts 101 // e: half width elements, double num elts, unsigned 102 // i: constant int 103 // l: constant uint64 104 // s: scalar of element type 105 // a: scalar of element type (splat to vector type) 106 // k: default elt width, double num elts 107 // #: array of default vectors 108 // p: pointer type 109 // c: const pointer type 110 111 // sizes: 112 // c: char 113 // s: short 114 // i: int 115 // l: long 116 // f: float 117 // h: half-float 118 119 // size modifiers: 120 // U: unsigned 121 // Q: 128b 122 // P: polynomial 123 124 //////////////////////////////////////////////////////////////////////////////// 125 // E.3.1 Addition 126 def VADD : Inst<"vadd", "ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>; 127 def VADDL : Inst<"vaddl", "wdd", "csiUcUsUi", OP_ADDL>; 128 def VADDW : Inst<"vaddw", "wwd", "csiUcUsUi", OP_ADDW>; 129 def VHADD : SInst<"vhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 130 def VRHADD : SInst<"vrhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 131 def VQADD : SInst<"vqadd", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 132 def VADDHN : IInst<"vaddhn", "hkk", "silUsUiUl">; 133 def VRADDHN : IInst<"vraddhn", "hkk", "silUsUiUl">; 134 135 //////////////////////////////////////////////////////////////////////////////// 136 // E.3.2 Multiplication 137 def VMUL : Inst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>; 138 def VMULP : SInst<"vmul", "ddd", "PcQPc">; 139 def VMLA : Inst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>; 140 def VMLAL : Inst<"vmlal", "wwdd", "csiUcUsUi", OP_MLAL>; 141 def VMLS : Inst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>; 142 def VMLSL : Inst<"vmlsl", "wwdd", "csiUcUsUi", OP_MLSL>; 143 def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">; 144 def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">; 145 def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">; 146 def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">; 147 def VMULL : SInst<"vmull", "wdd", "csiUcUsUiPc">; 148 def VQDMULL : SInst<"vqdmull", "wdd", "si">; 149 150 //////////////////////////////////////////////////////////////////////////////// 151 // E.3.3 Subtraction 152 def VSUB : Inst<"vsub", "ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>; 153 def VSUBL : Inst<"vsubl", "wdd", "csiUcUsUi", OP_SUBL>; 154 def VSUBW : Inst<"vsubw", "wwd", "csiUcUsUi", OP_SUBW>; 155 def VQSUB : SInst<"vqsub", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 156 def VHSUB : SInst<"vhsub", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 157 def VSUBHN : IInst<"vsubhn", "hkk", "silUsUiUl">; 158 def VRSUBHN : IInst<"vrsubhn", "hkk", "silUsUiUl">; 159 160 //////////////////////////////////////////////////////////////////////////////// 161 // E.3.4 Comparison 162 def VCEQ : Inst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>; 163 def VCGE : Inst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>; 164 def VCLE : Inst<"vcle", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>; 165 def VCGT : Inst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>; 166 def VCLT : Inst<"vclt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>; 167 def VCAGE : IInst<"vcage", "udd", "fQf">; 168 def VCALE : IInst<"vcale", "udd", "fQf">; 169 def VCAGT : IInst<"vcagt", "udd", "fQf">; 170 def VCALT : IInst<"vcalt", "udd", "fQf">; 171 def VTST : WInst<"vtst", "udd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc">; 172 173 //////////////////////////////////////////////////////////////////////////////// 174 // E.3.5 Absolute Difference 175 def VABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 176 def VABDL : Inst<"vabdl", "wdd", "csiUcUsUi", OP_ABDL>; 177 def VABA : Inst<"vaba", "dddd", "csiUcUsUiQcQsQiQUcQUsQUi", OP_ABA>; 178 def VABAL : Inst<"vabal", "wwdd", "csiUcUsUi", OP_ABAL>; 179 180 //////////////////////////////////////////////////////////////////////////////// 181 // E.3.6 Max/Min 182 def VMAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 183 def VMIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 184 185 //////////////////////////////////////////////////////////////////////////////// 186 // E.3.7 Pairwise Addition 187 def VPADD : IInst<"vpadd", "ddd", "csiUcUsUif">; 188 def VPADDL : SInst<"vpaddl", "nd", "csiUcUsUiQcQsQiQUcQUsQUi">; 189 def VPADAL : SInst<"vpadal", "nnd", "csiUcUsUiQcQsQiQUcQUsQUi">; 190 191 //////////////////////////////////////////////////////////////////////////////// 192 // E.3.8-9 Folding Max/Min 193 def VPMAX : SInst<"vpmax", "ddd", "csiUcUsUif">; 194 def VPMIN : SInst<"vpmin", "ddd", "csiUcUsUif">; 195 196 //////////////////////////////////////////////////////////////////////////////// 197 // E.3.10 Reciprocal/Sqrt 198 def VRECPS : IInst<"vrecps", "ddd", "fQf">; 199 def VRSQRTS : IInst<"vrsqrts", "ddd", "fQf">; 200 201 //////////////////////////////////////////////////////////////////////////////// 202 // E.3.11 Shifts by signed variable 203 def VSHL : SInst<"vshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 204 def VQSHL : SInst<"vqshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 205 def VRSHL : SInst<"vrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 206 def VQRSHL : SInst<"vqrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 207 208 //////////////////////////////////////////////////////////////////////////////// 209 // E.3.12 Shifts by constant 210 let isShift = 1 in { 211 def VSHR_N : SInst<"vshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 212 def VSHL_N : IInst<"vshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 213 def VRSHR_N : SInst<"vrshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 214 def VSRA_N : SInst<"vsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 215 def VRSRA_N : SInst<"vrsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 216 def VQSHL_N : SInst<"vqshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 217 def VQSHLU_N : SInst<"vqshlu_n", "udi", "csilQcQsQiQl">; 218 def VSHRN_N : IInst<"vshrn_n", "hki", "silUsUiUl">; 219 def VQSHRUN_N : SInst<"vqshrun_n", "eki", "sil">; 220 def VQRSHRUN_N : SInst<"vqrshrun_n", "eki", "sil">; 221 def VQSHRN_N : SInst<"vqshrn_n", "hki", "silUsUiUl">; 222 def VRSHRN_N : IInst<"vrshrn_n", "hki", "silUsUiUl">; 223 def VQRSHRN_N : SInst<"vqrshrn_n", "hki", "silUsUiUl">; 224 def VSHLL_N : SInst<"vshll_n", "wdi", "csiUcUsUi">; 225 226 //////////////////////////////////////////////////////////////////////////////// 227 // E.3.13 Shifts with insert 228 def VSRI_N : WInst<"vsri_n", "dddi", 229 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 230 def VSLI_N : WInst<"vsli_n", "dddi", 231 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 232 } 233 234 //////////////////////////////////////////////////////////////////////////////// 235 // E.3.14 Loads and stores of a single vector 236 def VLD1 : WInst<"vld1", "dc", 237 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 238 def VLD1_LANE : WInst<"vld1_lane", "dcdi", 239 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 240 def VLD1_DUP : WInst<"vld1_dup", "dc", 241 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 242 def VST1 : WInst<"vst1", "vpd", 243 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 244 def VST1_LANE : WInst<"vst1_lane", "vpdi", 245 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 246 247 //////////////////////////////////////////////////////////////////////////////// 248 // E.3.15 Loads and stores of an N-element structure 249 def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 250 def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 251 def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 252 def VLD2_DUP : WInst<"vld2_dup", "2c", "UcUsUiUlcsilhfPcPs">; 253 def VLD3_DUP : WInst<"vld3_dup", "3c", "UcUsUiUlcsilhfPcPs">; 254 def VLD4_DUP : WInst<"vld4_dup", "4c", "UcUsUiUlcsilhfPcPs">; 255 def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 256 def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 257 def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 258 def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 259 def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 260 def VST4 : WInst<"vst4", "vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 261 def VST2_LANE : WInst<"vst2_lane", "vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 262 def VST3_LANE : WInst<"vst3_lane", "vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 263 def VST4_LANE : WInst<"vst4_lane", "vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 264 265 //////////////////////////////////////////////////////////////////////////////// 266 // E.3.16 Extract lanes from a vector 267 def VGET_LANE : IInst<"vget_lane", "sdi", 268 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 269 270 //////////////////////////////////////////////////////////////////////////////// 271 // E.3.17 Set lanes within a vector 272 def VSET_LANE : IInst<"vset_lane", "dsdi", 273 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 274 275 //////////////////////////////////////////////////////////////////////////////// 276 // E.3.18 Initialize a vector from bit pattern 277 def VCREATE: Inst<"vcreate", "dl", "csihfUcUsUiUlPcPsl", OP_CAST>; 278 279 //////////////////////////////////////////////////////////////////////////////// 280 // E.3.19 Set all lanes to same value 281 def VDUP_N : Inst<"vdup_n", "ds", 282 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>; 283 def VMOV_N : Inst<"vmov_n", "ds", 284 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>; 285 def VDUP_LANE : Inst<"vdup_lane", "dgi", 286 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl",OP_DUP_LN>; 287 288 //////////////////////////////////////////////////////////////////////////////// 289 // E.3.20 Combining vectors 290 def VCOMBINE : Inst<"vcombine", "kdd", "csilhfUcUsUiUlPcPs", OP_CONC>; 291 292 //////////////////////////////////////////////////////////////////////////////// 293 // E.3.21 Splitting vectors 294 def VGET_HIGH : Inst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>; 295 def VGET_LOW : Inst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>; 296 297 //////////////////////////////////////////////////////////////////////////////// 298 // E.3.22 Converting vectors 299 def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">; 300 def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">; 301 def VCVT_F16 : SInst<"vcvt_f16", "hk", "f">; 302 def VCVT_F32 : SInst<"vcvt_f32", "fd", "iUiQiQUi">; 303 def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "fd", "h">; 304 let isVCVT_N = 1 in { 305 def VCVT_N_S32 : SInst<"vcvt_n_s32", "xdi", "fQf">; 306 def VCVT_N_U32 : SInst<"vcvt_n_u32", "udi", "fQf">; 307 def VCVT_N_F32 : SInst<"vcvt_n_f32", "fdi", "iUiQiQUi">; 308 } 309 def VMOVN : IInst<"vmovn", "hk", "silUsUiUl">; 310 def VMOVL : SInst<"vmovl", "wd", "csiUcUsUi">; 311 def VQMOVN : SInst<"vqmovn", "hk", "silUsUiUl">; 312 def VQMOVUN : SInst<"vqmovun", "ek", "sil">; 313 314 //////////////////////////////////////////////////////////////////////////////// 315 // E.3.23-24 Table lookup, Extended table lookup 316 def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">; 317 def VTBL2 : WInst<"vtbl2", "d2t", "UccPc">; 318 def VTBL3 : WInst<"vtbl3", "d3t", "UccPc">; 319 def VTBL4 : WInst<"vtbl4", "d4t", "UccPc">; 320 def VTBX1 : WInst<"vtbx1", "dddt", "UccPc">; 321 def VTBX2 : WInst<"vtbx2", "dd2t", "UccPc">; 322 def VTBX3 : WInst<"vtbx3", "dd3t", "UccPc">; 323 def VTBX4 : WInst<"vtbx4", "dd4t", "UccPc">; 324 325 //////////////////////////////////////////////////////////////////////////////// 326 // E.3.25 Operations with a scalar value 327 def VMLA_LANE : Inst<"vmla_lane", "dddgi", "siUsUifQsQiQUsQUiQf", OP_MLA_LN>; 328 def VMLAL_LANE : Inst<"vmlal_lane", "wwddi", "siUsUi", OP_MLAL_LN>; 329 def VQDMLAL_LANE : Inst<"vqdmlal_lane", "wwddi", "si", OP_QDMLAL_LN>; 330 def VMLS_LANE : Inst<"vmls_lane", "dddgi", "siUsUifQsQiQUsQUiQf", OP_MLS_LN>; 331 def VMLSL_LANE : Inst<"vmlsl_lane", "wwddi", "siUsUi", OP_MLSL_LN>; 332 def VQDMLSL_LANE : Inst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>; 333 def VMUL_N : Inst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>; 334 def VMUL_LANE : Inst<"vmul_lane", "ddgi", "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>; 335 def VMULL_N : SInst<"vmull_n", "wda", "siUsUi">; 336 def VMULL_LANE : Inst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>; 337 def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">; 338 def VQDMULL_LANE : Inst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>; 339 def VQDMULH_N : SInst<"vqdmulh_n", "dda", "siQsQi">; 340 def VQDMULH_LANE : Inst<"vqdmulh_lane", "ddgi", "siQsQi", OP_QDMULH_LN>; 341 def VQRDMULH_N : SInst<"vqrdmulh_n", "dda", "siQsQi">; 342 def VQRDMULH_LANE : Inst<"vqrdmulh_lane", "ddgi", "siQsQi", OP_QRDMULH_LN>; 343 def VMLA_N : Inst<"vmla_n", "ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>; 344 def VMLAL_N : Inst<"vmlal_n", "wwda", "siUsUi", OP_MLAL_N>; 345 def VQDMLAL_N : SInst<"vqdmlal_n", "wwda", "si">; 346 def VMLS_N : Inst<"vmls_n", "ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>; 347 def VMLSL_N : Inst<"vmlsl_n", "wwda", "siUsUi", OP_MLSL_N>; 348 def VQDMLSL_N : SInst<"vqdmlsl_n", "wwda", "si">; 349 350 //////////////////////////////////////////////////////////////////////////////// 351 // E.3.26 Vector Extract 352 def VEXT : WInst<"vext", "dddi", 353 "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">; 354 355 //////////////////////////////////////////////////////////////////////////////// 356 // E.3.27 Reverse vector elements 357 def VREV64 : Inst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf", 358 OP_REV64>; 359 def VREV32 : Inst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>; 360 def VREV16 : Inst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>; 361 362 //////////////////////////////////////////////////////////////////////////////// 363 // E.3.28 Other single operand arithmetic 364 def VABS : SInst<"vabs", "dd", "csifQcQsQiQf">; 365 def VQABS : SInst<"vqabs", "dd", "csiQcQsQi">; 366 def VNEG : Inst<"vneg", "dd", "csifQcQsQiQf", OP_NEG>; 367 def VQNEG : SInst<"vqneg", "dd", "csiQcQsQi">; 368 def VCLS : SInst<"vcls", "dd", "csiQcQsQi">; 369 def VCLZ : IInst<"vclz", "dd", "csiUcUsUiQcQsQiQUcQUsQUi">; 370 def VCNT : WInst<"vcnt", "dd", "UccPcQUcQcQPc">; 371 def VRECPE : SInst<"vrecpe", "dd", "fUiQfQUi">; 372 def VRSQRTE : SInst<"vrsqrte", "dd", "fUiQfQUi">; 373 374 //////////////////////////////////////////////////////////////////////////////// 375 // E.3.29 Logical operations 376 def VMVN : Inst<"vmvn", "dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>; 377 def VAND : Inst<"vand", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>; 378 def VORR : Inst<"vorr", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>; 379 def VEOR : Inst<"veor", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>; 380 def VBIC : Inst<"vbic", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>; 381 def VORN : Inst<"vorn", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>; 382 def VBSL : SInst<"vbsl", "dudd", 383 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">; 384 385 //////////////////////////////////////////////////////////////////////////////// 386 // E.3.30 Transposition operations 387 def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 388 def VZIP : WInst<"vzip", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 389 def VUZP : WInst<"vuzp", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 390 391 //////////////////////////////////////////////////////////////////////////////// 392 // E.3.31 Vector reinterpret cast operations 393 def VREINTERPRET 394 : Inst<"vreinterpret", "dd", 395 "csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs", OP_REINT>; 396 397 //////////////////////////////////////////////////////////////////////////////// 398 // Vector fused multiply-add operations 399 400 def VFMA : SInst<"vfma", "dddd", "fQf">; 401
