1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 2002 by Ralf Baechle 7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. 8 * Copyright (C) 2002 Maciej W. Rozycki 9 */ 10 #ifndef _ASM_PGTABLE_BITS_H 11 #define _ASM_PGTABLE_BITS_H 12 13 14 /* 15 * Note that we shift the lower 32bits of each EntryLo[01] entry 16 * 6 bits to the left. That way we can convert the PFN into the 17 * physical address by a single 'and' operation and gain 6 additional 18 * bits for storing information which isn't present in a normal 19 * MIPS page table. 20 * 21 * Similar to the Alpha port, we need to keep track of the ref 22 * and mod bits in software. We have a software "yeah you can read 23 * from this page" bit, and a hardware one which actually lets the 24 * process read from the page. On the same token we have a software 25 * writable bit and the real hardware one which actually lets the 26 * process write to the page, this keeps a mod bit via the hardware 27 * dirty bit. 28 * 29 * Certain revisions of the R4000 and R5000 have a bug where if a 30 * certain sequence occurs in the last 3 instructions of an executable 31 * page, and the following page is not mapped, the cpu can do 32 * unpredictable things. The code (when it is written) to deal with 33 * this problem will be in the update_mmu_cache() code for the r4k. 34 */ 35 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 36 37 #define _PAGE_PRESENT (1<<6) /* implemented in software */ 38 #define _PAGE_READ (1<<7) /* implemented in software */ 39 #define _PAGE_WRITE (1<<8) /* implemented in software */ 40 #define _PAGE_ACCESSED (1<<9) /* implemented in software */ 41 #define _PAGE_MODIFIED (1<<10) /* implemented in software */ 42 #define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */ 43 44 #define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */ 45 #define _PAGE_GLOBAL (1<<0) 46 #define _PAGE_VALID (1<<1) 47 #define _PAGE_SILENT_READ (1<<1) /* synonym */ 48 #define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */ 49 #define _PAGE_SILENT_WRITE (1<<2) 50 #define _CACHE_SHIFT 3 51 #define _CACHE_MASK (7<<3) 52 53 #else 54 55 #define _PAGE_PRESENT (1<<0) /* implemented in software */ 56 #define _PAGE_READ (1<<1) /* implemented in software */ 57 #define _PAGE_WRITE (1<<2) /* implemented in software */ 58 #define _PAGE_ACCESSED (1<<3) /* implemented in software */ 59 #define _PAGE_MODIFIED (1<<4) /* implemented in software */ 60 #define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */ 61 62 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 63 64 #define _PAGE_GLOBAL (1<<8) 65 #define _PAGE_VALID (1<<9) 66 #define _PAGE_SILENT_READ (1<<9) /* synonym */ 67 #define _PAGE_DIRTY (1<<10) /* The MIPS dirty bit */ 68 #define _PAGE_SILENT_WRITE (1<<10) 69 #define _CACHE_UNCACHED (1<<11) 70 #define _CACHE_MASK (1<<11) 71 72 #else 73 74 #define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ 75 #define _PAGE_GLOBAL (1<<6) 76 #define _PAGE_VALID (1<<7) 77 #define _PAGE_SILENT_READ (1<<7) /* synonym */ 78 #define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ 79 #define _PAGE_SILENT_WRITE (1<<8) 80 #define _CACHE_SHIFT 9 81 #define _CACHE_MASK (7<<9) 82 83 #endif 84 #endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ 85 86 87 /* 88 * Cache attributes 89 */ 90 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 91 92 #define _CACHE_CACHABLE_NONCOHERENT 0 93 94 #elif defined(CONFIG_CPU_SB1) 95 96 /* No penalty for being coherent on the SB1, so just 97 use it for "noncoherent" spaces, too. Shouldn't hurt. */ 98 99 #define _CACHE_UNCACHED (2<<_CACHE_SHIFT) 100 #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) 101 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) 102 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) 103 104 #elif defined(CONFIG_CPU_RM9000) 105 106 #define _CACHE_WT (0<<_CACHE_SHIFT) 107 #define _CACHE_WTWA (1<<_CACHE_SHIFT) 108 #define _CACHE_UC_B (2<<_CACHE_SHIFT) 109 #define _CACHE_WB (3<<_CACHE_SHIFT) 110 #define _CACHE_CWBEA (4<<_CACHE_SHIFT) 111 #define _CACHE_CWB (5<<_CACHE_SHIFT) 112 #define _CACHE_UCNB (6<<_CACHE_SHIFT) 113 #define _CACHE_FPC (7<<_CACHE_SHIFT) 114 115 #define _CACHE_UNCACHED _CACHE_UC_B 116 #define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB 117 118 #else 119 120 #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */ 121 #define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */ 122 #define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */ 123 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */ 124 #define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */ 125 #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */ 126 #define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */ 127 #define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */ 128 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */ 129 130 #endif 131 132 #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) 133 #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) 134 135 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) 136 137 #endif /* _ASM_PGTABLE_BITS_H */ 138
