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      1 /*
      2  *  linux/include/linux/mtd/onenand_regs.h
      3  *
      4  *  OneNAND Register header file
      5  *
      6  *  Copyright (C) 2005 Samsung Electronics
      7  *
      8  * This program is free software; you can redistribute it and/or modify
      9  * it under the terms of the GNU General Public License version 2 as
     10  * published by the Free Software Foundation.
     11  */
     12 
     13 #ifndef __ONENAND_REG_H
     14 #define __ONENAND_REG_H
     15 
     16 /* Memory Address Map Translation (Word order) */
     17 #define ONENAND_MEMORY_MAP(x)		((x) << 1)
     18 
     19 /*
     20  * External BufferRAM area
     21  */
     22 #define	ONENAND_BOOTRAM			ONENAND_MEMORY_MAP(0x0000)
     23 #define	ONENAND_DATARAM			ONENAND_MEMORY_MAP(0x0200)
     24 #define	ONENAND_SPARERAM		ONENAND_MEMORY_MAP(0x8010)
     25 
     26 /*
     27  * OneNAND Registers
     28  */
     29 #define ONENAND_REG_MANUFACTURER_ID	ONENAND_MEMORY_MAP(0xF000)
     30 #define ONENAND_REG_DEVICE_ID		ONENAND_MEMORY_MAP(0xF001)
     31 #define ONENAND_REG_VERSION_ID		ONENAND_MEMORY_MAP(0xF002)
     32 #define ONENAND_REG_DATA_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF003)
     33 #define ONENAND_REG_BOOT_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF004)
     34 #define ONENAND_REG_NUM_BUFFERS		ONENAND_MEMORY_MAP(0xF005)
     35 #define ONENAND_REG_TECHNOLOGY		ONENAND_MEMORY_MAP(0xF006)
     36 
     37 #define ONENAND_REG_START_ADDRESS1	ONENAND_MEMORY_MAP(0xF100)
     38 #define ONENAND_REG_START_ADDRESS2	ONENAND_MEMORY_MAP(0xF101)
     39 #define ONENAND_REG_START_ADDRESS3	ONENAND_MEMORY_MAP(0xF102)
     40 #define ONENAND_REG_START_ADDRESS4	ONENAND_MEMORY_MAP(0xF103)
     41 #define ONENAND_REG_START_ADDRESS5	ONENAND_MEMORY_MAP(0xF104)
     42 #define ONENAND_REG_START_ADDRESS6	ONENAND_MEMORY_MAP(0xF105)
     43 #define ONENAND_REG_START_ADDRESS7	ONENAND_MEMORY_MAP(0xF106)
     44 #define ONENAND_REG_START_ADDRESS8	ONENAND_MEMORY_MAP(0xF107)
     45 
     46 #define ONENAND_REG_START_BUFFER	ONENAND_MEMORY_MAP(0xF200)
     47 #define ONENAND_REG_COMMAND		ONENAND_MEMORY_MAP(0xF220)
     48 #define ONENAND_REG_SYS_CFG1		ONENAND_MEMORY_MAP(0xF221)
     49 #define ONENAND_REG_SYS_CFG2		ONENAND_MEMORY_MAP(0xF222)
     50 #define ONENAND_REG_CTRL_STATUS		ONENAND_MEMORY_MAP(0xF240)
     51 #define ONENAND_REG_INTERRUPT		ONENAND_MEMORY_MAP(0xF241)
     52 #define ONENAND_REG_START_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24C)
     53 #define ONENAND_REG_END_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24D)
     54 #define ONENAND_REG_WP_STATUS		ONENAND_MEMORY_MAP(0xF24E)
     55 
     56 #define ONENAND_REG_ECC_STATUS		ONENAND_MEMORY_MAP(0xFF00)
     57 #define ONENAND_REG_ECC_M0		ONENAND_MEMORY_MAP(0xFF01)
     58 #define ONENAND_REG_ECC_S0		ONENAND_MEMORY_MAP(0xFF02)
     59 #define ONENAND_REG_ECC_M1		ONENAND_MEMORY_MAP(0xFF03)
     60 #define ONENAND_REG_ECC_S1		ONENAND_MEMORY_MAP(0xFF04)
     61 #define ONENAND_REG_ECC_M2		ONENAND_MEMORY_MAP(0xFF05)
     62 #define ONENAND_REG_ECC_S2		ONENAND_MEMORY_MAP(0xFF06)
     63 #define ONENAND_REG_ECC_M3		ONENAND_MEMORY_MAP(0xFF07)
     64 #define ONENAND_REG_ECC_S3		ONENAND_MEMORY_MAP(0xFF08)
     65 
     66 /*
     67  * Device ID Register F001h (R)
     68  */
     69 #define ONENAND_DEVICE_DENSITY_SHIFT	(4)
     70 #define ONENAND_DEVICE_IS_DDP		(1 << 3)
     71 #define ONENAND_DEVICE_IS_DEMUX		(1 << 2)
     72 #define ONENAND_DEVICE_VCC_MASK		(0x3)
     73 
     74 #define ONENAND_DEVICE_DENSITY_512Mb	(0x002)
     75 
     76 /*
     77  * Version ID Register F002h (R)
     78  */
     79 #define ONENAND_VERSION_PROCESS_SHIFT	(8)
     80 
     81 /*
     82  * Start Address 1 F100h (R/W)
     83  */
     84 #define ONENAND_DDP_SHIFT		(15)
     85 
     86 /*
     87  * Start Address 8 F107h (R/W)
     88  */
     89 #define ONENAND_FPA_MASK		(0x3f)
     90 #define ONENAND_FPA_SHIFT		(2)
     91 #define ONENAND_FSA_MASK		(0x03)
     92 
     93 /*
     94  * Start Buffer Register F200h (R/W)
     95  */
     96 #define ONENAND_BSA_MASK		(0x03)
     97 #define ONENAND_BSA_SHIFT		(8)
     98 #define ONENAND_BSA_BOOTRAM		(0 << 2)
     99 #define ONENAND_BSA_DATARAM0		(2 << 2)
    100 #define ONENAND_BSA_DATARAM1		(3 << 2)
    101 #define ONENAND_BSC_MASK		(0x03)
    102 
    103 /*
    104  * Command Register F220h (R/W)
    105  */
    106 #define ONENAND_CMD_READ		(0x00)
    107 #define ONENAND_CMD_READOOB		(0x13)
    108 #define ONENAND_CMD_PROG		(0x80)
    109 #define ONENAND_CMD_PROGOOB		(0x1A)
    110 #define ONENAND_CMD_UNLOCK		(0x23)
    111 #define ONENAND_CMD_LOCK		(0x2A)
    112 #define ONENAND_CMD_LOCK_TIGHT		(0x2C)
    113 #define ONENAND_CMD_ERASE		(0x94)
    114 #define ONENAND_CMD_RESET		(0xF0)
    115 #define ONENAND_CMD_OTP_ACCESS		(0x65)
    116 #define ONENAND_CMD_READID		(0x90)
    117 
    118 /* NOTE: Those are not *REAL* commands */
    119 #define ONENAND_CMD_BUFFERRAM		(0x1978)
    120 
    121 /*
    122  * System Configuration 1 Register F221h (R, R/W)
    123  */
    124 #define ONENAND_SYS_CFG1_SYNC_READ	(1 << 15)
    125 #define ONENAND_SYS_CFG1_BRL_7		(7 << 12)
    126 #define ONENAND_SYS_CFG1_BRL_6		(6 << 12)
    127 #define ONENAND_SYS_CFG1_BRL_5		(5 << 12)
    128 #define ONENAND_SYS_CFG1_BRL_4		(4 << 12)
    129 #define ONENAND_SYS_CFG1_BRL_3		(3 << 12)
    130 #define ONENAND_SYS_CFG1_BRL_10		(2 << 12)
    131 #define ONENAND_SYS_CFG1_BRL_9		(1 << 12)
    132 #define ONENAND_SYS_CFG1_BRL_8		(0 << 12)
    133 #define ONENAND_SYS_CFG1_BRL_SHIFT	(12)
    134 #define ONENAND_SYS_CFG1_BL_32		(4 << 9)
    135 #define ONENAND_SYS_CFG1_BL_16		(3 << 9)
    136 #define ONENAND_SYS_CFG1_BL_8		(2 << 9)
    137 #define ONENAND_SYS_CFG1_BL_4		(1 << 9)
    138 #define ONENAND_SYS_CFG1_BL_CONT	(0 << 9)
    139 #define ONENAND_SYS_CFG1_BL_SHIFT	(9)
    140 #define ONENAND_SYS_CFG1_NO_ECC		(1 << 8)
    141 #define ONENAND_SYS_CFG1_RDY		(1 << 7)
    142 #define ONENAND_SYS_CFG1_INT		(1 << 6)
    143 #define ONENAND_SYS_CFG1_IOBE		(1 << 5)
    144 #define ONENAND_SYS_CFG1_RDY_CONF	(1 << 4)
    145 
    146 /*
    147  * Controller Status Register F240h (R)
    148  */
    149 #define ONENAND_CTRL_ONGO		(1 << 15)
    150 #define ONENAND_CTRL_LOCK		(1 << 14)
    151 #define ONENAND_CTRL_LOAD		(1 << 13)
    152 #define ONENAND_CTRL_PROGRAM		(1 << 12)
    153 #define ONENAND_CTRL_ERASE		(1 << 11)
    154 #define ONENAND_CTRL_ERROR		(1 << 10)
    155 #define ONENAND_CTRL_RSTB		(1 << 7)
    156 #define ONENAND_CTRL_OTP_L		(1 << 6)
    157 #define ONENAND_CTRL_OTP_BL		(1 << 5)
    158 
    159 /*
    160  * Interrupt Status Register F241h (R)
    161  */
    162 #define ONENAND_INT_MASTER		(1 << 15)
    163 #define ONENAND_INT_READ		(1 << 7)
    164 #define ONENAND_INT_WRITE		(1 << 6)
    165 #define ONENAND_INT_ERASE		(1 << 5)
    166 #define ONENAND_INT_RESET		(1 << 4)
    167 #define ONENAND_INT_CLEAR		(0 << 0)
    168 
    169 /*
    170  * NAND Flash Write Protection Status Register F24Eh (R)
    171  */
    172 #define ONENAND_WP_US			(1 << 2)
    173 #define ONENAND_WP_LS			(1 << 1)
    174 #define ONENAND_WP_LTS			(1 << 0)
    175 
    176 /*
    177  * ECC Status Reigser FF00h (R)
    178  */
    179 #define ONENAND_ECC_1BIT		(1 << 0)
    180 #define ONENAND_ECC_2BIT		(1 << 1)
    181 #define ONENAND_ECC_2BIT_ALL		(0xAAAA)
    182 
    183 /*
    184  * One-Time Programmable (OTP)
    185  */
    186 #define ONENAND_OTP_LOCK_OFFSET		(14)
    187 
    188 #endif	/* __ONENAND_REG_H */
    189