1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements an allocation order for virtual registers. 11 // 12 // The preferred allocation order for a virtual register depends on allocation 13 // hints and target hooks. The AllocationOrder class encapsulates all of that. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #define DEBUG_TYPE "regalloc" 18 #include "AllocationOrder.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/CodeGen/RegisterClassInfo.h" 22 #include "llvm/CodeGen/VirtRegMap.h" 23 #include "llvm/Support/Debug.h" 24 #include "llvm/Support/raw_ostream.h" 25 26 using namespace llvm; 27 28 // Compare VirtRegMap::getRegAllocPref(). 29 AllocationOrder::AllocationOrder(unsigned VirtReg, 30 const VirtRegMap &VRM, 31 const RegisterClassInfo &RegClassInfo) 32 : Pos(0) { 33 const MachineFunction &MF = VRM.getMachineFunction(); 34 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); 35 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); 36 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM); 37 rewind(); 38 39 DEBUG({ 40 if (!Hints.empty()) { 41 dbgs() << "hints:"; 42 for (unsigned I = 0, E = Hints.size(); I != E; ++I) 43 dbgs() << ' ' << PrintReg(Hints[I], TRI); 44 dbgs() << '\n'; 45 } 46 }); 47 #ifndef NDEBUG 48 for (unsigned I = 0, E = Hints.size(); I != E; ++I) 49 assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() && 50 "Target hint is outside allocation order."); 51 #endif 52 } 53
