1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Thumb instruction set. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Thumb specific DAG Nodes. 16 // 17 18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 20 SDNPVariadic]>; 21 22 def imm_sr_XFORM: SDNodeXForm<imm, [{ 23 unsigned Imm = N->getZExtValue(); 24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32); 25 }]>; 26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; } 27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{ 28 uint64_t Imm = N->getZExtValue(); 29 return Imm > 0 && Imm <= 32; 30 }], imm_sr_XFORM> { 31 let PrintMethod = "printThumbSRImm"; 32 let ParserMatchClass = ThumbSRImmAsmOperand; 33 } 34 35 def imm_comp_XFORM : SDNodeXForm<imm, [{ 36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 37 }]>; 38 39 def imm0_7_neg : PatLeaf<(i32 imm), [{ 40 return (uint32_t)-N->getZExtValue() < 8; 41 }], imm_neg_XFORM>; 42 43 def imm0_255_comp : PatLeaf<(i32 imm), [{ 44 return ~((uint32_t)N->getZExtValue()) < 256; 45 }]>; 46 47 def imm8_255 : ImmLeaf<i32, [{ 48 return Imm >= 8 && Imm < 256; 49 }]>; 50 def imm8_255_neg : PatLeaf<(i32 imm), [{ 51 unsigned Val = -N->getZExtValue(); 52 return Val >= 8 && Val < 256; 53 }], imm_neg_XFORM>; 54 55 // Break imm's up into two pieces: an immediate + a left shift. This uses 56 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 57 // to get the val/shift pieces. 58 def thumb_immshifted : PatLeaf<(imm), [{ 59 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 60 }]>; 61 62 def thumb_immshifted_val : SDNodeXForm<imm, [{ 63 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 64 return CurDAG->getTargetConstant(V, MVT::i32); 65 }]>; 66 67 def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 68 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 69 return CurDAG->getTargetConstant(V, MVT::i32); 70 }]>; 71 72 // ADR instruction labels. 73 def t_adrlabel : Operand<i32> { 74 let EncoderMethod = "getThumbAdrLabelOpValue"; 75 } 76 77 // Scaled 4 immediate. 78 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } 79 def t_imm0_1020s4 : Operand<i32> { 80 let PrintMethod = "printThumbS4ImmOperand"; 81 let ParserMatchClass = t_imm0_1020s4_asmoperand; 82 let OperandType = "OPERAND_IMMEDIATE"; 83 } 84 85 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } 86 def t_imm0_508s4 : Operand<i32> { 87 let PrintMethod = "printThumbS4ImmOperand"; 88 let ParserMatchClass = t_imm0_508s4_asmoperand; 89 let OperandType = "OPERAND_IMMEDIATE"; 90 } 91 // Alias use only, so no printer is necessary. 92 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; } 93 def t_imm0_508s4_neg : Operand<i32> { 94 let ParserMatchClass = t_imm0_508s4_neg_asmoperand; 95 let OperandType = "OPERAND_IMMEDIATE"; 96 } 97 98 // Define Thumb specific addressing modes. 99 100 let OperandType = "OPERAND_PCREL" in { 101 def t_brtarget : Operand<OtherVT> { 102 let EncoderMethod = "getThumbBRTargetOpValue"; 103 let DecoderMethod = "DecodeThumbBROperand"; 104 } 105 106 def t_bcctarget : Operand<i32> { 107 let EncoderMethod = "getThumbBCCTargetOpValue"; 108 let DecoderMethod = "DecodeThumbBCCTargetOperand"; 109 } 110 111 def t_cbtarget : Operand<i32> { 112 let EncoderMethod = "getThumbCBTargetOpValue"; 113 let DecoderMethod = "DecodeThumbCmpBROperand"; 114 } 115 116 def t_bltarget : Operand<i32> { 117 let EncoderMethod = "getThumbBLTargetOpValue"; 118 let DecoderMethod = "DecodeThumbBLTargetOperand"; 119 } 120 121 def t_blxtarget : Operand<i32> { 122 let EncoderMethod = "getThumbBLXTargetOpValue"; 123 let DecoderMethod = "DecodeThumbBLXOffset"; 124 } 125 } 126 127 // t_addrmode_rr := reg + reg 128 // 129 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; } 130 def t_addrmode_rr : Operand<i32>, 131 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 132 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 133 let PrintMethod = "printThumbAddrModeRROperand"; 134 let DecoderMethod = "DecodeThumbAddrModeRR"; 135 let ParserMatchClass = t_addrmode_rr_asm_operand; 136 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 137 } 138 139 // t_addrmode_rrs := reg + reg 140 // 141 // We use separate scaled versions because the Select* functions need 142 // to explicitly check for a matching constant and return false here so that 143 // the reg+imm forms will match instead. This is a horrible way to do that, 144 // as it forces tight coupling between the methods, but it's how selectiondag 145 // currently works. 146 def t_addrmode_rrs1 : Operand<i32>, 147 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 148 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 149 let PrintMethod = "printThumbAddrModeRROperand"; 150 let DecoderMethod = "DecodeThumbAddrModeRR"; 151 let ParserMatchClass = t_addrmode_rr_asm_operand; 152 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 153 } 154 def t_addrmode_rrs2 : Operand<i32>, 155 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 156 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 157 let DecoderMethod = "DecodeThumbAddrModeRR"; 158 let PrintMethod = "printThumbAddrModeRROperand"; 159 let ParserMatchClass = t_addrmode_rr_asm_operand; 160 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 161 } 162 def t_addrmode_rrs4 : Operand<i32>, 163 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 164 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 165 let DecoderMethod = "DecodeThumbAddrModeRR"; 166 let PrintMethod = "printThumbAddrModeRROperand"; 167 let ParserMatchClass = t_addrmode_rr_asm_operand; 168 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 169 } 170 171 // t_addrmode_is4 := reg + imm5 * 4 172 // 173 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; } 174 def t_addrmode_is4 : Operand<i32>, 175 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 176 let EncoderMethod = "getAddrModeISOpValue"; 177 let DecoderMethod = "DecodeThumbAddrModeIS"; 178 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 179 let ParserMatchClass = t_addrmode_is4_asm_operand; 180 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 181 } 182 183 // t_addrmode_is2 := reg + imm5 * 2 184 // 185 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; } 186 def t_addrmode_is2 : Operand<i32>, 187 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 188 let EncoderMethod = "getAddrModeISOpValue"; 189 let DecoderMethod = "DecodeThumbAddrModeIS"; 190 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 191 let ParserMatchClass = t_addrmode_is2_asm_operand; 192 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 193 } 194 195 // t_addrmode_is1 := reg + imm5 196 // 197 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } 198 def t_addrmode_is1 : Operand<i32>, 199 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 200 let EncoderMethod = "getAddrModeISOpValue"; 201 let DecoderMethod = "DecodeThumbAddrModeIS"; 202 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 203 let ParserMatchClass = t_addrmode_is1_asm_operand; 204 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 205 } 206 207 // t_addrmode_sp := sp + imm8 * 4 208 // 209 // FIXME: This really shouldn't have an explicit SP operand at all. It should 210 // be implicit, just like in the instruction encoding itself. 211 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; } 212 def t_addrmode_sp : Operand<i32>, 213 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 214 let EncoderMethod = "getAddrModeThumbSPOpValue"; 215 let DecoderMethod = "DecodeThumbAddrModeSP"; 216 let PrintMethod = "printThumbAddrModeSPOperand"; 217 let ParserMatchClass = t_addrmode_sp_asm_operand; 218 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 219 } 220 221 // t_addrmode_pc := <label> => pc + imm8 * 4 222 // 223 def t_addrmode_pc : Operand<i32> { 224 let EncoderMethod = "getAddrModePCOpValue"; 225 let DecoderMethod = "DecodeThumbAddrModePC"; 226 let PrintMethod = "printThumbLdrLabelOperand"; 227 } 228 229 //===----------------------------------------------------------------------===// 230 // Miscellaneous Instructions. 231 // 232 233 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 234 // from removing one half of the matched pairs. That breaks PEI, which assumes 235 // these will always be in pairs, and asserts if it finds otherwise. Better way? 236 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 237 def tADJCALLSTACKUP : 238 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 239 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 240 Requires<[IsThumb, IsThumb1Only]>; 241 242 def tADJCALLSTACKDOWN : 243 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 244 [(ARMcallseq_start imm:$amt)]>, 245 Requires<[IsThumb, IsThumb1Only]>; 246 } 247 248 class T1SystemEncoding<bits<8> opc> 249 : T1Encoding<0b101111> { 250 let Inst{9-8} = 0b11; 251 let Inst{7-0} = opc; 252 } 253 254 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>, 255 T1SystemEncoding<0x00>, // A8.6.110 256 Requires<[IsThumb2]>; 257 258 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>, 259 T1SystemEncoding<0x10>, // A8.6.410 260 Requires<[IsThumb2]>; 261 262 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>, 263 T1SystemEncoding<0x20>, // A8.6.408 264 Requires<[IsThumb2]>; 265 266 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>, 267 T1SystemEncoding<0x30>, // A8.6.409 268 Requires<[IsThumb2]>; 269 270 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>, 271 T1SystemEncoding<0x40>, // A8.6.157 272 Requires<[IsThumb2]>; 273 274 // The imm operand $val can be used by a debugger to store more information 275 // about the breakpoint. 276 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", 277 []>, 278 T1Encoding<0b101111> { 279 let Inst{9-8} = 0b10; 280 // A8.6.22 281 bits<8> val; 282 let Inst{7-0} = val; 283 } 284 285 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", 286 []>, T1Encoding<0b101101> { 287 bits<1> end; 288 // A8.6.156 289 let Inst{9-5} = 0b10010; 290 let Inst{4} = 1; 291 let Inst{3} = end; 292 let Inst{2-0} = 0b000; 293 } 294 295 // Change Processor State is a system instruction -- for disassembly only. 296 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 297 NoItinerary, "cps$imod $iflags", []>, 298 T1Misc<0b0110011> { 299 // A8.6.38 & B6.1.1 300 bit imod; 301 bits<3> iflags; 302 303 let Inst{4} = imod; 304 let Inst{3} = 0; 305 let Inst{2-0} = iflags; 306 let DecoderMethod = "DecodeThumbCPS"; 307 } 308 309 // For both thumb1 and thumb2. 310 let isNotDuplicable = 1, isCodeGenOnly = 1 in 311 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 312 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 313 T1Special<{0,0,?,?}> { 314 // A8.6.6 315 bits<3> dst; 316 let Inst{6-3} = 0b1111; // Rm = pc 317 let Inst{2-0} = dst; 318 } 319 320 // ADD <Rd>, sp, #<imm8> 321 // FIXME: This should not be marked as having side effects, and it should be 322 // rematerializable. Clearing the side effect bit causes miscompilations, 323 // probably because the instruction can be moved around. 324 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), 325 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>, 326 T1Encoding<{1,0,1,0,1,?}> { 327 // A6.2 & A8.6.8 328 bits<3> dst; 329 bits<8> imm; 330 let Inst{10-8} = dst; 331 let Inst{7-0} = imm; 332 let DecoderMethod = "DecodeThumbAddSpecialReg"; 333 } 334 335 // ADD sp, sp, #<imm7> 336 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 337 IIC_iALUi, "add", "\t$Rdn, $imm", []>, 338 T1Misc<{0,0,0,0,0,?,?}> { 339 // A6.2.5 & A8.6.8 340 bits<7> imm; 341 let Inst{6-0} = imm; 342 let DecoderMethod = "DecodeThumbAddSPImm"; 343 } 344 345 // SUB sp, sp, #<imm7> 346 // FIXME: The encoding and the ASM string don't match up. 347 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 348 IIC_iALUi, "sub", "\t$Rdn, $imm", []>, 349 T1Misc<{0,0,0,0,1,?,?}> { 350 // A6.2.5 & A8.6.214 351 bits<7> imm; 352 let Inst{6-0} = imm; 353 let DecoderMethod = "DecodeThumbAddSPImm"; 354 } 355 356 def : tInstAlias<"add${p} sp, $imm", 357 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 358 def : tInstAlias<"add${p} sp, sp, $imm", 359 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 360 361 // Can optionally specify SP as a three operand instruction. 362 def : tInstAlias<"add${p} sp, sp, $imm", 363 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; 364 def : tInstAlias<"sub${p} sp, sp, $imm", 365 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; 366 367 // ADD <Rm>, sp 368 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr, 369 "add", "\t$Rdn, $sp, $Rn", []>, 370 T1Special<{0,0,?,?}> { 371 // A8.6.9 Encoding T1 372 bits<4> Rdn; 373 let Inst{7} = Rdn{3}; 374 let Inst{6-3} = 0b1101; 375 let Inst{2-0} = Rdn{2-0}; 376 let DecoderMethod = "DecodeThumbAddSPReg"; 377 } 378 379 // ADD sp, <Rm> 380 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr, 381 "add", "\t$Rdn, $Rm", []>, 382 T1Special<{0,0,?,?}> { 383 // A8.6.9 Encoding T2 384 bits<4> Rm; 385 let Inst{7} = 1; 386 let Inst{6-3} = Rm; 387 let Inst{2-0} = 0b101; 388 let DecoderMethod = "DecodeThumbAddSPReg"; 389 } 390 391 //===----------------------------------------------------------------------===// 392 // Control Flow Instructions. 393 // 394 395 // Indirect branches 396 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 397 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 398 T1Special<{1,1,0,?}> { 399 // A6.2.3 & A8.6.25 400 bits<4> Rm; 401 let Inst{6-3} = Rm; 402 let Inst{2-0} = 0b000; 403 let Unpredictable{2-0} = 0b111; 404 } 405 } 406 407 let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 408 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 409 [(ARMretflag)], (tBX LR, pred:$p)>; 410 411 // Alternative return instruction used by vararg functions. 412 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 413 2, IIC_Br, [], 414 (tBX GPR:$Rm, pred:$p)>; 415 } 416 417 // All calls clobber the non-callee saved registers. SP is marked as a use to 418 // prevent stack-pointer assignments that appear immediately before calls from 419 // potentially appearing dead. 420 let isCall = 1, 421 Defs = [LR], Uses = [SP] in { 422 // Also used for Thumb2 423 def tBL : TIx2<0b11110, 0b11, 1, 424 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br, 425 "bl${p}\t$func", 426 [(ARMtcall tglobaladdr:$func)]>, 427 Requires<[IsThumb]> { 428 bits<24> func; 429 let Inst{26} = func{23}; 430 let Inst{25-16} = func{20-11}; 431 let Inst{13} = func{22}; 432 let Inst{11} = func{21}; 433 let Inst{10-0} = func{10-0}; 434 } 435 436 // ARMv5T and above, also used for Thumb2 437 def tBLXi : TIx2<0b11110, 0b11, 0, 438 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br, 439 "blx${p}\t$func", 440 [(ARMcall tglobaladdr:$func)]>, 441 Requires<[IsThumb, HasV5T]> { 442 bits<24> func; 443 let Inst{26} = func{23}; 444 let Inst{25-16} = func{20-11}; 445 let Inst{13} = func{22}; 446 let Inst{11} = func{21}; 447 let Inst{10-1} = func{10-1}; 448 let Inst{0} = 0; // func{0} is assumed zero 449 } 450 451 // Also used for Thumb2 452 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br, 453 "blx${p}\t$func", 454 [(ARMtcall GPR:$func)]>, 455 Requires<[IsThumb, HasV5T]>, 456 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24; 457 bits<4> func; 458 let Inst{6-3} = func; 459 let Inst{2-0} = 0b000; 460 } 461 462 // ARMv4T 463 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func), 464 4, IIC_Br, 465 [(ARMcall_nolink tGPR:$func)]>, 466 Requires<[IsThumb, IsThumb1Only]>; 467 } 468 469 let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 470 let isPredicable = 1 in 471 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br, 472 "b", "\t$target", [(br bb:$target)]>, 473 T1Encoding<{1,1,1,0,0,?}> { 474 bits<11> target; 475 let Inst{10-0} = target; 476 } 477 478 // Far jump 479 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 480 // the clobber of LR. 481 let Defs = [LR] in 482 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p), 483 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>; 484 485 def tBR_JTr : tPseudoInst<(outs), 486 (ins tGPR:$target, i32imm:$jt, i32imm:$id), 487 0, IIC_Br, 488 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> { 489 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 490 } 491 } 492 493 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 494 // a two-value operand where a dag node expects two operands. :( 495 let isBranch = 1, isTerminator = 1 in 496 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br, 497 "b${p}\t$target", 498 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 499 T1BranchCond<{1,1,0,1}> { 500 bits<4> p; 501 bits<8> target; 502 let Inst{11-8} = p; 503 let Inst{7-0} = target; 504 } 505 506 // Tail calls 507 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 508 // IOS versions. 509 let Uses = [SP] in { 510 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst), 511 4, IIC_Br, [], 512 (tBX GPR:$dst, (ops 14, zero_reg))>, 513 Requires<[IsThumb]>; 514 } 515 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls 516 // on IOS), so it's in ARMInstrThumb2.td. 517 // Non-IOS version: 518 let Uses = [SP] in { 519 def tTAILJMPdND : tPseudoExpand<(outs), 520 (ins t_brtarget:$dst, pred:$p), 521 4, IIC_Br, [], 522 (tB t_brtarget:$dst, pred:$p)>, 523 Requires<[IsThumb, IsNotIOS]>; 524 } 525 } 526 527 528 // A8.6.218 Supervisor Call (Software Interrupt) 529 // A8.6.16 B: Encoding T1 530 // If Inst{11-8} == 0b1111 then SEE SVC 531 let isCall = 1, Uses = [SP] in 532 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, 533 "svc", "\t$imm", []>, Encoding16 { 534 bits<8> imm; 535 let Inst{15-12} = 0b1101; 536 let Inst{11-8} = 0b1111; 537 let Inst{7-0} = imm; 538 } 539 540 // The assembler uses 0xDEFE for a trap instruction. 541 let isBarrier = 1, isTerminator = 1 in 542 def tTRAP : TI<(outs), (ins), IIC_Br, 543 "trap", [(trap)]>, Encoding16 { 544 let Inst = 0xdefe; 545 } 546 547 //===----------------------------------------------------------------------===// 548 // Load Store Instructions. 549 // 550 551 // Loads: reg/reg and reg/imm5 552 let canFoldAsLoad = 1, isReMaterializable = 1 in 553 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 554 Operand AddrMode_r, Operand AddrMode_i, 555 AddrMode am, InstrItinClass itin_r, 556 InstrItinClass itin_i, string asm, 557 PatFrag opnode> { 558 def r : // reg/reg 559 T1pILdStEncode<reg_opc, 560 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 561 am, itin_r, asm, "\t$Rt, $addr", 562 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 563 def i : // reg/imm5 564 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 565 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 566 am, itin_i, asm, "\t$Rt, $addr", 567 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 568 } 569 // Stores: reg/reg and reg/imm5 570 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 571 Operand AddrMode_r, Operand AddrMode_i, 572 AddrMode am, InstrItinClass itin_r, 573 InstrItinClass itin_i, string asm, 574 PatFrag opnode> { 575 def r : // reg/reg 576 T1pILdStEncode<reg_opc, 577 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 578 am, itin_r, asm, "\t$Rt, $addr", 579 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 580 def i : // reg/imm5 581 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 582 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 583 am, itin_i, asm, "\t$Rt, $addr", 584 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 585 } 586 587 // A8.6.57 & A8.6.60 588 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4, 589 t_addrmode_is4, AddrModeT1_4, 590 IIC_iLoad_r, IIC_iLoad_i, "ldr", 591 UnOpFrag<(load node:$Src)>>; 592 593 // A8.6.64 & A8.6.61 594 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1, 595 t_addrmode_is1, AddrModeT1_1, 596 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 597 UnOpFrag<(zextloadi8 node:$Src)>>; 598 599 // A8.6.76 & A8.6.73 600 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2, 601 t_addrmode_is2, AddrModeT1_2, 602 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 603 UnOpFrag<(zextloadi16 node:$Src)>>; 604 605 let AddedComplexity = 10 in 606 def tLDRSB : // A8.6.80 607 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 608 AddrModeT1_1, IIC_iLoad_bh_r, 609 "ldrsb", "\t$Rt, $addr", 610 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>; 611 612 let AddedComplexity = 10 in 613 def tLDRSH : // A8.6.84 614 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 615 AddrModeT1_2, IIC_iLoad_bh_r, 616 "ldrsh", "\t$Rt, $addr", 617 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>; 618 619 let canFoldAsLoad = 1 in 620 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 621 "ldr", "\t$Rt, $addr", 622 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 623 T1LdStSP<{1,?,?}> { 624 bits<3> Rt; 625 bits<8> addr; 626 let Inst{10-8} = Rt; 627 let Inst{7-0} = addr; 628 } 629 630 // Load tconstpool 631 // FIXME: Use ldr.n to work around a darwin assembler bug. 632 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in 633 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 634 "ldr", ".n\t$Rt, $addr", 635 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 636 T1Encoding<{0,1,0,0,1,?}> { 637 // A6.2 & A8.6.59 638 bits<3> Rt; 639 bits<8> addr; 640 let Inst{10-8} = Rt; 641 let Inst{7-0} = addr; 642 } 643 644 // FIXME: Remove this entry when the above ldr.n workaround is fixed. 645 // For assembly/disassembly use only. 646 def tLDRpciASM : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 647 "ldr", "\t$Rt, $addr", []>, 648 T1Encoding<{0,1,0,0,1,?}> { 649 // A6.2 & A8.6.59 650 bits<3> Rt; 651 bits<8> addr; 652 let Inst{10-8} = Rt; 653 let Inst{7-0} = addr; 654 } 655 656 // A8.6.194 & A8.6.192 657 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4, 658 t_addrmode_is4, AddrModeT1_4, 659 IIC_iStore_r, IIC_iStore_i, "str", 660 BinOpFrag<(store node:$LHS, node:$RHS)>>; 661 662 // A8.6.197 & A8.6.195 663 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1, 664 t_addrmode_is1, AddrModeT1_1, 665 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 666 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 667 668 // A8.6.207 & A8.6.205 669 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2, 670 t_addrmode_is2, AddrModeT1_2, 671 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 672 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 673 674 675 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 676 "str", "\t$Rt, $addr", 677 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 678 T1LdStSP<{0,?,?}> { 679 bits<3> Rt; 680 bits<8> addr; 681 let Inst{10-8} = Rt; 682 let Inst{7-0} = addr; 683 } 684 685 //===----------------------------------------------------------------------===// 686 // Load / store multiple Instructions. 687 // 688 689 // These require base address to be written back or one of the loaded regs. 690 let neverHasSideEffects = 1 in { 691 692 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 693 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 694 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> { 695 bits<3> Rn; 696 bits<8> regs; 697 let Inst{10-8} = Rn; 698 let Inst{7-0} = regs; 699 } 700 701 // Writeback version is just a pseudo, as there's no encoding difference. 702 // Writeback happens iff the base register is not in the destination register 703 // list. 704 def tLDMIA_UPD : 705 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 706 "$Rn = $wb", IIC_iLoad_mu>, 707 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> { 708 let Size = 2; 709 let OutOperandList = (outs GPR:$wb); 710 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); 711 let Pattern = []; 712 let isCodeGenOnly = 1; 713 let isPseudo = 1; 714 list<Predicate> Predicates = [IsThumb]; 715 } 716 717 // There is no non-writeback version of STM for Thumb. 718 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 719 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb), 720 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 721 AddrModeNone, 2, IIC_iStore_mu, 722 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>, 723 T1Encoding<{1,1,0,0,0,?}> { 724 bits<3> Rn; 725 bits<8> regs; 726 let Inst{10-8} = Rn; 727 let Inst{7-0} = regs; 728 } 729 730 } // neverHasSideEffects 731 732 def : InstAlias<"ldm${p} $Rn!, $regs", 733 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>, 734 Requires<[IsThumb, IsThumb1Only]>; 735 736 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 737 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 738 IIC_iPop, 739 "pop${p}\t$regs", []>, 740 T1Misc<{1,1,0,?,?,?,?}> { 741 bits<16> regs; 742 let Inst{8} = regs{15}; 743 let Inst{7-0} = regs{7-0}; 744 } 745 746 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 747 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 748 IIC_iStore_m, 749 "push${p}\t$regs", []>, 750 T1Misc<{0,1,0,?,?,?,?}> { 751 bits<16> regs; 752 let Inst{8} = regs{14}; 753 let Inst{7-0} = regs{7-0}; 754 } 755 756 //===----------------------------------------------------------------------===// 757 // Arithmetic Instructions. 758 // 759 760 // Helper classes for encoding T1pI patterns: 761 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 762 string opc, string asm, list<dag> pattern> 763 : T1pI<oops, iops, itin, opc, asm, pattern>, 764 T1DataProcessing<opA> { 765 bits<3> Rm; 766 bits<3> Rn; 767 let Inst{5-3} = Rm; 768 let Inst{2-0} = Rn; 769 } 770 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 771 string opc, string asm, list<dag> pattern> 772 : T1pI<oops, iops, itin, opc, asm, pattern>, 773 T1Misc<opA> { 774 bits<3> Rm; 775 bits<3> Rd; 776 let Inst{5-3} = Rm; 777 let Inst{2-0} = Rd; 778 } 779 780 // Helper classes for encoding T1sI patterns: 781 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 782 string opc, string asm, list<dag> pattern> 783 : T1sI<oops, iops, itin, opc, asm, pattern>, 784 T1DataProcessing<opA> { 785 bits<3> Rd; 786 bits<3> Rn; 787 let Inst{5-3} = Rn; 788 let Inst{2-0} = Rd; 789 } 790 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 791 string opc, string asm, list<dag> pattern> 792 : T1sI<oops, iops, itin, opc, asm, pattern>, 793 T1General<opA> { 794 bits<3> Rm; 795 bits<3> Rn; 796 bits<3> Rd; 797 let Inst{8-6} = Rm; 798 let Inst{5-3} = Rn; 799 let Inst{2-0} = Rd; 800 } 801 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 802 string opc, string asm, list<dag> pattern> 803 : T1sI<oops, iops, itin, opc, asm, pattern>, 804 T1General<opA> { 805 bits<3> Rd; 806 bits<3> Rm; 807 let Inst{5-3} = Rm; 808 let Inst{2-0} = Rd; 809 } 810 811 // Helper classes for encoding T1sIt patterns: 812 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 813 string opc, string asm, list<dag> pattern> 814 : T1sIt<oops, iops, itin, opc, asm, pattern>, 815 T1DataProcessing<opA> { 816 bits<3> Rdn; 817 bits<3> Rm; 818 let Inst{5-3} = Rm; 819 let Inst{2-0} = Rdn; 820 } 821 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 822 string opc, string asm, list<dag> pattern> 823 : T1sIt<oops, iops, itin, opc, asm, pattern>, 824 T1General<opA> { 825 bits<3> Rdn; 826 bits<8> imm8; 827 let Inst{10-8} = Rdn; 828 let Inst{7-0} = imm8; 829 } 830 831 // Add with carry register 832 let isCommutable = 1, Uses = [CPSR] in 833 def tADC : // A8.6.2 834 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 835 "adc", "\t$Rdn, $Rm", 836 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>; 837 838 // Add immediate 839 def tADDi3 : // A8.6.4 T1 840 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 841 IIC_iALUi, 842 "add", "\t$Rd, $Rm, $imm3", 843 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> { 844 bits<3> imm3; 845 let Inst{8-6} = imm3; 846 } 847 848 def tADDi8 : // A8.6.4 T2 849 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), 850 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 851 "add", "\t$Rdn, $imm8", 852 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>; 853 854 // Add register 855 let isCommutable = 1 in 856 def tADDrr : // A8.6.6 T1 857 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 858 IIC_iALUr, 859 "add", "\t$Rd, $Rn, $Rm", 860 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>; 861 862 let neverHasSideEffects = 1 in 863 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 864 "add", "\t$Rdn, $Rm", []>, 865 T1Special<{0,0,?,?}> { 866 // A8.6.6 T2 867 bits<4> Rdn; 868 bits<4> Rm; 869 let Inst{7} = Rdn{3}; 870 let Inst{6-3} = Rm; 871 let Inst{2-0} = Rdn{2-0}; 872 } 873 874 // AND register 875 let isCommutable = 1 in 876 def tAND : // A8.6.12 877 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 878 IIC_iBITr, 879 "and", "\t$Rdn, $Rm", 880 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>; 881 882 // ASR immediate 883 def tASRri : // A8.6.14 884 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 885 IIC_iMOVsi, 886 "asr", "\t$Rd, $Rm, $imm5", 887 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> { 888 bits<5> imm5; 889 let Inst{10-6} = imm5; 890 } 891 892 // ASR register 893 def tASRrr : // A8.6.15 894 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 895 IIC_iMOVsr, 896 "asr", "\t$Rdn, $Rm", 897 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>; 898 899 // BIC register 900 def tBIC : // A8.6.20 901 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 902 IIC_iBITr, 903 "bic", "\t$Rdn, $Rm", 904 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>; 905 906 // CMN register 907 let isCompare = 1, Defs = [CPSR] in { 908 //FIXME: Disable CMN, as CCodes are backwards from compare expectations 909 // Compare-to-zero still works out, just not the relationals 910 //def tCMN : // A8.6.33 911 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 912 // IIC_iCMPr, 913 // "cmn", "\t$lhs, $rhs", 914 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 915 916 def tCMNz : // A8.6.33 917 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 918 IIC_iCMPr, 919 "cmn", "\t$Rn, $Rm", 920 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>; 921 922 } // isCompare = 1, Defs = [CPSR] 923 924 // CMP immediate 925 let isCompare = 1, Defs = [CPSR] in { 926 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 927 "cmp", "\t$Rn, $imm8", 928 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 929 T1General<{1,0,1,?,?}> { 930 // A8.6.35 931 bits<3> Rn; 932 bits<8> imm8; 933 let Inst{10-8} = Rn; 934 let Inst{7-0} = imm8; 935 } 936 937 // CMP register 938 def tCMPr : // A8.6.36 T1 939 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 940 IIC_iCMPr, 941 "cmp", "\t$Rn, $Rm", 942 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>; 943 944 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 945 "cmp", "\t$Rn, $Rm", []>, 946 T1Special<{0,1,?,?}> { 947 // A8.6.36 T2 948 bits<4> Rm; 949 bits<4> Rn; 950 let Inst{7} = Rn{3}; 951 let Inst{6-3} = Rm; 952 let Inst{2-0} = Rn{2-0}; 953 } 954 } // isCompare = 1, Defs = [CPSR] 955 956 957 // XOR register 958 let isCommutable = 1 in 959 def tEOR : // A8.6.45 960 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 961 IIC_iBITr, 962 "eor", "\t$Rdn, $Rm", 963 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>; 964 965 // LSL immediate 966 def tLSLri : // A8.6.88 967 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5), 968 IIC_iMOVsi, 969 "lsl", "\t$Rd, $Rm, $imm5", 970 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> { 971 bits<5> imm5; 972 let Inst{10-6} = imm5; 973 } 974 975 // LSL register 976 def tLSLrr : // A8.6.89 977 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 978 IIC_iMOVsr, 979 "lsl", "\t$Rdn, $Rm", 980 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>; 981 982 // LSR immediate 983 def tLSRri : // A8.6.90 984 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 985 IIC_iMOVsi, 986 "lsr", "\t$Rd, $Rm, $imm5", 987 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> { 988 bits<5> imm5; 989 let Inst{10-6} = imm5; 990 } 991 992 // LSR register 993 def tLSRrr : // A8.6.91 994 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 995 IIC_iMOVsr, 996 "lsr", "\t$Rdn, $Rm", 997 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>; 998 999 // Move register 1000 let isMoveImm = 1 in 1001 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 1002 "mov", "\t$Rd, $imm8", 1003 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1004 T1General<{1,0,0,?,?}> { 1005 // A8.6.96 1006 bits<3> Rd; 1007 bits<8> imm8; 1008 let Inst{10-8} = Rd; 1009 let Inst{7-0} = imm8; 1010 } 1011 // Because we have an explicit tMOVSr below, we need an alias to handle 1012 // the immediate "movs" form here. Blech. 1013 def : tInstAlias <"movs $Rdn, $imm", 1014 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>; 1015 1016 // A7-73: MOV(2) - mov setting flag. 1017 1018 let neverHasSideEffects = 1 in { 1019 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1020 2, IIC_iMOVr, 1021 "mov", "\t$Rd, $Rm", "", []>, 1022 T1Special<{1,0,?,?}> { 1023 // A8.6.97 1024 bits<4> Rd; 1025 bits<4> Rm; 1026 let Inst{7} = Rd{3}; 1027 let Inst{6-3} = Rm; 1028 let Inst{2-0} = Rd{2-0}; 1029 } 1030 let Defs = [CPSR] in 1031 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1032 "movs\t$Rd, $Rm", []>, Encoding16 { 1033 // A8.6.97 1034 bits<3> Rd; 1035 bits<3> Rm; 1036 let Inst{15-6} = 0b0000000000; 1037 let Inst{5-3} = Rm; 1038 let Inst{2-0} = Rd; 1039 } 1040 } // neverHasSideEffects 1041 1042 // Multiply register 1043 let isCommutable = 1 in 1044 def tMUL : // A8.6.105 T1 1045 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, 1046 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", 1047 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>, 1048 T1DataProcessing<0b1101> { 1049 bits<3> Rd; 1050 bits<3> Rn; 1051 let Inst{5-3} = Rn; 1052 let Inst{2-0} = Rd; 1053 let AsmMatchConverter = "cvtThumbMultiply"; 1054 } 1055 1056 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, 1057 pred:$p)>; 1058 1059 // Move inverse register 1060 def tMVN : // A8.6.107 1061 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1062 "mvn", "\t$Rd, $Rn", 1063 [(set tGPR:$Rd, (not tGPR:$Rn))]>; 1064 1065 // Bitwise or register 1066 let isCommutable = 1 in 1067 def tORR : // A8.6.114 1068 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1069 IIC_iBITr, 1070 "orr", "\t$Rdn, $Rm", 1071 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>; 1072 1073 // Swaps 1074 def tREV : // A8.6.134 1075 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1076 IIC_iUNAr, 1077 "rev", "\t$Rd, $Rm", 1078 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1079 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1080 1081 def tREV16 : // A8.6.135 1082 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1083 IIC_iUNAr, 1084 "rev16", "\t$Rd, $Rm", 1085 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1086 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1087 1088 def tREVSH : // A8.6.136 1089 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1090 IIC_iUNAr, 1091 "revsh", "\t$Rd, $Rm", 1092 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1093 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1094 1095 // Rotate right register 1096 def tROR : // A8.6.139 1097 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1098 IIC_iMOVsr, 1099 "ror", "\t$Rdn, $Rm", 1100 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>; 1101 1102 // Negate register 1103 def tRSB : // A8.6.141 1104 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1105 IIC_iALUi, 1106 "rsb", "\t$Rd, $Rn, #0", 1107 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>; 1108 1109 // Subtract with carry register 1110 let Uses = [CPSR] in 1111 def tSBC : // A8.6.151 1112 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1113 IIC_iALUr, 1114 "sbc", "\t$Rdn, $Rm", 1115 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>; 1116 1117 // Subtract immediate 1118 def tSUBi3 : // A8.6.210 T1 1119 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1120 IIC_iALUi, 1121 "sub", "\t$Rd, $Rm, $imm3", 1122 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> { 1123 bits<3> imm3; 1124 let Inst{8-6} = imm3; 1125 } 1126 1127 def tSUBi8 : // A8.6.210 T2 1128 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), 1129 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 1130 "sub", "\t$Rdn, $imm8", 1131 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>; 1132 1133 // Subtract register 1134 def tSUBrr : // A8.6.212 1135 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1136 IIC_iALUr, 1137 "sub", "\t$Rd, $Rn, $Rm", 1138 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>; 1139 1140 // Sign-extend byte 1141 def tSXTB : // A8.6.222 1142 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1143 IIC_iUNAr, 1144 "sxtb", "\t$Rd, $Rm", 1145 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1146 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1147 1148 // Sign-extend short 1149 def tSXTH : // A8.6.224 1150 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1151 IIC_iUNAr, 1152 "sxth", "\t$Rd, $Rm", 1153 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1154 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1155 1156 // Test 1157 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1158 def tTST : // A8.6.230 1159 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1160 "tst", "\t$Rn, $Rm", 1161 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>; 1162 1163 // Zero-extend byte 1164 def tUXTB : // A8.6.262 1165 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1166 IIC_iUNAr, 1167 "uxtb", "\t$Rd, $Rm", 1168 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1169 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1170 1171 // Zero-extend short 1172 def tUXTH : // A8.6.264 1173 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1174 IIC_iUNAr, 1175 "uxth", "\t$Rd, $Rm", 1176 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1177 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1178 1179 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1180 // Expanded after instruction selection into a branch sequence. 1181 let usesCustomInserter = 1 in // Expanded after instruction selection. 1182 def tMOVCCr_pseudo : 1183 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), 1184 NoItinerary, 1185 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; 1186 1187 // tLEApcrel - Load a pc-relative address into a register without offending the 1188 // assembler. 1189 1190 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1191 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>, 1192 T1Encoding<{1,0,1,0,0,?}> { 1193 bits<3> Rd; 1194 bits<8> addr; 1195 let Inst{10-8} = Rd; 1196 let Inst{7-0} = addr; 1197 let DecoderMethod = "DecodeThumbAddSpecialReg"; 1198 } 1199 1200 let neverHasSideEffects = 1, isReMaterializable = 1 in 1201 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1202 2, IIC_iALUi, []>; 1203 1204 let hasSideEffects = 1 in 1205 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1206 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1207 2, IIC_iALUi, []>; 1208 1209 //===----------------------------------------------------------------------===// 1210 // TLS Instructions 1211 // 1212 1213 // __aeabi_read_tp preserves the registers r1-r3. 1214 // This is a pseudo inst so that we can get the encoding right, 1215 // complete with fixup for the aeabi_read_tp function. 1216 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1217 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1218 [(set R0, ARMthread_pointer)]>; 1219 1220 //===----------------------------------------------------------------------===// 1221 // SJLJ Exception handling intrinsics 1222 // 1223 1224 // eh_sjlj_setjmp() is an instruction sequence to store the return address and 1225 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1226 // from some other function to get here, and we're using the stack frame for the 1227 // containing function to save/restore registers, we can't keep anything live in 1228 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1229 // tromped upon when we get here from a longjmp(). We force everything out of 1230 // registers except for our own input by listing the relevant registers in 1231 // Defs. By doing so, we also cause the prologue/epilogue code to actively 1232 // preserve all of the callee-saved resgisters, which is exactly what we want. 1233 // $val is a scratch register for our use. 1234 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1235 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1236 usesCustomInserter = 1 in 1237 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1238 AddrModeNone, 0, NoItinerary, "","", 1239 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1240 1241 // FIXME: Non-IOS version(s) 1242 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1243 Defs = [ R7, LR, SP ] in 1244 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1245 AddrModeNone, 0, IndexModeNone, 1246 Pseudo, NoItinerary, "", "", 1247 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1248 Requires<[IsThumb, IsIOS]>; 1249 1250 //===----------------------------------------------------------------------===// 1251 // Non-Instruction Patterns 1252 // 1253 1254 // Comparisons 1255 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1256 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1257 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1258 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1259 1260 // Add with carry 1261 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1262 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1263 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1264 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1265 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1266 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1267 1268 // Subtract with carry 1269 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1270 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1271 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1272 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1273 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1274 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1275 1276 // ConstantPool, GlobalAddress 1277 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>; 1278 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1279 1280 // JumpTable 1281 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1282 (tLEApcrelJT tjumptable:$dst, imm:$id)>; 1283 1284 // Direct calls 1285 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 1286 Requires<[IsThumb]>; 1287 1288 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 1289 Requires<[IsThumb, HasV5T]>; 1290 1291 // Indirect calls to ARM routines 1292 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 1293 Requires<[IsThumb, HasV5T]>; 1294 1295 // zextload i1 -> zextload i8 1296 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr), 1297 (tLDRBr t_addrmode_rrs1:$addr)>; 1298 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1299 (tLDRBi t_addrmode_is1:$addr)>; 1300 1301 // extload -> zextload 1302 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1303 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1304 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1305 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1306 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>; 1307 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1308 1309 // If it's impossible to use [r,r] address mode for sextload, select to 1310 // ldr{b|h} + sxt{b|h} instead. 1311 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1312 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1313 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1314 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1315 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>, 1316 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1317 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1318 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1319 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1320 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1321 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>, 1322 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1323 1324 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1325 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>; 1326 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1327 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1328 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1329 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>; 1330 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1331 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1332 1333 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src), 1334 (tLDRBi t_addrmode_is1:$src)>; 1335 def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src), 1336 (tLDRBr t_addrmode_rrs1:$src)>; 1337 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src), 1338 (tLDRHi t_addrmode_is2:$src)>; 1339 def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src), 1340 (tLDRHr t_addrmode_rrs2:$src)>; 1341 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src), 1342 (tLDRi t_addrmode_is4:$src)>; 1343 def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src), 1344 (tLDRr t_addrmode_rrs4:$src)>; 1345 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val), 1346 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>; 1347 def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val), 1348 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>; 1349 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val), 1350 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>; 1351 def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val), 1352 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>; 1353 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val), 1354 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>; 1355 def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val), 1356 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>; 1357 1358 // Large immediate handling. 1359 1360 // Two piece imms. 1361 def : T1Pat<(i32 thumb_immshifted:$src), 1362 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1363 (thumb_immshifted_shamt imm:$src))>; 1364 1365 def : T1Pat<(i32 imm0_255_comp:$src), 1366 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1367 1368 // Pseudo instruction that combines ldr from constpool and add pc. This should 1369 // be expanded into two instructions late to allow if-conversion and 1370 // scheduling. 1371 let isReMaterializable = 1 in 1372 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1373 NoItinerary, 1374 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1375 imm:$cp))]>, 1376 Requires<[IsThumb, IsThumb1Only]>; 1377 1378 // Pseudo-instruction for merged POP and return. 1379 // FIXME: remove when we have a way to marking a MI with these properties. 1380 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1381 hasExtraDefRegAllocReq = 1 in 1382 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1383 2, IIC_iPop_Br, [], 1384 (tPOP pred:$p, reglist:$regs)>; 1385 1386 // Indirect branch using "mov pc, $Rm" 1387 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1388 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1389 2, IIC_Br, [(brind GPR:$Rm)], 1390 (tMOVr PC, GPR:$Rm, pred:$p)>; 1391 } 1392 1393 1394 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00 1395 // encoding is available on ARMv6K, but we don't differentiate that finely. 1396 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>; 1397 1398 1399 // For round-trip assembly/disassembly, we have to handle a CPS instruction 1400 // without any iflags. That's not, strictly speaking, valid syntax, but it's 1401 // a useful extension and assembles to defined behaviour (the insn does 1402 // nothing). 1403 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1404 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1405 1406 // "neg" is and alias for "rsb rd, rn, #0" 1407 def : tInstAlias<"neg${s}${p} $Rd, $Rm", 1408 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>; 1409 1410 1411 // Implied destination operand forms for shifts. 1412 def : tInstAlias<"lsl${s}${p} $Rdm, $imm", 1413 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>; 1414 def : tInstAlias<"lsr${s}${p} $Rdm, $imm", 1415 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1416 def : tInstAlias<"asr${s}${p} $Rdm, $imm", 1417 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1418
