1 def SDTHexagonFCONST32 : SDTypeProfile<1, 1, [ 2 SDTCisVT<0, f32>, 3 SDTCisPtrTy<1>]>; 4 def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32", SDTHexagonFCONST32>; 5 6 let isReMaterializable = 1, isMoveImm = 1 in 7 def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global), 8 "$dst = CONST32(#$global)", 9 [(set (f32 IntRegs:$dst), 10 (HexagonFCONST32 tglobaladdr:$global))]>, 11 Requires<[HasV5T]>; 12 13 let isReMaterializable = 1, isMoveImm = 1 in 14 def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1), 15 "$dst = CONST64(#$src1)", 16 [(set DoubleRegs:$dst, fpimm:$src1)]>, 17 Requires<[HasV5T]>; 18 19 let isReMaterializable = 1, isMoveImm = 1 in 20 def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1), 21 "$dst = CONST32(#$src1)", 22 [(set IntRegs:$dst, fpimm:$src1)]>, 23 Requires<[HasV5T]>; 24 25 // Transfer immediate float. 26 // Only works with single precision fp value. 27 // For double precision, use CONST64_float_real, as 64bit transfer 28 // can only hold 40-bit values - 32 from const ext + 8 bit immediate. 29 let isMoveImm = 1, isReMaterializable = 1, isPredicable = 1 in 30 def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32imm:$src1), 31 "$dst = ##$src1", 32 [(set IntRegs:$dst, fpimm:$src1)]>, 33 Requires<[HasV5T]>; 34 35 def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst), 36 (ins PredRegs:$src1, f32imm:$src2), 37 "if ($src1) $dst = ##$src2", 38 []>, 39 Requires<[HasV5T]>; 40 41 let isPredicated = 1 in 42 def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst), 43 (ins PredRegs:$src1, f32imm:$src2), 44 "if (!$src1) $dst = ##$src2", 45 []>, 46 Requires<[HasV5T]>; 47 48 // Convert single precision to double precision and vice-versa. 49 def CONVERT_sf2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src), 50 "$dst = convert_sf2df($src)", 51 [(set DoubleRegs:$dst, (fextend IntRegs:$src))]>, 52 Requires<[HasV5T]>; 53 54 def CONVERT_df2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src), 55 "$dst = convert_df2sf($src)", 56 [(set IntRegs:$dst, (fround DoubleRegs:$src))]>, 57 Requires<[HasV5T]>; 58 59 60 // Load. 61 def LDrid_f : LDInst<(outs DoubleRegs:$dst), 62 (ins MEMri:$addr), 63 "$dst = memd($addr)", 64 [(set DoubleRegs:$dst, (f64 (load ADDRriS11_3:$addr)))]>, 65 Requires<[HasV5T]>; 66 67 68 let AddedComplexity = 20 in 69 def LDrid_indexed_f : LDInst<(outs DoubleRegs:$dst), 70 (ins IntRegs:$src1, s11_3Imm:$offset), 71 "$dst = memd($src1+#$offset)", 72 [(set DoubleRegs:$dst, (f64 (load (add IntRegs:$src1, 73 s11_3ImmPred:$offset))))]>, 74 Requires<[HasV5T]>; 75 76 def LDriw_f : LDInst<(outs IntRegs:$dst), 77 (ins MEMri:$addr), "$dst = memw($addr)", 78 [(set IntRegs:$dst, (f32 (load ADDRriS11_2:$addr)))]>, 79 Requires<[HasV5T]>; 80 81 82 let AddedComplexity = 20 in 83 def LDriw_indexed_f : LDInst<(outs IntRegs:$dst), 84 (ins IntRegs:$src1, s11_2Imm:$offset), 85 "$dst = memw($src1+#$offset)", 86 [(set IntRegs:$dst, (f32 (load (add IntRegs:$src1, 87 s11_2ImmPred:$offset))))]>, 88 Requires<[HasV5T]>; 89 90 // Store. 91 def STriw_f : STInst<(outs), 92 (ins MEMri:$addr, IntRegs:$src1), 93 "memw($addr) = $src1", 94 [(store (f32 IntRegs:$src1), ADDRriS11_2:$addr)]>, 95 Requires<[HasV5T]>; 96 97 let AddedComplexity = 10 in 98 def STriw_indexed_f : STInst<(outs), 99 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3), 100 "memw($src1+#$src2) = $src3", 101 [(store (f32 IntRegs:$src3), 102 (add IntRegs:$src1, s11_2ImmPred:$src2))]>, 103 Requires<[HasV5T]>; 104 105 def STrid_f : STInst<(outs), 106 (ins MEMri:$addr, DoubleRegs:$src1), 107 "memd($addr) = $src1", 108 [(store (f64 DoubleRegs:$src1), ADDRriS11_2:$addr)]>, 109 Requires<[HasV5T]>; 110 111 // Indexed store double word. 112 let AddedComplexity = 10 in 113 def STrid_indexed_f : STInst<(outs), 114 (ins IntRegs:$src1, s11_3Imm:$src2, DoubleRegs:$src3), 115 "memd($src1+#$src2) = $src3", 116 [(store (f64 DoubleRegs:$src3), 117 (add IntRegs:$src1, s11_3ImmPred:$src2))]>, 118 Requires<[HasV5T]>; 119 120 121 // Add 122 let isCommutable = 1 in 123 def fADD_rr : ALU64_rr<(outs IntRegs:$dst), 124 (ins IntRegs:$src1, IntRegs:$src2), 125 "$dst = sfadd($src1, $src2)", 126 [(set IntRegs:$dst, (fadd IntRegs:$src1, IntRegs:$src2))]>, 127 Requires<[HasV5T]>; 128 129 let isCommutable = 1 in 130 def fADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, 131 DoubleRegs:$src2), 132 "$dst = dfadd($src1, $src2)", 133 [(set DoubleRegs:$dst, (fadd DoubleRegs:$src1, 134 DoubleRegs:$src2))]>, 135 Requires<[HasV5T]>; 136 137 def fSUB_rr : ALU64_rr<(outs IntRegs:$dst), 138 (ins IntRegs:$src1, IntRegs:$src2), 139 "$dst = sfsub($src1, $src2)", 140 [(set IntRegs:$dst, (fsub IntRegs:$src1, IntRegs:$src2))]>, 141 Requires<[HasV5T]>; 142 143 def fSUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, 144 DoubleRegs:$src2), 145 "$dst = dfsub($src1, $src2)", 146 [(set DoubleRegs:$dst, (fsub DoubleRegs:$src1, 147 DoubleRegs:$src2))]>, 148 Requires<[HasV5T]>; 149 150 let isCommutable = 1 in 151 def fMUL_rr : ALU64_rr<(outs IntRegs:$dst), 152 (ins IntRegs:$src1, IntRegs:$src2), 153 "$dst = sfmpy($src1, $src2)", 154 [(set IntRegs:$dst, (fmul IntRegs:$src1, IntRegs:$src2))]>, 155 Requires<[HasV5T]>; 156 157 let isCommutable = 1 in 158 def fMUL64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, 159 DoubleRegs:$src2), 160 "$dst = dfmpy($src1, $src2)", 161 [(set DoubleRegs:$dst, (fmul DoubleRegs:$src1, 162 DoubleRegs:$src2))]>, 163 Requires<[HasV5T]>; 164 165 // Compare. 166 let isCompare = 1 in { 167 multiclass FCMP64_rr<string OpcStr, PatFrag OpNode> { 168 def _rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c), 169 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")), 170 [(set PredRegs:$dst, 171 (OpNode (f64 DoubleRegs:$b), (f64 DoubleRegs:$c)))]>, 172 Requires<[HasV5T]>; 173 } 174 175 multiclass FCMP32_rr<string OpcStr, PatFrag OpNode> { 176 def _rr : ALU64_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 177 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")), 178 [(set PredRegs:$dst, 179 (OpNode (f32 IntRegs:$b), (f32 IntRegs:$c)))]>, 180 Requires<[HasV5T]>; 181 } 182 } 183 184 defm FCMPOEQ64 : FCMP64_rr<"dfcmp.eq", setoeq>; 185 defm FCMPUEQ64 : FCMP64_rr<"dfcmp.eq", setueq>; 186 defm FCMPOGT64 : FCMP64_rr<"dfcmp.gt", setogt>; 187 defm FCMPUGT64 : FCMP64_rr<"dfcmp.gt", setugt>; 188 defm FCMPOGE64 : FCMP64_rr<"dfcmp.ge", setoge>; 189 defm FCMPUGE64 : FCMP64_rr<"dfcmp.ge", setuge>; 190 191 defm FCMPOEQ32 : FCMP32_rr<"sfcmp.eq", setoeq>; 192 defm FCMPUEQ32 : FCMP32_rr<"sfcmp.eq", setueq>; 193 defm FCMPOGT32 : FCMP32_rr<"sfcmp.gt", setogt>; 194 defm FCMPUGT32 : FCMP32_rr<"sfcmp.gt", setugt>; 195 defm FCMPOGE32 : FCMP32_rr<"sfcmp.ge", setoge>; 196 defm FCMPUGE32 : FCMP32_rr<"sfcmp.ge", setuge>; 197 198 // olt. 199 def : Pat <(i1 (setolt (f32 IntRegs:$src1), (f32 IntRegs:$src2))), 200 (i1 (FCMPOGT32_rr IntRegs:$src2, IntRegs:$src1))>, 201 Requires<[HasV5T]>; 202 203 def : Pat <(i1 (setolt (f32 IntRegs:$src1), (fpimm:$src2))), 204 (i1 (FCMPOGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>, 205 Requires<[HasV5T]>; 206 207 def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))), 208 (i1 (FCMPOGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>, 209 Requires<[HasV5T]>; 210 211 def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (fpimm:$src2))), 212 (i1 (FCMPOGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)), 213 (f64 DoubleRegs:$src1)))>, 214 Requires<[HasV5T]>; 215 216 // gt. 217 def : Pat <(i1 (setugt (f64 DoubleRegs:$src1), (fpimm:$src2))), 218 (i1 (FCMPUGT64_rr (f64 DoubleRegs:$src1), 219 (f64 (CONST64_Float_Real fpimm:$src2))))>, 220 Requires<[HasV5T]>; 221 222 def : Pat <(i1 (setugt (f32 IntRegs:$src1), (fpimm:$src2))), 223 (i1 (FCMPUGT32_rr (f32 IntRegs:$src1), (f32 (TFRI_f fpimm:$src2))))>, 224 Requires<[HasV5T]>; 225 226 // ult. 227 def : Pat <(i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))), 228 (i1 (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1))>, 229 Requires<[HasV5T]>; 230 231 def : Pat <(i1 (setult (f32 IntRegs:$src1), (fpimm:$src2))), 232 (i1 (FCMPUGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>, 233 Requires<[HasV5T]>; 234 235 def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))), 236 (i1 (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>, 237 Requires<[HasV5T]>; 238 239 def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (fpimm:$src2))), 240 (i1 (FCMPUGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)), 241 (f64 DoubleRegs:$src1)))>, 242 Requires<[HasV5T]>; 243 244 // le. 245 // rs <= rt -> rt >= rs. 246 def : Pat<(i1 (setole (f32 IntRegs:$src1), (f32 IntRegs:$src2))), 247 (i1 (FCMPOGE32_rr IntRegs:$src2, IntRegs:$src1))>, 248 Requires<[HasV5T]>; 249 250 def : Pat<(i1 (setole (f32 IntRegs:$src1), (fpimm:$src2))), 251 (i1 (FCMPOGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>, 252 Requires<[HasV5T]>; 253 254 255 // Rss <= Rtt -> Rtt >= Rss. 256 def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))), 257 (i1 (FCMPOGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>, 258 Requires<[HasV5T]>; 259 260 def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (fpimm:$src2))), 261 (i1 (FCMPOGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)), 262 DoubleRegs:$src1))>, 263 Requires<[HasV5T]>; 264 265 // rs <= rt -> rt >= rs. 266 def : Pat<(i1 (setule (f32 IntRegs:$src1), (f32 IntRegs:$src2))), 267 (i1 (FCMPUGE32_rr IntRegs:$src2, IntRegs:$src1))>, 268 Requires<[HasV5T]>; 269 270 def : Pat<(i1 (setule (f32 IntRegs:$src1), (fpimm:$src2))), 271 (i1 (FCMPUGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>, 272 Requires<[HasV5T]>; 273 274 // Rss <= Rtt -> Rtt >= Rss. 275 def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))), 276 (i1 (FCMPUGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>, 277 Requires<[HasV5T]>; 278 279 def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (fpimm:$src2))), 280 (i1 (FCMPUGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)), 281 DoubleRegs:$src1))>, 282 Requires<[HasV5T]>; 283 284 // ne. 285 def : Pat<(i1 (setone (f32 IntRegs:$src1), (f32 IntRegs:$src2))), 286 (i1 (NOT_p (FCMPOEQ32_rr IntRegs:$src1, IntRegs:$src2)))>, 287 Requires<[HasV5T]>; 288 289 def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))), 290 (i1 (NOT_p (FCMPOEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>, 291 Requires<[HasV5T]>; 292 293 def : Pat<(i1 (setune (f32 IntRegs:$src1), (f32 IntRegs:$src2))), 294 (i1 (NOT_p (FCMPUEQ32_rr IntRegs:$src1, IntRegs:$src2)))>, 295 Requires<[HasV5T]>; 296 297 def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))), 298 (i1 (NOT_p (FCMPUEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>, 299 Requires<[HasV5T]>; 300 301 def : Pat<(i1 (setone (f32 IntRegs:$src1), (fpimm:$src2))), 302 (i1 (NOT_p (FCMPOEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>, 303 Requires<[HasV5T]>; 304 305 def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (fpimm:$src2))), 306 (i1 (NOT_p (FCMPOEQ64_rr DoubleRegs:$src1, 307 (f64 (CONST64_Float_Real fpimm:$src2)))))>, 308 Requires<[HasV5T]>; 309 310 def : Pat<(i1 (setune (f32 IntRegs:$src1), (fpimm:$src2))), 311 (i1 (NOT_p (FCMPUEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>, 312 Requires<[HasV5T]>; 313 314 def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (fpimm:$src2))), 315 (i1 (NOT_p (FCMPUEQ64_rr DoubleRegs:$src1, 316 (f64 (CONST64_Float_Real fpimm:$src2)))))>, 317 Requires<[HasV5T]>; 318 319 // Convert Integer to Floating Point. 320 def CONVERT_d2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src), 321 "$dst = convert_d2sf($src)", 322 [(set (f32 IntRegs:$dst), (sint_to_fp (i64 DoubleRegs:$src)))]>, 323 Requires<[HasV5T]>; 324 325 def CONVERT_ud2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src), 326 "$dst = convert_ud2sf($src)", 327 [(set (f32 IntRegs:$dst), (uint_to_fp (i64 DoubleRegs:$src)))]>, 328 Requires<[HasV5T]>; 329 330 def CONVERT_uw2sf : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src), 331 "$dst = convert_uw2sf($src)", 332 [(set (f32 IntRegs:$dst), (uint_to_fp (i32 IntRegs:$src)))]>, 333 Requires<[HasV5T]>; 334 335 def CONVERT_w2sf : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src), 336 "$dst = convert_w2sf($src)", 337 [(set (f32 IntRegs:$dst), (sint_to_fp (i32 IntRegs:$src)))]>, 338 Requires<[HasV5T]>; 339 340 def CONVERT_d2df : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src), 341 "$dst = convert_d2df($src)", 342 [(set (f64 DoubleRegs:$dst), (sint_to_fp (i64 DoubleRegs:$src)))]>, 343 Requires<[HasV5T]>; 344 345 def CONVERT_ud2df : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src), 346 "$dst = convert_ud2df($src)", 347 [(set (f64 DoubleRegs:$dst), (uint_to_fp (i64 DoubleRegs:$src)))]>, 348 Requires<[HasV5T]>; 349 350 def CONVERT_uw2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src), 351 "$dst = convert_uw2df($src)", 352 [(set (f64 DoubleRegs:$dst), (uint_to_fp (i32 IntRegs:$src)))]>, 353 Requires<[HasV5T]>; 354 355 def CONVERT_w2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src), 356 "$dst = convert_w2df($src)", 357 [(set (f64 DoubleRegs:$dst), (sint_to_fp (i32 IntRegs:$src)))]>, 358 Requires<[HasV5T]>; 359 360 // Convert Floating Point to Integer - default. 361 def CONVERT_df2uw : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src), 362 "$dst = convert_df2uw($src):chop", 363 [(set (i32 IntRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>, 364 Requires<[HasV5T]>; 365 366 def CONVERT_df2w : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src), 367 "$dst = convert_df2w($src):chop", 368 [(set (i32 IntRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>, 369 Requires<[HasV5T]>; 370 371 def CONVERT_sf2uw : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src), 372 "$dst = convert_sf2uw($src):chop", 373 [(set (i32 IntRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>, 374 Requires<[HasV5T]>; 375 376 def CONVERT_sf2w : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src), 377 "$dst = convert_sf2w($src):chop", 378 [(set (i32 IntRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>, 379 Requires<[HasV5T]>; 380 381 def CONVERT_df2d : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src), 382 "$dst = convert_df2d($src):chop", 383 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>, 384 Requires<[HasV5T]>; 385 386 def CONVERT_df2ud : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src), 387 "$dst = convert_df2ud($src):chop", 388 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>, 389 Requires<[HasV5T]>; 390 391 def CONVERT_sf2d : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src), 392 "$dst = convert_sf2d($src):chop", 393 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>, 394 Requires<[HasV5T]>; 395 396 def CONVERT_sf2ud : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src), 397 "$dst = convert_sf2ud($src):chop", 398 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>, 399 Requires<[HasV5T]>; 400 401 // Convert Floating Point to Integer: non-chopped. 402 let AddedComplexity = 20 in 403 def CONVERT_df2uw_nchop : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src), 404 "$dst = convert_df2uw($src)", 405 [(set (i32 IntRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>, 406 Requires<[HasV5T, IEEERndNearV5T]>; 407 408 let AddedComplexity = 20 in 409 def CONVERT_df2w_nchop : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src), 410 "$dst = convert_df2w($src)", 411 [(set (i32 IntRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>, 412 Requires<[HasV5T, IEEERndNearV5T]>; 413 414 let AddedComplexity = 20 in 415 def CONVERT_sf2uw_nchop : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src), 416 "$dst = convert_sf2uw($src)", 417 [(set (i32 IntRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>, 418 Requires<[HasV5T, IEEERndNearV5T]>; 419 420 let AddedComplexity = 20 in 421 def CONVERT_sf2w_nchop : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src), 422 "$dst = convert_sf2w($src)", 423 [(set (i32 IntRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>, 424 Requires<[HasV5T, IEEERndNearV5T]>; 425 426 let AddedComplexity = 20 in 427 def CONVERT_df2d_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src), 428 "$dst = convert_df2d($src)", 429 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>, 430 Requires<[HasV5T, IEEERndNearV5T]>; 431 432 let AddedComplexity = 20 in 433 def CONVERT_df2ud_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src), 434 "$dst = convert_df2ud($src)", 435 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>, 436 Requires<[HasV5T, IEEERndNearV5T]>; 437 438 let AddedComplexity = 20 in 439 def CONVERT_sf2d_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src), 440 "$dst = convert_sf2d($src)", 441 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>, 442 Requires<[HasV5T, IEEERndNearV5T]>; 443 444 let AddedComplexity = 20 in 445 def CONVERT_sf2ud_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src), 446 "$dst = convert_sf2ud($src)", 447 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>, 448 Requires<[HasV5T, IEEERndNearV5T]>; 449 450 451 452 // Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp]. 453 def : Pat <(i32 (bitconvert (f32 IntRegs:$src))), 454 (i32 (TFR IntRegs:$src))>, 455 Requires<[HasV5T]>; 456 457 def : Pat <(f32 (bitconvert (i32 IntRegs:$src))), 458 (f32 (TFR IntRegs:$src))>, 459 Requires<[HasV5T]>; 460 461 def : Pat <(i64 (bitconvert (f64 DoubleRegs:$src))), 462 (i64 (TFR64 DoubleRegs:$src))>, 463 Requires<[HasV5T]>; 464 465 def : Pat <(f64 (bitconvert (i64 DoubleRegs:$src))), 466 (f64 (TFR64 DoubleRegs:$src))>, 467 Requires<[HasV5T]>; 468 469 // Floating point fused multiply-add. 470 def FMADD_dp : ALU64_acc<(outs DoubleRegs:$dst), 471 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), 472 "$dst += dfmpy($src2, $src3)", 473 [(set (f64 DoubleRegs:$dst), 474 (fma DoubleRegs:$src2, DoubleRegs:$src3, DoubleRegs:$src1))], 475 "$src1 = $dst">, 476 Requires<[HasV5T]>; 477 478 def FMADD_sp : ALU64_acc<(outs IntRegs:$dst), 479 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), 480 "$dst += sfmpy($src2, $src3)", 481 [(set (f32 IntRegs:$dst), 482 (fma IntRegs:$src2, IntRegs:$src3, IntRegs:$src1))], 483 "$src1 = $dst">, 484 Requires<[HasV5T]>; 485 486 487 // Floating point max/min. 488 let AddedComplexity = 100 in 489 def FMAX_dp : ALU64_rr<(outs DoubleRegs:$dst), 490 (ins DoubleRegs:$src1, DoubleRegs:$src2), 491 "$dst = dfmax($src1, $src2)", 492 [(set DoubleRegs:$dst, (f64 (select (i1 (setolt DoubleRegs:$src2, 493 DoubleRegs:$src1)), 494 DoubleRegs:$src1, 495 DoubleRegs:$src2)))]>, 496 Requires<[HasV5T]>; 497 498 let AddedComplexity = 100 in 499 def FMAX_sp : ALU64_rr<(outs IntRegs:$dst), 500 (ins IntRegs:$src1, IntRegs:$src2), 501 "$dst = sfmax($src1, $src2)", 502 [(set IntRegs:$dst, (f32 (select (i1 (setolt IntRegs:$src2, 503 IntRegs:$src1)), 504 IntRegs:$src1, 505 IntRegs:$src2)))]>, 506 Requires<[HasV5T]>; 507 508 let AddedComplexity = 100 in 509 def FMIN_dp : ALU64_rr<(outs DoubleRegs:$dst), 510 (ins DoubleRegs:$src1, DoubleRegs:$src2), 511 "$dst = dfmin($src1, $src2)", 512 [(set DoubleRegs:$dst, (f64 (select (i1 (setogt DoubleRegs:$src2, 513 DoubleRegs:$src1)), 514 DoubleRegs:$src1, 515 DoubleRegs:$src2)))]>, 516 Requires<[HasV5T]>; 517 518 let AddedComplexity = 100 in 519 def FMIN_sp : ALU64_rr<(outs IntRegs:$dst), 520 (ins IntRegs:$src1, IntRegs:$src2), 521 "$dst = sfmin($src1, $src2)", 522 [(set IntRegs:$dst, (f32 (select (i1 (setogt IntRegs:$src2, 523 IntRegs:$src1)), 524 IntRegs:$src1, 525 IntRegs:$src2)))]>, 526 Requires<[HasV5T]>; 527 528 // Pseudo instruction to encode a set of conditional transfers. 529 // This instruction is used instead of a mux and trades-off codesize 530 // for performance. We conduct this transformation optimistically in 531 // the hope that these instructions get promoted to dot-new transfers. 532 let AddedComplexity = 100, isPredicated = 1 in 533 def TFR_condset_rr_f : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, 534 IntRegs:$src2, 535 IntRegs:$src3), 536 "Error; should not emit", 537 [(set IntRegs:$dst, (f32 (select PredRegs:$src1, 538 IntRegs:$src2, 539 IntRegs:$src3)))]>, 540 Requires<[HasV5T]>; 541 542 let AddedComplexity = 100, isPredicated = 1 in 543 def TFR_condset_rr64_f : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1, 544 DoubleRegs:$src2, 545 DoubleRegs:$src3), 546 "Error; should not emit", 547 [(set DoubleRegs:$dst, (f64 (select PredRegs:$src1, 548 DoubleRegs:$src2, 549 DoubleRegs:$src3)))]>, 550 Requires<[HasV5T]>; 551 552 553 554 let AddedComplexity = 100, isPredicated = 1 in 555 def TFR_condset_ri_f : ALU32_rr<(outs IntRegs:$dst), 556 (ins PredRegs:$src1, IntRegs:$src2, f32imm:$src3), 557 "Error; should not emit", 558 [(set IntRegs:$dst, 559 (f32 (select PredRegs:$src1, IntRegs:$src2, fpimm:$src3)))]>, 560 Requires<[HasV5T]>; 561 562 let AddedComplexity = 100, isPredicated = 1 in 563 def TFR_condset_ir_f : ALU32_rr<(outs IntRegs:$dst), 564 (ins PredRegs:$src1, f32imm:$src2, IntRegs:$src3), 565 "Error; should not emit", 566 [(set IntRegs:$dst, 567 (f32 (select PredRegs:$src1, fpimm:$src2, IntRegs:$src3)))]>, 568 Requires<[HasV5T]>; 569 570 let AddedComplexity = 100, isPredicated = 1 in 571 def TFR_condset_ii_f : ALU32_rr<(outs IntRegs:$dst), 572 (ins PredRegs:$src1, f32imm:$src2, f32imm:$src3), 573 "Error; should not emit", 574 [(set IntRegs:$dst, (f32 (select PredRegs:$src1, 575 fpimm:$src2, 576 fpimm:$src3)))]>, 577 Requires<[HasV5T]>; 578 579 580 def : Pat <(select (i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))), 581 (f32 IntRegs:$src3), 582 (f32 IntRegs:$src4)), 583 (TFR_condset_rr_f (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1), IntRegs:$src4, 584 IntRegs:$src3)>, Requires<[HasV5T]>; 585 586 def : Pat <(select (i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))), 587 (f64 DoubleRegs:$src3), 588 (f64 DoubleRegs:$src4)), 589 (TFR_condset_rr64_f (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1), 590 DoubleRegs:$src4, DoubleRegs:$src3)>, Requires<[HasV5T]>; 591 592 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i). 593 def : Pat <(select (not PredRegs:$src1), fpimm:$src2, fpimm:$src3), 594 (TFR_condset_ii_f PredRegs:$src1, fpimm:$src3, fpimm:$src2)>; 595 596 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1) 597 // => r0 = TFR_condset_ri(p0, r1, #i) 598 def : Pat <(select (not PredRegs:$src1), fpimm:$src2, IntRegs:$src3), 599 (TFR_condset_ri_f PredRegs:$src1, IntRegs:$src3, fpimm:$src2)>; 600 601 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i) 602 // => r0 = TFR_condset_ir(p0, #i, r1) 603 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, fpimm:$src3), 604 (TFR_condset_ir_f PredRegs:$src1, fpimm:$src3, IntRegs:$src2)>; 605 606 def : Pat <(i32 (fp_to_sint (f64 DoubleRegs:$src1))), 607 (i32 (EXTRACT_SUBREG (i64 (CONVERT_df2d (f64 DoubleRegs:$src1))), subreg_loreg))>, 608 Requires<[HasV5T]>; 609 610 def : Pat <(fabs (f32 IntRegs:$src1)), 611 (CLRBIT_31 (f32 IntRegs:$src1), 31)>, 612 Requires<[HasV5T]>; 613 614 def : Pat <(fneg (f32 IntRegs:$src1)), 615 (TOGBIT_31 (f32 IntRegs:$src1), 31)>, 616 Requires<[HasV5T]>; 617 618 /* 619 def : Pat <(fabs (f64 DoubleRegs:$src1)), 620 (CLRBIT_31 (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>, 621 Requires<[HasV5T]>; 622 623 def : Pat <(fabs (f64 DoubleRegs:$src1)), 624 (CLRBIT_31 (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>, 625 Requires<[HasV5T]>; 626 */ 627
