1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips64 instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Mips Operand, Complex Patterns and Transformations Definitions. 16 //===----------------------------------------------------------------------===// 17 18 // Instruction operand types 19 def shamt_64 : Operand<i64>; 20 21 // Unsigned Operand 22 def uimm16_64 : Operand<i64> { 23 let PrintMethod = "printUnsignedImm"; 24 } 25 26 // Transformation Function - get Imm - 32. 27 def Subtract32 : SDNodeXForm<imm, [{ 28 return getImm(N, (unsigned)N->getZExtValue() - 32); 29 }]>; 30 31 // shamt must fit in 6 bits. 32 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 33 34 //===----------------------------------------------------------------------===// 35 // Instructions specific format 36 //===----------------------------------------------------------------------===// 37 let DecoderNamespace = "Mips64" in { 38 39 multiclass Atomic2Ops64<PatFrag Op> { 40 def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>, 41 Requires<[NotN64, HasStdEnc]>; 42 def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>, 43 Requires<[IsN64, HasStdEnc]> { 44 let isCodeGenOnly = 1; 45 } 46 } 47 48 multiclass AtomicCmpSwap64<PatFrag Op> { 49 def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>, 50 Requires<[NotN64, HasStdEnc]>; 51 def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>, 52 Requires<[IsN64, HasStdEnc]> { 53 let isCodeGenOnly = 1; 54 } 55 } 56 } 57 let usesCustomInserter = 1, Predicates = [HasStdEnc], 58 DecoderNamespace = "Mips64" in { 59 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>; 60 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>; 61 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>; 62 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>; 63 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>; 64 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>; 65 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>; 66 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>; 67 } 68 69 //===----------------------------------------------------------------------===// 70 // Instruction definition 71 //===----------------------------------------------------------------------===// 72 let DecoderNamespace = "Mips64" in { 73 /// Arithmetic Instructions (ALU Immediate) 74 def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>; 75 def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, immSExt16, add>, 76 ADDI_FM<0x19>, IsAsCheapAsAMove; 77 def DANDi : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, immZExt16, and>, 78 ADDI_FM<0xc>; 79 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>, 80 SLTI_FM<0xa>; 81 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>, 82 SLTI_FM<0xb>; 83 def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, immZExt16, or>, 84 ADDI_FM<0xd>; 85 def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, immZExt16, xor>, 86 ADDI_FM<0xe>; 87 def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM; 88 89 /// Arithmetic Instructions (3-Operand, R-Type) 90 def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>; 91 def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIAlu, add>, 92 ADD_FM<0, 0x2d>; 93 def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIAlu, sub>, 94 ADD_FM<0, 0x2f>; 95 def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>; 96 def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>; 97 def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>; 98 def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>; 99 def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 100 def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>; 101 102 /// Shift Instructions 103 def DSLL : shift_rotate_imm<"dsll", shamt, CPU64RegsOpnd, shl, immZExt6>, 104 SRA_FM<0x38, 0>; 105 def DSRL : shift_rotate_imm<"dsrl", shamt, CPU64RegsOpnd, srl, immZExt6>, 106 SRA_FM<0x3a, 0>; 107 def DSRA : shift_rotate_imm<"dsra", shamt, CPU64RegsOpnd, sra, immZExt6>, 108 SRA_FM<0x3b, 0>; 109 def DSLLV : shift_rotate_reg<"dsllv", CPU64RegsOpnd, shl>, SRLV_FM<0x14, 0>; 110 def DSRLV : shift_rotate_reg<"dsrlv", CPU64RegsOpnd, srl>, SRLV_FM<0x16, 0>; 111 def DSRAV : shift_rotate_reg<"dsrav", CPU64RegsOpnd, sra>, SRLV_FM<0x17, 0>; 112 def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64RegsOpnd>, SRA_FM<0x3c, 0>; 113 def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64RegsOpnd>, SRA_FM<0x3e, 0>; 114 def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>; 115 } 116 // Rotate Instructions 117 let Predicates = [HasMips64r2, HasStdEnc], 118 DecoderNamespace = "Mips64" in { 119 def DROTR : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>, 120 SRA_FM<0x3a, 1>; 121 def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>, 122 SRLV_FM<0x16, 1>; 123 } 124 125 let DecoderNamespace = "Mips64" in { 126 /// Load and Store Instructions 127 /// aligned 128 defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8>, LW_FM<0x20>; 129 defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8>, LW_FM<0x24>; 130 defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16>, LW_FM<0x21>; 131 defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16>, LW_FM<0x25>; 132 defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32>, LW_FM<0x23>; 133 defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32>, LW_FM<0x27>; 134 defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8>, LW_FM<0x28>; 135 defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16>, LW_FM<0x29>; 136 defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32>, LW_FM<0x2b>; 137 defm LD : LoadM<"ld", CPU64Regs, load>, LW_FM<0x37>; 138 defm SD : StoreM<"sd", CPU64Regs, store>, LW_FM<0x3f>; 139 140 /// load/store left/right 141 defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>; 142 defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>; 143 defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>; 144 defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>; 145 146 defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>; 147 defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>; 148 defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>; 149 defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>; 150 151 /// Load-linked, Store-conditional 152 let Predicates = [NotN64, HasStdEnc] in { 153 def LLD : LLBase<"lld", CPU64RegsOpnd, mem>, LW_FM<0x34>; 154 def SCD : SCBase<"scd", CPU64RegsOpnd, mem>, LW_FM<0x3c>; 155 } 156 157 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in { 158 def LLD_P8 : LLBase<"lld", CPU64RegsOpnd, mem64>, LW_FM<0x34>; 159 def SCD_P8 : SCBase<"scd", CPU64RegsOpnd, mem64>, LW_FM<0x3c>; 160 } 161 162 /// Jump and Branch Instructions 163 def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>; 164 def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>; 165 def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>; 166 def BGEZ64 : CBranchZero<"bgez", setge, CPU64Regs>, BGEZ_FM<1, 1>; 167 def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64Regs>, BGEZ_FM<7, 0>; 168 def BLEZ64 : CBranchZero<"blez", setle, CPU64Regs>, BGEZ_FM<6, 0>; 169 def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>; 170 } 171 let DecoderNamespace = "Mips64" in 172 def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM; 173 def JALR64Pseudo : JumpLinkRegPseudo<CPU64Regs, JALR64, RA_64>; 174 def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 175 176 let DecoderNamespace = "Mips64" in { 177 /// Multiply and Divide Instructions. 178 def DMULT : Mult<"dmult", IIImul, CPU64RegsOpnd, [HI64, LO64]>, 179 MULT_FM<0, 0x1c>; 180 def DMULTu : Mult<"dmultu", IIImul, CPU64RegsOpnd, [HI64, LO64]>, 181 MULT_FM<0, 0x1d>; 182 def DSDIV : Div<MipsDivRem, "ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, 183 MULT_FM<0, 0x1e>; 184 def DUDIV : Div<MipsDivRemU, "ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, 185 MULT_FM<0, 0x1f>; 186 187 def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>; 188 def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>; 189 def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>; 190 def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>; 191 192 /// Sign Ext In Register Instructions. 193 def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>; 194 def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>; 195 196 /// Count Leading 197 def DCLZ : CountLeading0<"dclz", CPU64RegsOpnd>, CLO_FM<0x24>; 198 def DCLO : CountLeading1<"dclo", CPU64RegsOpnd>, CLO_FM<0x25>; 199 200 /// Double Word Swap Bytes/HalfWords 201 def DSBH : SubwordSwap<"dsbh", CPU64RegsOpnd>, SEB_FM<2, 0x24>; 202 def DSHD : SubwordSwap<"dshd", CPU64RegsOpnd>, SEB_FM<5, 0x24>; 203 204 def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>; 205 206 } 207 let DecoderNamespace = "Mips64" in { 208 def RDHWR64 : ReadHardware<CPU64Regs, HW64RegsOpnd>, RDHWR_FM; 209 210 def DEXT : ExtBase<"dext", CPU64RegsOpnd>, EXT_FM<3>; 211 let Pattern = []<dag> in { 212 def DEXTU : ExtBase<"dextu", CPU64RegsOpnd>, EXT_FM<2>; 213 def DEXTM : ExtBase<"dextm", CPU64RegsOpnd>, EXT_FM<1>; 214 } 215 def DINS : InsBase<"dins", CPU64RegsOpnd>, EXT_FM<7>; 216 let Pattern = []<dag> in { 217 def DINSU : InsBase<"dinsu", CPU64RegsOpnd>, EXT_FM<6>; 218 def DINSM : InsBase<"dinsm", CPU64RegsOpnd>, EXT_FM<5>; 219 } 220 221 let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 222 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 223 "dsll\t$rd, $rt, 32", [], IIAlu>; 224 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 225 "sll\t$rd, $rt, 0", [], IIAlu>; 226 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), 227 "sll\t$rd, $rt, 0", [], IIAlu>; 228 } 229 } 230 //===----------------------------------------------------------------------===// 231 // Arbitrary patterns that map to one or more instructions 232 //===----------------------------------------------------------------------===// 233 234 // extended loads 235 let Predicates = [NotN64, HasStdEnc] in { 236 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 237 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 238 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 239 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 240 } 241 let Predicates = [IsN64, HasStdEnc] in { 242 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; 243 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; 244 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>; 245 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>; 246 } 247 248 // hi/lo relocs 249 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 250 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 251 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 252 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 253 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 254 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 255 256 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 257 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 258 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 259 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 260 def : MipsPat<(MipsLo tglobaltlsaddr:$in), 261 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 262 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 263 264 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)), 265 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>; 266 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)), 267 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>; 268 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)), 269 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>; 270 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)), 271 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>; 272 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)), 273 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>; 274 275 def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>; 276 def : WrapperPat<tconstpool, DADDiu, CPU64Regs>; 277 def : WrapperPat<texternalsym, DADDiu, CPU64Regs>; 278 def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>; 279 def : WrapperPat<tjumptable, DADDiu, CPU64Regs>; 280 def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>; 281 282 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 283 ZERO_64>; 284 285 // setcc patterns 286 defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 287 defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 288 defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 289 defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 290 defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 291 292 // truncate 293 def : MipsPat<(i32 (trunc CPU64Regs:$src)), 294 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, 295 Requires<[IsN64, HasStdEnc]>; 296 297 // 32-to-64-bit extension 298 def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 299 def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; 300 def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 301 302 // Sign extend in register 303 def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)), 304 (SLL64_64 CPU64Regs:$src)>; 305 306 // bswap MipsPattern 307 def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; 308 309 //===----------------------------------------------------------------------===// 310 // Instruction aliases 311 //===----------------------------------------------------------------------===// 312 def : InstAlias<"move $dst, $src", 313 (DADDu CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>, 314 Requires<[HasMips64]>; 315 def : InstAlias<"move $dst, $src", 316 (OR64 CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>, 317 Requires<[HasMips64]>; 318 def : InstAlias<"and $rs, $rt, $imm", 319 (DANDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), 320 1>, 321 Requires<[HasMips64]>; 322 def : InstAlias<"slt $rs, $rt, $imm", 323 (SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm), 1>, 324 Requires<[HasMips64]>; 325 def : InstAlias<"xor $rs, $rt, $imm", 326 (XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), 327 1>, 328 Requires<[HasMips64]>; 329 def : InstAlias<"not $rt, $rs", 330 (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>, 331 Requires<[HasMips64]>; 332 def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>; 333 def : InstAlias<"jalr $rs", (JALR64 RA_64, CPU64Regs:$rs)>, 334 Requires<[HasMips64]>; 335 def : InstAlias<"daddu $rs, $rt, $imm", 336 (DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), 337 1>; 338 def : InstAlias<"dadd $rs, $rt, $imm", 339 (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), 340 1>; 341 342 /// Move between CPU and coprocessor registers 343 344 let DecoderNamespace = "Mips64" in { 345 def DMFC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt), 346 (ins CPU64RegsOpnd:$rd, uimm16:$sel), 347 "dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>; 348 def DMTC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel), 349 (ins CPU64RegsOpnd:$rt), 350 "dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>; 351 def DMFC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt), 352 (ins CPU64RegsOpnd:$rd, uimm16:$sel), 353 "dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>; 354 def DMTC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel), 355 (ins CPU64RegsOpnd:$rt), 356 "dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>; 357 } 358 359 // Two operand (implicit 0 selector) versions: 360 def : InstAlias<"dmfc0 $rt, $rd", 361 (DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>; 362 def : InstAlias<"dmtc0 $rt, $rd", 363 (DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>; 364 def : InstAlias<"dmfc2 $rt, $rd", 365 (DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>; 366 def : InstAlias<"dmtc2 $rt, $rd", 367 (DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>; 368 369
