1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the subset of the 32-bit PowerPC instruction set, as used 11 // by the PowerPC instruction selector. 12 // 13 //===----------------------------------------------------------------------===// 14 15 include "PPCInstrFormats.td" 16 17 //===----------------------------------------------------------------------===// 18 // PowerPC specific type constraints. 19 // 20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22 ]>; 23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 25 SDTCisVT<1, i32> ]>; 26 def SDT_PPCvperm : SDTypeProfile<1, 3, [ 27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 28 ]>; 29 30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 32 ]>; 33 34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 36 ]>; 37 38 def SDT_PPClbrx : SDTypeProfile<1, 2, [ 39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 40 ]>; 41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 43 ]>; 44 45 def SDT_PPClarx : SDTypeProfile<1, 1, [ 46 SDTCisInt<0>, SDTCisPtrTy<1> 47 ]>; 48 def SDT_PPCstcx : SDTypeProfile<0, 2, [ 49 SDTCisInt<0>, SDTCisPtrTy<1> 50 ]>; 51 52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 53 SDTCisPtrTy<0>, SDTCisVT<1, i32> 54 ]>; 55 56 def SDT_PPCnop : SDTypeProfile<0, 0, []>; 57 58 //===----------------------------------------------------------------------===// 59 // PowerPC specific DAG Nodes. 60 // 61 62 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 63 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 64 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 65 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 66 [SDNPHasChain, SDNPMayStore]>; 67 68 // This sequence is used for long double->int conversions. It changes the 69 // bits in the FPSCR which is not modelled. 70 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 71 [SDNPOutGlue]>; 72 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 73 [SDNPInGlue, SDNPOutGlue]>; 74 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 75 [SDNPInGlue, SDNPOutGlue]>; 76 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, 77 [SDNPInGlue, SDNPOutGlue]>; 78 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3, 79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>, 80 SDTCisVT<3, f64>]>, 81 [SDNPInGlue]>; 82 83 def PPCfsel : SDNode<"PPCISD::FSEL", 84 // Type constraint for fsel. 85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 87 88 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 89 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 90 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>; 91 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 92 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 93 94 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 95 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 96 [SDNPMayLoad]>; 97 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 98 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 99 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 100 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 101 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 102 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 103 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 104 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp, 105 [SDNPHasChain]>; 106 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 107 108 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 109 110 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 111 // amounts. These nodes are generated by the multi-precision shift code. 112 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 113 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 114 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 115 116 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; 117 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, 118 [SDNPHasChain, SDNPMayStore]>; 119 120 // These are target-independent nodes, but have target-specific formats. 121 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 122 [SDNPHasChain, SDNPOutGlue]>; 123 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 125 126 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 127 def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall, 128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 129 SDNPVariadic]>; 130 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall, 131 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 132 SDNPVariadic]>; 133 def PPCcall_nop_SVR4 : SDNode<"PPCISD::CALL_NOP_SVR4", SDT_PPCCall, 134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 135 SDNPVariadic]>; 136 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>; 137 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>, 138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 139 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>, 140 [SDNPHasChain, SDNPSideEffect, 141 SDNPInGlue, SDNPOutGlue]>; 142 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>, 143 [SDNPHasChain, SDNPSideEffect, 144 SDNPInGlue, SDNPOutGlue]>; 145 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 147 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone, 148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 149 SDNPVariadic]>; 150 151 def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone, 152 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 153 SDNPVariadic]>; 154 155 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 156 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 157 158 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 159 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 160 161 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 162 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 163 164 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 165 [SDNPHasChain, SDNPOptInGlue]>; 166 167 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 168 [SDNPHasChain, SDNPMayLoad]>; 169 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 170 [SDNPHasChain, SDNPMayStore]>; 171 172 // Instructions to set/unset CR bit 6 for SVR4 vararg calls 173 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 174 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 175 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 176 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 177 178 // Instructions to support atomic operations 179 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx, 180 [SDNPHasChain, SDNPMayLoad]>; 181 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx, 182 [SDNPHasChain, SDNPMayStore]>; 183 184 // Instructions to support medium and large code model 185 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>; 186 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>; 187 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>; 188 189 190 // Instructions to support dynamic alloca. 191 def SDTDynOp : SDTypeProfile<1, 2, []>; 192 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 193 194 //===----------------------------------------------------------------------===// 195 // PowerPC specific transformation functions and pattern fragments. 196 // 197 198 def SHL32 : SDNodeXForm<imm, [{ 199 // Transformation function: 31 - imm 200 return getI32Imm(31 - N->getZExtValue()); 201 }]>; 202 203 def SRL32 : SDNodeXForm<imm, [{ 204 // Transformation function: 32 - imm 205 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0); 206 }]>; 207 208 def LO16 : SDNodeXForm<imm, [{ 209 // Transformation function: get the low 16 bits. 210 return getI32Imm((unsigned short)N->getZExtValue()); 211 }]>; 212 213 def HI16 : SDNodeXForm<imm, [{ 214 // Transformation function: shift the immediate value down into the low bits. 215 return getI32Imm((unsigned)N->getZExtValue() >> 16); 216 }]>; 217 218 def HA16 : SDNodeXForm<imm, [{ 219 // Transformation function: shift the immediate value down into the low bits. 220 signed int Val = N->getZExtValue(); 221 return getI32Imm((Val - (signed short)Val) >> 16); 222 }]>; 223 def MB : SDNodeXForm<imm, [{ 224 // Transformation function: get the start bit of a mask 225 unsigned mb = 0, me; 226 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 227 return getI32Imm(mb); 228 }]>; 229 230 def ME : SDNodeXForm<imm, [{ 231 // Transformation function: get the end bit of a mask 232 unsigned mb, me = 0; 233 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 234 return getI32Imm(me); 235 }]>; 236 def maskimm32 : PatLeaf<(imm), [{ 237 // maskImm predicate - True if immediate is a run of ones. 238 unsigned mb, me; 239 if (N->getValueType(0) == MVT::i32) 240 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 241 else 242 return false; 243 }]>; 244 245 def immSExt16 : PatLeaf<(imm), [{ 246 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 247 // field. Used by instructions like 'addi'. 248 if (N->getValueType(0) == MVT::i32) 249 return (int32_t)N->getZExtValue() == (short)N->getZExtValue(); 250 else 251 return (int64_t)N->getZExtValue() == (short)N->getZExtValue(); 252 }]>; 253 def immZExt16 : PatLeaf<(imm), [{ 254 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 255 // field. Used by instructions like 'ori'. 256 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 257 }], LO16>; 258 259 // imm16Shifted* - These match immediates where the low 16-bits are zero. There 260 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 261 // identical in 32-bit mode, but in 64-bit mode, they return true if the 262 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits 263 // clear). 264 def imm16ShiftedZExt : PatLeaf<(imm), [{ 265 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 266 // immediate are set. Used by instructions like 'xoris'. 267 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 268 }], HI16>; 269 270 def imm16ShiftedSExt : PatLeaf<(imm), [{ 271 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 272 // immediate are set. Used by instructions like 'addis'. Identical to 273 // imm16ShiftedZExt in 32-bit mode. 274 if (N->getZExtValue() & 0xFFFF) return false; 275 if (N->getValueType(0) == MVT::i32) 276 return true; 277 // For 64-bit, make sure it is sext right. 278 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 279 }], HI16>; 280 281 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 282 // restricted memrix (offset/4) constants are alignment sensitive. If these 283 // offsets are hidden behind TOC entries than the values of the lower-order 284 // bits cannot be checked directly. As a result, we need to also incorporate 285 // an alignment check into the relevant patterns. 286 287 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 288 return cast<LoadSDNode>(N)->getAlignment() >= 4; 289 }]>; 290 def aligned4store : PatFrag<(ops node:$val, node:$ptr), 291 (store node:$val, node:$ptr), [{ 292 return cast<StoreSDNode>(N)->getAlignment() >= 4; 293 }]>; 294 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 295 return cast<LoadSDNode>(N)->getAlignment() >= 4; 296 }]>; 297 def aligned4pre_store : PatFrag< 298 (ops node:$val, node:$base, node:$offset), 299 (pre_store node:$val, node:$base, node:$offset), [{ 300 return cast<StoreSDNode>(N)->getAlignment() >= 4; 301 }]>; 302 303 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 304 return cast<LoadSDNode>(N)->getAlignment() < 4; 305 }]>; 306 def unaligned4store : PatFrag<(ops node:$val, node:$ptr), 307 (store node:$val, node:$ptr), [{ 308 return cast<StoreSDNode>(N)->getAlignment() < 4; 309 }]>; 310 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 311 return cast<LoadSDNode>(N)->getAlignment() < 4; 312 }]>; 313 314 //===----------------------------------------------------------------------===// 315 // PowerPC Flag Definitions. 316 317 class isPPC64 { bit PPC64 = 1; } 318 class isDOT { 319 list<Register> Defs = [CR0]; 320 bit RC = 1; 321 } 322 323 class RegConstraint<string C> { 324 string Constraints = C; 325 } 326 class NoEncode<string E> { 327 string DisableEncoding = E; 328 } 329 330 331 //===----------------------------------------------------------------------===// 332 // PowerPC Operand Definitions. 333 334 def s5imm : Operand<i32> { 335 let PrintMethod = "printS5ImmOperand"; 336 } 337 def u5imm : Operand<i32> { 338 let PrintMethod = "printU5ImmOperand"; 339 } 340 def u6imm : Operand<i32> { 341 let PrintMethod = "printU6ImmOperand"; 342 } 343 def s16imm : Operand<i32> { 344 let PrintMethod = "printS16ImmOperand"; 345 } 346 def u16imm : Operand<i32> { 347 let PrintMethod = "printU16ImmOperand"; 348 } 349 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 350 let PrintMethod = "printS16X4ImmOperand"; 351 } 352 def directbrtarget : Operand<OtherVT> { 353 let PrintMethod = "printBranchOperand"; 354 let EncoderMethod = "getDirectBrEncoding"; 355 } 356 def condbrtarget : Operand<OtherVT> { 357 let PrintMethod = "printBranchOperand"; 358 let EncoderMethod = "getCondBrEncoding"; 359 } 360 def calltarget : Operand<iPTR> { 361 let EncoderMethod = "getDirectBrEncoding"; 362 } 363 def aaddr : Operand<iPTR> { 364 let PrintMethod = "printAbsAddrOperand"; 365 } 366 def symbolHi: Operand<i32> { 367 let PrintMethod = "printSymbolHi"; 368 let EncoderMethod = "getHA16Encoding"; 369 } 370 def symbolLo: Operand<i32> { 371 let PrintMethod = "printSymbolLo"; 372 let EncoderMethod = "getLO16Encoding"; 373 } 374 def crbitm: Operand<i8> { 375 let PrintMethod = "printcrbitm"; 376 let EncoderMethod = "get_crbitm_encoding"; 377 } 378 // Address operands 379 def memri : Operand<iPTR> { 380 let PrintMethod = "printMemRegImm"; 381 let MIOperandInfo = (ops symbolLo:$imm, ptr_rc:$reg); 382 let EncoderMethod = "getMemRIEncoding"; 383 } 384 def memrr : Operand<iPTR> { 385 let PrintMethod = "printMemRegReg"; 386 let MIOperandInfo = (ops ptr_rc:$offreg, ptr_rc:$ptrreg); 387 } 388 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. 389 let PrintMethod = "printMemRegImmShifted"; 390 let MIOperandInfo = (ops symbolLo:$imm, ptr_rc:$reg); 391 let EncoderMethod = "getMemRIXEncoding"; 392 } 393 394 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg 395 // that doesn't matter. 396 def pred : PredicateOperand<OtherVT, (ops imm, CRRC), 397 (ops (i32 20), (i32 zero_reg))> { 398 let PrintMethod = "printPredicateOperand"; 399 } 400 401 // Define PowerPC specific addressing mode. 402 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 403 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 404 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 405 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" 406 407 /// This is just the offset part of iaddr, used for preinc. 408 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 409 def xaddroff : ComplexPattern<iPTR, 1, "SelectAddrIdxOffs", [], []>; 410 411 //===----------------------------------------------------------------------===// 412 // PowerPC Instruction Predicate Definitions. 413 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">; 414 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">; 415 def IsBookE : Predicate<"PPCSubTarget.isBookE()">; 416 417 //===----------------------------------------------------------------------===// 418 // PowerPC Instruction Definitions. 419 420 // Pseudo-instructions: 421 422 let hasCtrlDep = 1 in { 423 let Defs = [R1], Uses = [R1] in { 424 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt", 425 [(callseq_start timm:$amt)]>; 426 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2", 427 [(callseq_end timm:$amt1, timm:$amt2)]>; 428 } 429 430 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), 431 "UPDATE_VRSAVE $rD, $rS", []>; 432 } 433 434 let Defs = [R1], Uses = [R1] in 435 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC", 436 [(set GPRC:$result, 437 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>; 438 439 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 440 // instruction selection into a branch sequence. 441 let usesCustomInserter = 1, // Expanded after instruction selection. 442 PPC970_Single = 1 in { 443 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F, 444 i32imm:$BROPC), "#SELECT_CC_I4", 445 []>; 446 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F, 447 i32imm:$BROPC), "#SELECT_CC_I8", 448 []>; 449 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F, 450 i32imm:$BROPC), "#SELECT_CC_F4", 451 []>; 452 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F, 453 i32imm:$BROPC), "#SELECT_CC_F8", 454 []>; 455 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F, 456 i32imm:$BROPC), "#SELECT_CC_VRRC", 457 []>; 458 } 459 460 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 461 // scavenge a register for it. 462 let mayStore = 1 in 463 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F), 464 "#SPILL_CR", []>; 465 466 // RESTORE_CR - Indicate that we're restoring the CR register (previously 467 // spilled), so we'll need to scavenge a register for it. 468 let mayLoad = 1 in 469 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F), 470 "#RESTORE_CR", []>; 471 472 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 473 let isCodeGenOnly = 1, isReturn = 1, Uses = [LR, RM] in 474 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), 475 "b${p:cc}lr ${p:reg}", BrB, 476 [(retflag)]>; 477 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in 478 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; 479 } 480 481 let Defs = [LR] in 482 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>, 483 PPC970_Unit_BRU; 484 485 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 486 let isBarrier = 1 in { 487 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 488 "b $dst", BrB, 489 [(br bb:$dst)]>; 490 } 491 492 // BCC represents an arbitrary conditional branch on a predicate. 493 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 494 // a two-value operand where a dag node expects two operands. :( 495 let isCodeGenOnly = 1 in 496 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 497 "b${cond:cc} ${cond:reg}, $dst" 498 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; 499 500 let Defs = [CTR], Uses = [CTR] in { 501 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 502 "bdz $dst">; 503 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 504 "bdnz $dst">; 505 } 506 } 507 508 // Darwin ABI Calls. 509 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 510 // Convenient aliases for call instructions 511 let Uses = [RM] in { 512 def BL_Darwin : IForm<18, 0, 1, 513 (outs), (ins calltarget:$func), 514 "bl $func", BrB, []>; // See Pat patterns below. 515 def BLA_Darwin : IForm<18, 1, 1, 516 (outs), (ins aaddr:$func), 517 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>; 518 } 519 let Uses = [CTR, RM] in { 520 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 521 (outs), (ins), 522 "bctrl", BrB, 523 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>; 524 } 525 } 526 527 // SVR4 ABI Calls. 528 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 529 // Convenient aliases for call instructions 530 let Uses = [RM] in { 531 def BL_SVR4 : IForm<18, 0, 1, 532 (outs), (ins calltarget:$func), 533 "bl $func", BrB, []>; // See Pat patterns below. 534 def BLA_SVR4 : IForm<18, 1, 1, 535 (outs), (ins aaddr:$func), 536 "bla $func", BrB, 537 [(PPCcall_SVR4 (i32 imm:$func))]>; 538 } 539 let Uses = [CTR, RM] in { 540 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1, 541 (outs), (ins), 542 "bctrl", BrB, 543 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>; 544 } 545 } 546 547 548 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 549 def TCRETURNdi :Pseudo< (outs), 550 (ins calltarget:$dst, i32imm:$offset), 551 "#TC_RETURNd $dst $offset", 552 []>; 553 554 555 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 556 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), 557 "#TC_RETURNa $func $offset", 558 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 559 560 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 561 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 562 "#TC_RETURNr $dst $offset", 563 []>; 564 565 566 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 567 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 568 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 569 Requires<[In32BitMode]>; 570 571 572 573 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 574 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 575 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 576 "b $dst", BrB, 577 []>; 578 579 580 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 581 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 582 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 583 "ba $dst", BrB, 584 []>; 585 586 587 // DCB* instructions. 588 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), 589 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 590 PPC970_DGroup_Single; 591 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), 592 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 593 PPC970_DGroup_Single; 594 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), 595 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 596 PPC970_DGroup_Single; 597 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), 598 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 599 PPC970_DGroup_Single; 600 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), 601 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 602 PPC970_DGroup_Single; 603 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), 604 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 605 PPC970_DGroup_Single; 606 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), 607 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 608 PPC970_DGroup_Single; 609 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), 610 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 611 PPC970_DGroup_Single; 612 613 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 614 (DCBT xoaddr:$dst)>; 615 616 // Atomic operations 617 let usesCustomInserter = 1 in { 618 let Defs = [CR0] in { 619 def ATOMIC_LOAD_ADD_I8 : Pseudo< 620 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8", 621 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>; 622 def ATOMIC_LOAD_SUB_I8 : Pseudo< 623 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8", 624 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>; 625 def ATOMIC_LOAD_AND_I8 : Pseudo< 626 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8", 627 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>; 628 def ATOMIC_LOAD_OR_I8 : Pseudo< 629 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8", 630 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>; 631 def ATOMIC_LOAD_XOR_I8 : Pseudo< 632 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8", 633 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>; 634 def ATOMIC_LOAD_NAND_I8 : Pseudo< 635 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8", 636 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>; 637 def ATOMIC_LOAD_ADD_I16 : Pseudo< 638 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16", 639 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>; 640 def ATOMIC_LOAD_SUB_I16 : Pseudo< 641 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16", 642 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>; 643 def ATOMIC_LOAD_AND_I16 : Pseudo< 644 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16", 645 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>; 646 def ATOMIC_LOAD_OR_I16 : Pseudo< 647 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16", 648 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>; 649 def ATOMIC_LOAD_XOR_I16 : Pseudo< 650 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16", 651 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>; 652 def ATOMIC_LOAD_NAND_I16 : Pseudo< 653 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16", 654 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>; 655 def ATOMIC_LOAD_ADD_I32 : Pseudo< 656 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32", 657 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>; 658 def ATOMIC_LOAD_SUB_I32 : Pseudo< 659 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32", 660 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>; 661 def ATOMIC_LOAD_AND_I32 : Pseudo< 662 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32", 663 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>; 664 def ATOMIC_LOAD_OR_I32 : Pseudo< 665 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32", 666 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>; 667 def ATOMIC_LOAD_XOR_I32 : Pseudo< 668 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32", 669 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>; 670 def ATOMIC_LOAD_NAND_I32 : Pseudo< 671 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32", 672 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>; 673 674 def ATOMIC_CMP_SWAP_I8 : Pseudo< 675 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8", 676 [(set GPRC:$dst, 677 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 678 def ATOMIC_CMP_SWAP_I16 : Pseudo< 679 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 680 [(set GPRC:$dst, 681 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 682 def ATOMIC_CMP_SWAP_I32 : Pseudo< 683 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 684 [(set GPRC:$dst, 685 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 686 687 def ATOMIC_SWAP_I8 : Pseudo< 688 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8", 689 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>; 690 def ATOMIC_SWAP_I16 : Pseudo< 691 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16", 692 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>; 693 def ATOMIC_SWAP_I32 : Pseudo< 694 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32", 695 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>; 696 } 697 } 698 699 // Instructions to support atomic operations 700 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src), 701 "lwarx $rD, $src", LdStLWARX, 702 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>; 703 704 let Defs = [CR0] in 705 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst), 706 "stwcx. $rS, $dst", LdStSTWCX, 707 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>, 708 isDOT; 709 710 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 711 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>; 712 713 //===----------------------------------------------------------------------===// 714 // PPC32 Load Instructions. 715 // 716 717 // Unindexed (r+i) Loads. 718 let canFoldAsLoad = 1, PPC970_Unit = 2 in { 719 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), 720 "lbz $rD, $src", LdStLoad, 721 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; 722 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src), 723 "lha $rD, $src", LdStLHA, 724 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, 725 PPC970_DGroup_Cracked; 726 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src), 727 "lhz $rD, $src", LdStLoad, 728 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; 729 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src), 730 "lwz $rD, $src", LdStLoad, 731 [(set GPRC:$rD, (load iaddr:$src))]>; 732 733 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src), 734 "lfs $rD, $src", LdStLFD, 735 [(set F4RC:$rD, (load iaddr:$src))]>; 736 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src), 737 "lfd $rD, $src", LdStLFD, 738 [(set F8RC:$rD, (load iaddr:$src))]>; 739 740 741 // Unindexed (r+i) Loads with Update (preinc). 742 let mayLoad = 1 in { 743 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 744 "lbzu $rD, $addr", LdStLoadUpd, 745 []>, RegConstraint<"$addr.reg = $ea_result">, 746 NoEncode<"$ea_result">; 747 748 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 749 "lhau $rD, $addr", LdStLHAU, 750 []>, RegConstraint<"$addr.reg = $ea_result">, 751 NoEncode<"$ea_result">; 752 753 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 754 "lhzu $rD, $addr", LdStLoadUpd, 755 []>, RegConstraint<"$addr.reg = $ea_result">, 756 NoEncode<"$ea_result">; 757 758 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 759 "lwzu $rD, $addr", LdStLoadUpd, 760 []>, RegConstraint<"$addr.reg = $ea_result">, 761 NoEncode<"$ea_result">; 762 763 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 764 "lfsu $rD, $addr", LdStLFDU, 765 []>, RegConstraint<"$addr.reg = $ea_result">, 766 NoEncode<"$ea_result">; 767 768 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 769 "lfdu $rD, $addr", LdStLFDU, 770 []>, RegConstraint<"$addr.reg = $ea_result">, 771 NoEncode<"$ea_result">; 772 773 774 // Indexed (r+r) Loads with Update (preinc). 775 def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc:$ea_result), 776 (ins memrr:$addr), 777 "lbzux $rD, $addr", LdStLoadUpd, 778 []>, RegConstraint<"$addr.offreg = $ea_result">, 779 NoEncode<"$ea_result">; 780 781 def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc:$ea_result), 782 (ins memrr:$addr), 783 "lhaux $rD, $addr", LdStLHAU, 784 []>, RegConstraint<"$addr.offreg = $ea_result">, 785 NoEncode<"$ea_result">; 786 787 def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc:$ea_result), 788 (ins memrr:$addr), 789 "lhzux $rD, $addr", LdStLoadUpd, 790 []>, RegConstraint<"$addr.offreg = $ea_result">, 791 NoEncode<"$ea_result">; 792 793 def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc:$ea_result), 794 (ins memrr:$addr), 795 "lwzux $rD, $addr", LdStLoadUpd, 796 []>, RegConstraint<"$addr.offreg = $ea_result">, 797 NoEncode<"$ea_result">; 798 799 def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc:$ea_result), 800 (ins memrr:$addr), 801 "lfsux $rD, $addr", LdStLFDU, 802 []>, RegConstraint<"$addr.offreg = $ea_result">, 803 NoEncode<"$ea_result">; 804 805 def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc:$ea_result), 806 (ins memrr:$addr), 807 "lfdux $rD, $addr", LdStLFDU, 808 []>, RegConstraint<"$addr.offreg = $ea_result">, 809 NoEncode<"$ea_result">; 810 } 811 } 812 813 // Indexed (r+r) Loads. 814 // 815 let canFoldAsLoad = 1, PPC970_Unit = 2 in { 816 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), 817 "lbzx $rD, $src", LdStLoad, 818 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; 819 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src), 820 "lhax $rD, $src", LdStLHA, 821 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, 822 PPC970_DGroup_Cracked; 823 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src), 824 "lhzx $rD, $src", LdStLoad, 825 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; 826 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src), 827 "lwzx $rD, $src", LdStLoad, 828 [(set GPRC:$rD, (load xaddr:$src))]>; 829 830 831 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src), 832 "lhbrx $rD, $src", LdStLoad, 833 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>; 834 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src), 835 "lwbrx $rD, $src", LdStLoad, 836 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>; 837 838 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src), 839 "lfsx $frD, $src", LdStLFD, 840 [(set F4RC:$frD, (load xaddr:$src))]>; 841 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src), 842 "lfdx $frD, $src", LdStLFD, 843 [(set F8RC:$frD, (load xaddr:$src))]>; 844 } 845 846 //===----------------------------------------------------------------------===// 847 // PPC32 Store Instructions. 848 // 849 850 // Unindexed (r+i) Stores. 851 let PPC970_Unit = 2 in { 852 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src), 853 "stb $rS, $src", LdStStore, 854 [(truncstorei8 GPRC:$rS, iaddr:$src)]>; 855 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src), 856 "sth $rS, $src", LdStStore, 857 [(truncstorei16 GPRC:$rS, iaddr:$src)]>; 858 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src), 859 "stw $rS, $src", LdStStore, 860 [(store GPRC:$rS, iaddr:$src)]>; 861 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst), 862 "stfs $rS, $dst", LdStSTFD, 863 [(store F4RC:$rS, iaddr:$dst)]>; 864 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst), 865 "stfd $rS, $dst", LdStSTFD, 866 [(store F8RC:$rS, iaddr:$dst)]>; 867 } 868 869 // Unindexed (r+i) Stores with Update (preinc). 870 let PPC970_Unit = 2 in { 871 def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 872 symbolLo:$ptroff, ptr_rc:$ptrreg), 873 "stbu $rS, $ptroff($ptrreg)", LdStStoreUpd, 874 [(set ptr_rc:$ea_res, 875 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, 876 iaddroff:$ptroff))]>, 877 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 878 def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 879 symbolLo:$ptroff, ptr_rc:$ptrreg), 880 "sthu $rS, $ptroff($ptrreg)", LdStStoreUpd, 881 [(set ptr_rc:$ea_res, 882 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, 883 iaddroff:$ptroff))]>, 884 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 885 def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 886 symbolLo:$ptroff, ptr_rc:$ptrreg), 887 "stwu $rS, $ptroff($ptrreg)", LdStStoreUpd, 888 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg, 889 iaddroff:$ptroff))]>, 890 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 891 def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS, 892 symbolLo:$ptroff, ptr_rc:$ptrreg), 893 "stfsu $rS, $ptroff($ptrreg)", LdStSTFDU, 894 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg, 895 iaddroff:$ptroff))]>, 896 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 897 def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS, 898 symbolLo:$ptroff, ptr_rc:$ptrreg), 899 "stfdu $rS, $ptroff($ptrreg)", LdStSTFDU, 900 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg, 901 iaddroff:$ptroff))]>, 902 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 903 } 904 905 906 // Indexed (r+r) Stores. 907 // 908 let PPC970_Unit = 2 in { 909 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst), 910 "stbx $rS, $dst", LdStStore, 911 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, 912 PPC970_DGroup_Cracked; 913 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst), 914 "sthx $rS, $dst", LdStStore, 915 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, 916 PPC970_DGroup_Cracked; 917 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst), 918 "stwx $rS, $dst", LdStStore, 919 [(store GPRC:$rS, xaddr:$dst)]>, 920 PPC970_DGroup_Cracked; 921 922 def STBUX : XForm_8<31, 247, (outs ptr_rc:$ea_res), 923 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 924 "stbux $rS, $ptroff, $ptrreg", LdStStoreUpd, 925 [(set ptr_rc:$ea_res, 926 (pre_truncsti8 GPRC:$rS, 927 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 928 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 929 PPC970_DGroup_Cracked; 930 931 def STHUX : XForm_8<31, 439, (outs ptr_rc:$ea_res), 932 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 933 "sthux $rS, $ptroff, $ptrreg", LdStStoreUpd, 934 [(set ptr_rc:$ea_res, 935 (pre_truncsti16 GPRC:$rS, 936 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 937 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 938 PPC970_DGroup_Cracked; 939 940 def STWUX : XForm_8<31, 183, (outs ptr_rc:$ea_res), 941 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 942 "stwux $rS, $ptroff, $ptrreg", LdStStoreUpd, 943 [(set ptr_rc:$ea_res, 944 (pre_store GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 945 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 946 PPC970_DGroup_Cracked; 947 948 def STFSUX : XForm_8<31, 695, (outs ptr_rc:$ea_res), 949 (ins F4RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 950 "stfsux $rS, $ptroff, $ptrreg", LdStSTFDU, 951 [(set ptr_rc:$ea_res, 952 (pre_store F4RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 953 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 954 PPC970_DGroup_Cracked; 955 956 def STFDUX : XForm_8<31, 759, (outs ptr_rc:$ea_res), 957 (ins F8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 958 "stfdux $rS, $ptroff, $ptrreg", LdStSTFDU, 959 [(set ptr_rc:$ea_res, 960 (pre_store F8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 961 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 962 PPC970_DGroup_Cracked; 963 964 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst), 965 "sthbrx $rS, $dst", LdStStore, 966 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>, 967 PPC970_DGroup_Cracked; 968 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst), 969 "stwbrx $rS, $dst", LdStStore, 970 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>, 971 PPC970_DGroup_Cracked; 972 973 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst), 974 "stfiwx $frS, $dst", LdStSTFD, 975 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 976 977 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst), 978 "stfsx $frS, $dst", LdStSTFD, 979 [(store F4RC:$frS, xaddr:$dst)]>; 980 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst), 981 "stfdx $frS, $dst", LdStSTFD, 982 [(store F8RC:$frS, xaddr:$dst)]>; 983 } 984 985 def SYNC : XForm_24_sync<31, 598, (outs), (ins), 986 "sync", LdStSync, 987 [(int_ppc_sync)]>; 988 989 //===----------------------------------------------------------------------===// 990 // PPC32 Arithmetic Instructions. 991 // 992 993 let PPC970_Unit = 1 in { // FXU Operations. 994 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 995 "addi $rD, $rA, $imm", IntSimple, 996 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 997 def ADDIL : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$imm), 998 "addi $rD, $rA, $imm", IntSimple, 999 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 1000 let Defs = [CARRY] in { 1001 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 1002 "addic $rD, $rA, $imm", IntGeneral, 1003 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 1004 PPC970_DGroup_Cracked; 1005 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 1006 "addic. $rD, $rA, $imm", IntGeneral, 1007 []>; 1008 } 1009 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm), 1010 "addis $rD, $rA, $imm", IntSimple, 1011 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>; 1012 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym), 1013 "la $rD, $sym($rA)", IntGeneral, 1014 [(set GPRC:$rD, (add GPRC:$rA, 1015 (PPClo tglobaladdr:$sym, 0)))]>; 1016 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 1017 "mulli $rD, $rA, $imm", IntMulLI, 1018 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 1019 let Defs = [CARRY] in { 1020 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 1021 "subfic $rD, $rA, $imm", IntGeneral, 1022 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 1023 } 1024 1025 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 1026 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), 1027 "li $rD, $imm", IntSimple, 1028 [(set GPRC:$rD, immSExt16:$imm)]>; 1029 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), 1030 "lis $rD, $imm", IntSimple, 1031 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; 1032 } 1033 } 1034 1035 let PPC970_Unit = 1 in { // FXU Operations. 1036 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1037 "andi. $dst, $src1, $src2", IntGeneral, 1038 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 1039 isDOT; 1040 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1041 "andis. $dst, $src1, $src2", IntGeneral, 1042 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, 1043 isDOT; 1044 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1045 "ori $dst, $src1, $src2", IntSimple, 1046 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 1047 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1048 "oris $dst, $src1, $src2", IntSimple, 1049 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; 1050 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1051 "xori $dst, $src1, $src2", IntSimple, 1052 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 1053 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1054 "xoris $dst, $src1, $src2", IntSimple, 1055 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; 1056 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple, 1057 []>; 1058 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm), 1059 "cmpwi $crD, $rA, $imm", IntCompare>; 1060 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1061 "cmplwi $dst, $src1, $src2", IntCompare>; 1062 } 1063 1064 1065 let PPC970_Unit = 1 in { // FXU Operations. 1066 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1067 "nand $rA, $rS, $rB", IntSimple, 1068 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 1069 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1070 "and $rA, $rS, $rB", IntSimple, 1071 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 1072 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1073 "andc $rA, $rS, $rB", IntSimple, 1074 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 1075 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1076 "or $rA, $rS, $rB", IntSimple, 1077 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 1078 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1079 "nor $rA, $rS, $rB", IntSimple, 1080 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 1081 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1082 "orc $rA, $rS, $rB", IntSimple, 1083 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 1084 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1085 "eqv $rA, $rS, $rB", IntSimple, 1086 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 1087 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1088 "xor $rA, $rS, $rB", IntSimple, 1089 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 1090 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1091 "slw $rA, $rS, $rB", IntGeneral, 1092 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 1093 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1094 "srw $rA, $rS, $rB", IntGeneral, 1095 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 1096 let Defs = [CARRY] in { 1097 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1098 "sraw $rA, $rS, $rB", IntShift, 1099 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 1100 } 1101 } 1102 1103 let PPC970_Unit = 1 in { // FXU Operations. 1104 let Defs = [CARRY] in { 1105 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH), 1106 "srawi $rA, $rS, $SH", IntShift, 1107 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 1108 } 1109 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS), 1110 "cntlzw $rA, $rS", IntGeneral, 1111 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 1112 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS), 1113 "extsb $rA, $rS", IntSimple, 1114 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 1115 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS), 1116 "extsh $rA, $rS", IntSimple, 1117 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 1118 1119 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 1120 "cmpw $crD, $rA, $rB", IntCompare>; 1121 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 1122 "cmplw $crD, $rA, $rB", IntCompare>; 1123 } 1124 let PPC970_Unit = 3 in { // FPU Operations. 1125 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 1126 // "fcmpo $crD, $fA, $fB", FPCompare>; 1127 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB), 1128 "fcmpu $crD, $fA, $fB", FPCompare>; 1129 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB), 1130 "fcmpu $crD, $fA, $fB", FPCompare>; 1131 1132 let Uses = [RM] in { 1133 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB), 1134 "fctiwz $frD, $frB", FPGeneral, 1135 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 1136 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB), 1137 "frsp $frD, $frB", FPGeneral, 1138 [(set F4RC:$frD, (fround F8RC:$frB))]>; 1139 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB), 1140 "fsqrt $frD, $frB", FPSqrt, 1141 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 1142 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB), 1143 "fsqrts $frD, $frB", FPSqrt, 1144 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 1145 } 1146 } 1147 1148 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are 1149 /// often coalesced away and we don't want the dispatch group builder to think 1150 /// that they will fill slots (which could cause the load of a LSU reject to 1151 /// sneak into a d-group with a store). 1152 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB), 1153 "fmr $frD, $frB", FPGeneral, 1154 []>, // (set F4RC:$frD, F4RC:$frB) 1155 PPC970_Unit_Pseudo; 1156 1157 let PPC970_Unit = 3 in { // FPU Operations. 1158 // These are artificially split into two different forms, for 4/8 byte FP. 1159 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB), 1160 "fabs $frD, $frB", FPGeneral, 1161 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 1162 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB), 1163 "fabs $frD, $frB", FPGeneral, 1164 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 1165 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB), 1166 "fnabs $frD, $frB", FPGeneral, 1167 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 1168 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB), 1169 "fnabs $frD, $frB", FPGeneral, 1170 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 1171 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB), 1172 "fneg $frD, $frB", FPGeneral, 1173 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 1174 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB), 1175 "fneg $frD, $frB", FPGeneral, 1176 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 1177 } 1178 1179 1180 // XL-Form instructions. condition register logical ops. 1181 // 1182 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA), 1183 "mcrf $BF, $BFA", BrMCR>, 1184 PPC970_DGroup_First, PPC970_Unit_CRU; 1185 1186 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD), 1187 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1188 "creqv $CRD, $CRA, $CRB", BrCR, 1189 []>; 1190 1191 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD), 1192 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1193 "cror $CRD, $CRA, $CRB", BrCR, 1194 []>; 1195 1196 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins), 1197 "creqv $dst, $dst, $dst", BrCR, 1198 []>; 1199 1200 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins), 1201 "crxor $dst, $dst, $dst", BrCR, 1202 []>; 1203 1204 let Defs = [CR1EQ], CRD = 6 in { 1205 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 1206 "creqv 6, 6, 6", BrCR, 1207 [(PPCcr6set)]>; 1208 1209 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 1210 "crxor 6, 6, 6", BrCR, 1211 [(PPCcr6unset)]>; 1212 } 1213 1214 // XFX-Form instructions. Instructions that deal with SPRs. 1215 // 1216 let Uses = [CTR] in { 1217 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins), 1218 "mfctr $rT", SprMFSPR>, 1219 PPC970_DGroup_First, PPC970_Unit_FXU; 1220 } 1221 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in { 1222 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS), 1223 "mtctr $rS", SprMTSPR>, 1224 PPC970_DGroup_First, PPC970_Unit_FXU; 1225 } 1226 1227 let Defs = [LR] in { 1228 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS), 1229 "mtlr $rS", SprMTSPR>, 1230 PPC970_DGroup_First, PPC970_Unit_FXU; 1231 } 1232 let Uses = [LR] in { 1233 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins), 1234 "mflr $rT", SprMFSPR>, 1235 PPC970_DGroup_First, PPC970_Unit_FXU; 1236 } 1237 1238 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 1239 // a GPR on the PPC970. As such, copies in and out have the same performance 1240 // characteristics as an OR instruction. 1241 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS), 1242 "mtspr 256, $rS", IntGeneral>, 1243 PPC970_DGroup_Single, PPC970_Unit_FXU; 1244 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins), 1245 "mfspr $rT, 256", IntGeneral>, 1246 PPC970_DGroup_First, PPC970_Unit_FXU; 1247 1248 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS), 1249 "mtcrf $FXM, $rS", BrMCRX>, 1250 PPC970_MicroCode, PPC970_Unit_CRU; 1251 1252 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters; 1253 // declaring that here gives the local register allocator problems with this: 1254 // vreg = MCRF CR0 1255 // MFCR <kill of whatever preg got assigned to vreg> 1256 // while not declaring it breaks DeadMachineInstructionElimination. 1257 // As it turns out, in all cases where we currently use this, 1258 // we're only interested in one subregister of it. Represent this in the 1259 // instruction to keep the register allocator from becoming confused. 1260 // 1261 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC. 1262 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1263 "#MFCRpseud", SprMFCR>, 1264 PPC970_MicroCode, PPC970_Unit_CRU; 1265 1266 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), 1267 "mfcr $rT", SprMFCR>, 1268 PPC970_MicroCode, PPC970_Unit_CRU; 1269 1270 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1271 "mfocrf $rT, $FXM", SprMFCR>, 1272 PPC970_DGroup_First, PPC970_Unit_CRU; 1273 1274 // Instructions to manipulate FPSCR. Only long double handling uses these. 1275 // FPSCR is not modelled; we use the SDNode Flag to keep things in order. 1276 1277 let Uses = [RM], Defs = [RM] in { 1278 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 1279 "mtfsb0 $FM", IntMTFSB0, 1280 [(PPCmtfsb0 (i32 imm:$FM))]>, 1281 PPC970_DGroup_Single, PPC970_Unit_FPU; 1282 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 1283 "mtfsb1 $FM", IntMTFSB0, 1284 [(PPCmtfsb1 (i32 imm:$FM))]>, 1285 PPC970_DGroup_Single, PPC970_Unit_FPU; 1286 // MTFSF does not actually produce an FP result. We pretend it copies 1287 // input reg B to the output. If we didn't do this it would look like the 1288 // instruction had no outputs (because we aren't modelling the FPSCR) and 1289 // it would be deleted. 1290 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA), 1291 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB), 1292 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0, 1293 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM), 1294 F8RC:$rT, F8RC:$FRB))]>, 1295 PPC970_DGroup_Single, PPC970_Unit_FPU; 1296 } 1297 let Uses = [RM] in { 1298 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins), 1299 "mffs $rT", IntMFFS, 1300 [(set F8RC:$rT, (PPCmffs))]>, 1301 PPC970_DGroup_Single, PPC970_Unit_FPU; 1302 def FADDrtz: AForm_2<63, 21, 1303 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1304 "fadd $FRT, $FRA, $FRB", FPAddSub, 1305 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>, 1306 PPC970_DGroup_Single, PPC970_Unit_FPU; 1307 } 1308 1309 1310 let PPC970_Unit = 1 in { // FXU Operations. 1311 1312 // XO-Form instructions. Arithmetic instructions that can set overflow bit 1313 // 1314 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1315 "add $rT, $rA, $rB", IntSimple, 1316 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 1317 let Defs = [CARRY] in { 1318 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1319 "addc $rT, $rA, $rB", IntGeneral, 1320 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 1321 PPC970_DGroup_Cracked; 1322 } 1323 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1324 "divw $rT, $rA, $rB", IntDivW, 1325 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 1326 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1327 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1328 "divwu $rT, $rA, $rB", IntDivW, 1329 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 1330 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1331 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1332 "mulhw $rT, $rA, $rB", IntMulHW, 1333 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 1334 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1335 "mulhwu $rT, $rA, $rB", IntMulHWU, 1336 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 1337 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1338 "mullw $rT, $rA, $rB", IntMulHW, 1339 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 1340 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1341 "subf $rT, $rA, $rB", IntGeneral, 1342 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 1343 let Defs = [CARRY] in { 1344 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1345 "subfc $rT, $rA, $rB", IntGeneral, 1346 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 1347 PPC970_DGroup_Cracked; 1348 } 1349 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1350 "neg $rT, $rA", IntSimple, 1351 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 1352 let Uses = [CARRY], Defs = [CARRY] in { 1353 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1354 "adde $rT, $rA, $rB", IntGeneral, 1355 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 1356 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1357 "addme $rT, $rA", IntGeneral, 1358 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>; 1359 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1360 "addze $rT, $rA", IntGeneral, 1361 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 1362 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1363 "subfe $rT, $rA, $rB", IntGeneral, 1364 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 1365 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1366 "subfme $rT, $rA", IntGeneral, 1367 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>; 1368 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1369 "subfze $rT, $rA", IntGeneral, 1370 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 1371 } 1372 } 1373 1374 // A-Form instructions. Most of the instructions executed in the FPU are of 1375 // this type. 1376 // 1377 let PPC970_Unit = 3 in { // FPU Operations. 1378 let Uses = [RM] in { 1379 def FMADD : AForm_1<63, 29, 1380 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1381 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1382 [(set F8RC:$FRT, 1383 (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB))]>; 1384 def FMADDS : AForm_1<59, 29, 1385 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1386 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1387 [(set F4RC:$FRT, 1388 (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB))]>; 1389 def FMSUB : AForm_1<63, 28, 1390 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1391 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1392 [(set F8RC:$FRT, 1393 (fma F8RC:$FRA, F8RC:$FRC, (fneg F8RC:$FRB)))]>; 1394 def FMSUBS : AForm_1<59, 28, 1395 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1396 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1397 [(set F4RC:$FRT, 1398 (fma F4RC:$FRA, F4RC:$FRC, (fneg F4RC:$FRB)))]>; 1399 def FNMADD : AForm_1<63, 31, 1400 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1401 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1402 [(set F8RC:$FRT, 1403 (fneg (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB)))]>; 1404 def FNMADDS : AForm_1<59, 31, 1405 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1406 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1407 [(set F4RC:$FRT, 1408 (fneg (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB)))]>; 1409 def FNMSUB : AForm_1<63, 30, 1410 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1411 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1412 [(set F8RC:$FRT, (fneg (fma F8RC:$FRA, F8RC:$FRC, 1413 (fneg F8RC:$FRB))))]>; 1414 def FNMSUBS : AForm_1<59, 30, 1415 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1416 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1417 [(set F4RC:$FRT, (fneg (fma F4RC:$FRA, F4RC:$FRC, 1418 (fneg F4RC:$FRB))))]>; 1419 } 1420 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 1421 // having 4 of these, force the comparison to always be an 8-byte double (code 1422 // should use an FMRSD if the input comparison value really wants to be a float) 1423 // and 4/8 byte forms for the result and operand type.. 1424 def FSELD : AForm_1<63, 23, 1425 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1426 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1427 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 1428 def FSELS : AForm_1<63, 23, 1429 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1430 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1431 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 1432 let Uses = [RM] in { 1433 def FADD : AForm_2<63, 21, 1434 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1435 "fadd $FRT, $FRA, $FRB", FPAddSub, 1436 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 1437 def FADDS : AForm_2<59, 21, 1438 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1439 "fadds $FRT, $FRA, $FRB", FPGeneral, 1440 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 1441 def FDIV : AForm_2<63, 18, 1442 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1443 "fdiv $FRT, $FRA, $FRB", FPDivD, 1444 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 1445 def FDIVS : AForm_2<59, 18, 1446 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1447 "fdivs $FRT, $FRA, $FRB", FPDivS, 1448 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 1449 def FMUL : AForm_3<63, 25, 1450 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC), 1451 "fmul $FRT, $FRA, $FRC", FPFused, 1452 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRC))]>; 1453 def FMULS : AForm_3<59, 25, 1454 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC), 1455 "fmuls $FRT, $FRA, $FRC", FPGeneral, 1456 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRC))]>; 1457 def FSUB : AForm_2<63, 20, 1458 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1459 "fsub $FRT, $FRA, $FRB", FPAddSub, 1460 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 1461 def FSUBS : AForm_2<59, 20, 1462 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1463 "fsubs $FRT, $FRA, $FRB", FPGeneral, 1464 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 1465 } 1466 } 1467 1468 let PPC970_Unit = 1 in { // FXU Operations. 1469 def ISEL : AForm_4<31, 15, 1470 (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB, pred:$cond), 1471 "isel $rT, $rA, $rB, $cond", IntGeneral, 1472 []>; 1473 } 1474 1475 let PPC970_Unit = 1 in { // FXU Operations. 1476 // M-Form instructions. rotate and mask instructions. 1477 // 1478 let isCommutable = 1 in { 1479 // RLWIMI can be commuted if the rotate amount is zero. 1480 def RLWIMI : MForm_2<20, 1481 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 1482 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 1483 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, 1484 NoEncode<"$rSi">; 1485 } 1486 def RLWINM : MForm_2<21, 1487 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1488 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 1489 []>; 1490 def RLWINMo : MForm_2<21, 1491 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1492 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 1493 []>, isDOT, PPC970_DGroup_Cracked; 1494 def RLWNM : MForm_2<23, 1495 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 1496 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 1497 []>; 1498 } 1499 1500 1501 //===----------------------------------------------------------------------===// 1502 // PowerPC Instruction Patterns 1503 // 1504 1505 // Arbitrary immediate support. Implement in terms of LIS/ORI. 1506 def : Pat<(i32 imm:$imm), 1507 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 1508 1509 // Implement the 'not' operation with the NOR instruction. 1510 def NOT : Pat<(not GPRC:$in), 1511 (NOR GPRC:$in, GPRC:$in)>; 1512 1513 // ADD an arbitrary immediate. 1514 def : Pat<(add GPRC:$in, imm:$imm), 1515 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1516 // OR an arbitrary immediate. 1517 def : Pat<(or GPRC:$in, imm:$imm), 1518 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1519 // XOR an arbitrary immediate. 1520 def : Pat<(xor GPRC:$in, imm:$imm), 1521 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1522 // SUBFIC 1523 def : Pat<(sub immSExt16:$imm, GPRC:$in), 1524 (SUBFIC GPRC:$in, imm:$imm)>; 1525 1526 // SHL/SRL 1527 def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 1528 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1529 def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1530 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1531 1532 // ROTL 1533 def : Pat<(rotl GPRC:$in, GPRC:$sh), 1534 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1535 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1536 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1537 1538 // RLWNM 1539 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm), 1540 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 1541 1542 // Calls 1543 def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)), 1544 (BL_Darwin tglobaladdr:$dst)>; 1545 def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)), 1546 (BL_Darwin texternalsym:$dst)>; 1547 def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)), 1548 (BL_SVR4 tglobaladdr:$dst)>; 1549 def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)), 1550 (BL_SVR4 texternalsym:$dst)>; 1551 1552 1553 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 1554 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 1555 1556 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 1557 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 1558 1559 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 1560 (TCRETURNri CTRRC:$dst, imm:$imm)>; 1561 1562 1563 1564 // Hi and Lo for Darwin Global Addresses. 1565 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1566 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1567 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1568 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1569 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 1570 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 1571 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 1572 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 1573 def : Pat<(PPChi tglobaltlsaddr:$g, GPRC:$in), 1574 (ADDIS GPRC:$in, tglobaltlsaddr:$g)>; 1575 def : Pat<(PPClo tglobaltlsaddr:$g, GPRC:$in), 1576 (ADDIL GPRC:$in, tglobaltlsaddr:$g)>; 1577 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1578 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1579 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1580 (ADDIS GPRC:$in, tconstpool:$g)>; 1581 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)), 1582 (ADDIS GPRC:$in, tjumptable:$g)>; 1583 def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)), 1584 (ADDIS GPRC:$in, tblockaddress:$g)>; 1585 1586 // Standard shifts. These are represented separately from the real shifts above 1587 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1588 // amounts. 1589 def : Pat<(sra GPRC:$rS, GPRC:$rB), 1590 (SRAW GPRC:$rS, GPRC:$rB)>; 1591 def : Pat<(srl GPRC:$rS, GPRC:$rB), 1592 (SRW GPRC:$rS, GPRC:$rB)>; 1593 def : Pat<(shl GPRC:$rS, GPRC:$rB), 1594 (SLW GPRC:$rS, GPRC:$rB)>; 1595 1596 def : Pat<(zextloadi1 iaddr:$src), 1597 (LBZ iaddr:$src)>; 1598 def : Pat<(zextloadi1 xaddr:$src), 1599 (LBZX xaddr:$src)>; 1600 def : Pat<(extloadi1 iaddr:$src), 1601 (LBZ iaddr:$src)>; 1602 def : Pat<(extloadi1 xaddr:$src), 1603 (LBZX xaddr:$src)>; 1604 def : Pat<(extloadi8 iaddr:$src), 1605 (LBZ iaddr:$src)>; 1606 def : Pat<(extloadi8 xaddr:$src), 1607 (LBZX xaddr:$src)>; 1608 def : Pat<(extloadi16 iaddr:$src), 1609 (LHZ iaddr:$src)>; 1610 def : Pat<(extloadi16 xaddr:$src), 1611 (LHZX xaddr:$src)>; 1612 def : Pat<(f64 (extloadf32 iaddr:$src)), 1613 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 1614 def : Pat<(f64 (extloadf32 xaddr:$src)), 1615 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 1616 1617 def : Pat<(f64 (fextend F4RC:$src)), 1618 (COPY_TO_REGCLASS F4RC:$src, F8RC)>; 1619 1620 // Memory barriers 1621 def : Pat<(membarrier (i32 imm /*ll*/), 1622 (i32 imm /*ls*/), 1623 (i32 imm /*sl*/), 1624 (i32 imm /*ss*/), 1625 (i32 imm /*device*/)), 1626 (SYNC)>; 1627 1628 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>; 1629 1630 include "PPCInstrAltivec.td" 1631 include "PPCInstr64Bit.td" 1632
