1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the PPC specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCSubtarget.h" 15 #include "PPC.h" 16 #include "PPCRegisterInfo.h" 17 #include "llvm/IR/GlobalValue.h" 18 #include "llvm/Support/Host.h" 19 #include "llvm/Support/TargetRegistry.h" 20 #include "llvm/Target/TargetMachine.h" 21 #include <cstdlib> 22 23 #define GET_SUBTARGETINFO_TARGET_DESC 24 #define GET_SUBTARGETINFO_CTOR 25 #include "PPCGenSubtargetInfo.inc" 26 27 using namespace llvm; 28 29 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, 30 const std::string &FS, bool is64Bit) 31 : PPCGenSubtargetInfo(TT, CPU, FS) 32 , StackAlignment(16) 33 , DarwinDirective(PPC::DIR_NONE) 34 , HasMFOCRF(false) 35 , Has64BitSupport(false) 36 , Use64BitRegs(false) 37 , IsPPC64(is64Bit) 38 , HasAltivec(false) 39 , HasQPX(false) 40 , HasFSQRT(false) 41 , HasSTFIWX(false) 42 , HasISEL(false) 43 , IsBookE(false) 44 , HasLazyResolverStubs(false) 45 , IsJITCodeModel(false) 46 , TargetTriple(TT) { 47 48 // Determine default and user specified characteristics 49 std::string CPUName = CPU; 50 if (CPUName.empty()) 51 CPUName = "generic"; 52 #if (defined(__APPLE__) || defined(__linux__)) && \ 53 (defined(__ppc__) || defined(__powerpc__)) 54 if (CPUName == "generic") 55 CPUName = sys::getHostCPUName(); 56 #endif 57 58 // Initialize scheduling itinerary for the specified CPU. 59 InstrItins = getInstrItineraryForCPU(CPUName); 60 61 // Make sure 64-bit features are available when CPUname is generic 62 std::string FullFS = FS; 63 64 // If we are generating code for ppc64, verify that options make sense. 65 if (is64Bit) { 66 Has64BitSupport = true; 67 // Silently force 64-bit register use on ppc64. 68 Use64BitRegs = true; 69 if (!FullFS.empty()) 70 FullFS = "+64bit," + FullFS; 71 else 72 FullFS = "+64bit"; 73 } 74 75 // Parse features string. 76 ParseSubtargetFeatures(CPUName, FullFS); 77 78 // If the user requested use of 64-bit regs, but the cpu selected doesn't 79 // support it, ignore. 80 if (use64BitRegs() && !has64BitSupport()) 81 Use64BitRegs = false; 82 83 // Set up darwin-specific properties. 84 if (isDarwin()) 85 HasLazyResolverStubs = true; 86 87 // QPX requires a 32-byte aligned stack. Note that we need to do this if 88 // we're compiling for a BG/Q system regardless of whether or not QPX 89 // is enabled because external functions will assume this alignment. 90 if (hasQPX() || isBGQ()) 91 StackAlignment = 32; 92 } 93 94 /// SetJITMode - This is called to inform the subtarget info that we are 95 /// producing code for the JIT. 96 void PPCSubtarget::SetJITMode() { 97 // JIT mode doesn't want lazy resolver stubs, it knows exactly where 98 // everything is. This matters for PPC64, which codegens in PIC mode without 99 // stubs. 100 HasLazyResolverStubs = false; 101 102 // Calls to external functions need to use indirect calls 103 IsJITCodeModel = true; 104 } 105 106 107 /// hasLazyResolverStub - Return true if accesses to the specified global have 108 /// to go through a dyld lazy resolution stub. This means that an extra load 109 /// is required to get the address of the global. 110 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV, 111 const TargetMachine &TM) const { 112 // We never have stubs if HasLazyResolverStubs=false or if in static mode. 113 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static) 114 return false; 115 // If symbol visibility is hidden, the extra load is not needed if 116 // the symbol is definitely defined in the current translation unit. 117 bool isDecl = GV->isDeclaration() && !GV->isMaterializable(); 118 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage()) 119 return false; 120 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 121 GV->hasCommonLinkage() || isDecl; 122 } 123 124 bool PPCSubtarget::enablePostRAScheduler( 125 CodeGenOpt::Level OptLevel, 126 TargetSubtargetInfo::AntiDepBreakMode& Mode, 127 RegClassVector& CriticalPathRCs) const { 128 // FIXME: It would be best to use TargetSubtargetInfo::ANTIDEP_ALL here, 129 // but we can't because we can't reassign the cr registers. There is a 130 // dependence between the cr register and the RLWINM instruction used 131 // to extract its value which the anti-dependency breaker can't currently 132 // see. Maybe we should make a late-expanded pseudo to encode this dependency. 133 // (the relevant code is in PPCDAGToDAGISel::SelectSETCC) 134 135 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL; 136 137 CriticalPathRCs.clear(); 138 139 if (isPPC64()) 140 CriticalPathRCs.push_back(&PPC::G8RCRegClass); 141 else 142 CriticalPathRCs.push_back(&PPC::GPRCRegClass); 143 144 CriticalPathRCs.push_back(&PPC::F8RCRegClass); 145 CriticalPathRCs.push_back(&PPC::VRRCRegClass); 146 147 return OptLevel >= CodeGenOpt::Default; 148 } 149 150
