1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // SI Instruction format definitions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> : 15 AMDGPUInst<outs, ins, asm, pattern> { 16 17 field bits<1> VM_CNT = 0; 18 field bits<1> EXP_CNT = 0; 19 field bits<1> LGKM_CNT = 0; 20 21 let TSFlags{0} = VM_CNT; 22 let TSFlags{1} = EXP_CNT; 23 let TSFlags{2} = LGKM_CNT; 24 } 25 26 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> : 27 InstSI <outs, ins, asm, pattern> { 28 29 field bits<32> Inst; 30 let Size = 4; 31 } 32 33 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> : 34 InstSI <outs, ins, asm, pattern> { 35 36 field bits<64> Inst; 37 let Size = 8; 38 } 39 40 //===----------------------------------------------------------------------===// 41 // Scalar operations 42 //===----------------------------------------------------------------------===// 43 44 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : 45 Enc32<outs, ins, asm, pattern> { 46 47 bits<7> SDST; 48 bits<8> SSRC0; 49 50 let Inst{7-0} = SSRC0; 51 let Inst{15-8} = op; 52 let Inst{22-16} = SDST; 53 let Inst{31-23} = 0x17d; //encoding; 54 55 let mayLoad = 0; 56 let mayStore = 0; 57 let hasSideEffects = 0; 58 } 59 60 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 61 Enc32 <outs, ins, asm, pattern> { 62 63 bits<7> SDST; 64 bits<8> SSRC0; 65 bits<8> SSRC1; 66 67 let Inst{7-0} = SSRC0; 68 let Inst{15-8} = SSRC1; 69 let Inst{22-16} = SDST; 70 let Inst{29-23} = op; 71 let Inst{31-30} = 0x2; // encoding 72 73 let mayLoad = 0; 74 let mayStore = 0; 75 let hasSideEffects = 0; 76 } 77 78 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 79 Enc32<outs, ins, asm, pattern> { 80 81 bits<8> SSRC0; 82 bits<8> SSRC1; 83 84 let Inst{7-0} = SSRC0; 85 let Inst{15-8} = SSRC1; 86 let Inst{22-16} = op; 87 let Inst{31-23} = 0x17e; 88 89 let DisableEncoding = "$dst"; 90 let mayLoad = 0; 91 let mayStore = 0; 92 let hasSideEffects = 0; 93 } 94 95 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> : 96 Enc32 <outs, ins , asm, pattern> { 97 98 bits <7> SDST; 99 bits <16> SIMM16; 100 101 let Inst{15-0} = SIMM16; 102 let Inst{22-16} = SDST; 103 let Inst{27-23} = op; 104 let Inst{31-28} = 0xb; //encoding 105 106 let mayLoad = 0; 107 let mayStore = 0; 108 let hasSideEffects = 0; 109 } 110 111 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 < 112 (outs), 113 ins, 114 asm, 115 pattern > { 116 117 bits <16> SIMM16; 118 119 let Inst{15-0} = SIMM16; 120 let Inst{22-16} = op; 121 let Inst{31-23} = 0x17f; // encoding 122 123 let mayLoad = 0; 124 let mayStore = 0; 125 let hasSideEffects = 0; 126 } 127 128 class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm, 129 list<dag> pattern> : Enc32<outs, ins, asm, pattern> { 130 131 bits<7> SDST; 132 bits<7> SBASE; 133 bits<8> OFFSET; 134 135 let Inst{7-0} = OFFSET; 136 let Inst{8} = imm; 137 let Inst{14-9} = SBASE{6-1}; 138 let Inst{21-15} = SDST; 139 let Inst{26-22} = op; 140 let Inst{31-27} = 0x18; //encoding 141 142 let LGKM_CNT = 1; 143 } 144 145 //===----------------------------------------------------------------------===// 146 // Vector ALU operations 147 //===----------------------------------------------------------------------===// 148 149 let Uses = [EXEC] in { 150 151 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : 152 Enc32 <outs, ins, asm, pattern> { 153 154 bits<8> VDST; 155 bits<9> SRC0; 156 157 let Inst{8-0} = SRC0; 158 let Inst{16-9} = op; 159 let Inst{24-17} = VDST; 160 let Inst{31-25} = 0x3f; //encoding 161 162 let mayLoad = 0; 163 let mayStore = 0; 164 let hasSideEffects = 0; 165 } 166 167 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> : 168 Enc32 <outs, ins, asm, pattern> { 169 170 bits<8> VDST; 171 bits<9> SRC0; 172 bits<8> VSRC1; 173 174 let Inst{8-0} = SRC0; 175 let Inst{16-9} = VSRC1; 176 let Inst{24-17} = VDST; 177 let Inst{30-25} = op; 178 let Inst{31} = 0x0; //encoding 179 180 let mayLoad = 0; 181 let mayStore = 0; 182 let hasSideEffects = 0; 183 } 184 185 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> : 186 Enc64 <outs, ins, asm, pattern> { 187 188 bits<8> VDST; 189 bits<9> SRC0; 190 bits<9> SRC1; 191 bits<9> SRC2; 192 bits<3> ABS; 193 bits<1> CLAMP; 194 bits<2> OMOD; 195 bits<3> NEG; 196 197 let Inst{7-0} = VDST; 198 let Inst{10-8} = ABS; 199 let Inst{11} = CLAMP; 200 let Inst{25-17} = op; 201 let Inst{31-26} = 0x34; //encoding 202 let Inst{40-32} = SRC0; 203 let Inst{49-41} = SRC1; 204 let Inst{58-50} = SRC2; 205 let Inst{60-59} = OMOD; 206 let Inst{63-61} = NEG; 207 208 let mayLoad = 0; 209 let mayStore = 0; 210 let hasSideEffects = 0; 211 } 212 213 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> : 214 Enc64 <outs, ins, asm, pattern> { 215 216 bits<8> VDST; 217 bits<9> SRC0; 218 bits<9> SRC1; 219 bits<9> SRC2; 220 bits<7> SDST; 221 bits<2> OMOD; 222 bits<3> NEG; 223 224 let Inst{7-0} = VDST; 225 let Inst{14-8} = SDST; 226 let Inst{25-17} = op; 227 let Inst{31-26} = 0x34; //encoding 228 let Inst{40-32} = SRC0; 229 let Inst{49-41} = SRC1; 230 let Inst{58-50} = SRC2; 231 let Inst{60-59} = OMOD; 232 let Inst{63-61} = NEG; 233 234 let mayLoad = 0; 235 let mayStore = 0; 236 let hasSideEffects = 0; 237 } 238 239 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> : 240 Enc32 <(outs VCCReg:$dst), ins, asm, pattern> { 241 242 bits<9> SRC0; 243 bits<8> VSRC1; 244 245 let Inst{8-0} = SRC0; 246 let Inst{16-9} = VSRC1; 247 let Inst{24-17} = op; 248 let Inst{31-25} = 0x3e; 249 250 let DisableEncoding = "$dst"; 251 let mayLoad = 0; 252 let mayStore = 0; 253 let hasSideEffects = 0; 254 } 255 256 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> : 257 Enc32 <outs, ins, asm, pattern> { 258 259 bits<8> VDST; 260 bits<8> VSRC; 261 bits<2> ATTRCHAN; 262 bits<6> ATTR; 263 264 let Inst{7-0} = VSRC; 265 let Inst{9-8} = ATTRCHAN; 266 let Inst{15-10} = ATTR; 267 let Inst{17-16} = op; 268 let Inst{25-18} = VDST; 269 let Inst{31-26} = 0x32; // encoding 270 271 let neverHasSideEffects = 1; 272 let mayLoad = 1; 273 let mayStore = 0; 274 } 275 276 } // End Uses = [EXEC] 277 278 //===----------------------------------------------------------------------===// 279 // Vector I/O operations 280 //===----------------------------------------------------------------------===// 281 282 let Uses = [EXEC] in { 283 284 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 285 Enc64<outs, ins, asm, pattern> { 286 287 bits<8> VDATA; 288 bits<12> OFFSET; 289 bits<1> OFFEN; 290 bits<1> IDXEN; 291 bits<1> GLC; 292 bits<1> ADDR64; 293 bits<1> LDS; 294 bits<8> VADDR; 295 bits<7> SRSRC; 296 bits<1> SLC; 297 bits<1> TFE; 298 bits<8> SOFFSET; 299 300 let Inst{11-0} = OFFSET; 301 let Inst{12} = OFFEN; 302 let Inst{13} = IDXEN; 303 let Inst{14} = GLC; 304 let Inst{15} = ADDR64; 305 let Inst{16} = LDS; 306 let Inst{24-18} = op; 307 let Inst{31-26} = 0x38; //encoding 308 let Inst{39-32} = VADDR; 309 let Inst{47-40} = VDATA; 310 let Inst{52-48} = SRSRC{6-2}; 311 let Inst{54} = SLC; 312 let Inst{55} = TFE; 313 let Inst{63-56} = SOFFSET; 314 315 let VM_CNT = 1; 316 let EXP_CNT = 1; 317 318 let neverHasSideEffects = 1; 319 } 320 321 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> : 322 Enc64<outs, ins, asm, pattern> { 323 324 bits<8> VDATA; 325 bits<12> OFFSET; 326 bits<1> OFFEN; 327 bits<1> IDXEN; 328 bits<1> GLC; 329 bits<1> ADDR64; 330 bits<4> DFMT; 331 bits<3> NFMT; 332 bits<8> VADDR; 333 bits<7> SRSRC; 334 bits<1> SLC; 335 bits<1> TFE; 336 bits<8> SOFFSET; 337 338 let Inst{11-0} = OFFSET; 339 let Inst{12} = OFFEN; 340 let Inst{13} = IDXEN; 341 let Inst{14} = GLC; 342 let Inst{15} = ADDR64; 343 let Inst{18-16} = op; 344 let Inst{22-19} = DFMT; 345 let Inst{25-23} = NFMT; 346 let Inst{31-26} = 0x3a; //encoding 347 let Inst{39-32} = VADDR; 348 let Inst{47-40} = VDATA; 349 let Inst{52-48} = SRSRC{6-2}; 350 let Inst{54} = SLC; 351 let Inst{55} = TFE; 352 let Inst{63-56} = SOFFSET; 353 354 let VM_CNT = 1; 355 let EXP_CNT = 1; 356 357 let neverHasSideEffects = 1; 358 } 359 360 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 361 Enc64 <outs, ins, asm, pattern> { 362 363 bits<8> VDATA; 364 bits<4> DMASK; 365 bits<1> UNORM; 366 bits<1> GLC; 367 bits<1> DA; 368 bits<1> R128; 369 bits<1> TFE; 370 bits<1> LWE; 371 bits<1> SLC; 372 bits<8> VADDR; 373 bits<7> SRSRC; 374 bits<7> SSAMP; 375 376 let Inst{11-8} = DMASK; 377 let Inst{12} = UNORM; 378 let Inst{13} = GLC; 379 let Inst{14} = DA; 380 let Inst{15} = R128; 381 let Inst{16} = TFE; 382 let Inst{17} = LWE; 383 let Inst{24-18} = op; 384 let Inst{25} = SLC; 385 let Inst{31-26} = 0x3c; 386 let Inst{39-32} = VADDR; 387 let Inst{47-40} = VDATA; 388 let Inst{52-48} = SRSRC{6-2}; 389 let Inst{57-53} = SSAMP{6-2}; 390 391 let VM_CNT = 1; 392 let EXP_CNT = 1; 393 } 394 395 def EXP : Enc64< 396 (outs), 397 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm, 398 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3), 399 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3", 400 [] > { 401 402 bits<4> EN; 403 bits<6> TGT; 404 bits<1> COMPR; 405 bits<1> DONE; 406 bits<1> VM; 407 bits<8> VSRC0; 408 bits<8> VSRC1; 409 bits<8> VSRC2; 410 bits<8> VSRC3; 411 412 let Inst{3-0} = EN; 413 let Inst{9-4} = TGT; 414 let Inst{10} = COMPR; 415 let Inst{11} = DONE; 416 let Inst{12} = VM; 417 let Inst{31-26} = 0x3e; 418 let Inst{39-32} = VSRC0; 419 let Inst{47-40} = VSRC1; 420 let Inst{55-48} = VSRC2; 421 let Inst{63-56} = VSRC3; 422 423 let EXP_CNT = 1; 424 } 425 426 } // End Uses = [EXEC] 427
