1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides pattern fragments useful for SIMD instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // MMX Pattern Fragments 16 //===----------------------------------------------------------------------===// 17 18 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>; 19 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>; 20 21 //===----------------------------------------------------------------------===// 22 // SSE specific DAG Nodes. 23 //===----------------------------------------------------------------------===// 24 25 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>, 26 SDTCisFP<0>, SDTCisInt<2> ]>; 27 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, 28 SDTCisFP<1>, SDTCisVT<3, i8>]>; 29 30 def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>; 31 def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>; 32 def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>; 33 def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>; 34 35 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>; 36 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>; 37 38 // Commutative and Associative FMIN and FMAX. 39 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp, 40 [SDNPCommutative, SDNPAssociative]>; 41 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp, 42 [SDNPCommutative, SDNPAssociative]>; 43 44 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, 45 [SDNPCommutative, SDNPAssociative]>; 46 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp, 47 [SDNPCommutative, SDNPAssociative]>; 48 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, 49 [SDNPCommutative, SDNPAssociative]>; 50 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; 51 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; 52 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>; 53 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>; 54 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>; 55 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>; 56 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>; 57 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>; 58 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; 59 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; 60 def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>; 61 def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>; 62 def X86pshufb : SDNode<"X86ISD::PSHUFB", 63 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 64 SDTCisSameAs<0,2>]>>; 65 def X86andnp : SDNode<"X86ISD::ANDNP", 66 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 67 SDTCisSameAs<0,2>]>>; 68 def X86psign : SDNode<"X86ISD::PSIGN", 69 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 70 SDTCisSameAs<0,2>]>>; 71 def X86pextrb : SDNode<"X86ISD::PEXTRB", 72 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; 73 def X86pextrw : SDNode<"X86ISD::PEXTRW", 74 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; 75 def X86pinsrb : SDNode<"X86ISD::PINSRB", 76 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 77 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 78 def X86pinsrw : SDNode<"X86ISD::PINSRW", 79 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, 80 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 81 def X86insrtps : SDNode<"X86ISD::INSERTPS", 82 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, 83 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>; 84 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", 85 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; 86 87 def X86vzmovly : SDNode<"X86ISD::VZEXT_MOVL", 88 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 89 SDTCisOpSmallerThanOp<1, 0> ]>>; 90 91 def X86vsmovl : SDNode<"X86ISD::VSEXT_MOVL", 92 SDTypeProfile<1, 1, 93 [SDTCisVec<0>, SDTCisInt<1>, SDTCisInt<0>]>>; 94 95 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, 96 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 97 98 def X86vzext : SDNode<"X86ISD::VZEXT", 99 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 100 SDTCisInt<0>, SDTCisInt<1>]>>; 101 102 def X86vsext : SDNode<"X86ISD::VSEXT", 103 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 104 SDTCisInt<0>, SDTCisInt<1>]>>; 105 106 def X86vfpext : SDNode<"X86ISD::VFPEXT", 107 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 108 SDTCisFP<0>, SDTCisFP<1>]>>; 109 def X86vfpround: SDNode<"X86ISD::VFPROUND", 110 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 111 SDTCisFP<0>, SDTCisFP<1>]>>; 112 113 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>; 114 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>; 115 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>; 116 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>; 117 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>; 118 119 def X86vshl : SDNode<"X86ISD::VSHL", 120 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 121 SDTCisVec<2>]>>; 122 def X86vsrl : SDNode<"X86ISD::VSRL", 123 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 124 SDTCisVec<2>]>>; 125 def X86vsra : SDNode<"X86ISD::VSRA", 126 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 127 SDTCisVec<2>]>>; 128 129 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>; 130 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>; 131 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>; 132 133 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 134 SDTCisVec<1>, 135 SDTCisSameAs<2, 1>]>; 136 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>; 137 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>; 138 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>; 139 140 def X86pmuludq : SDNode<"X86ISD::PMULUDQ", 141 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 142 SDTCisSameAs<1,2>]>>; 143 144 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get 145 // translated into one of the target nodes below during lowering. 146 // Note: this is a work in progress... 147 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 148 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 149 SDTCisSameAs<0,2>]>; 150 151 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>, 152 SDTCisSameAs<0,1>, SDTCisInt<2>]>; 153 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 154 SDTCisSameAs<0,2>, SDTCisInt<3>]>; 155 156 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>; 157 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 158 SDTCisSameAs<1,2>, SDTCisVT<3, i32>]>; 159 160 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>, 161 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; 162 163 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>; 164 165 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>; 166 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>; 167 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>; 168 169 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>; 170 171 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>; 172 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>; 173 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>; 174 175 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>; 176 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>; 177 178 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>; 179 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>; 180 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>; 181 182 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>; 183 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>; 184 185 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>; 186 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>; 187 188 def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>; 189 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>; 190 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>; 191 192 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>; 193 194 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>; 195 196 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>; 197 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>; 198 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>; 199 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>; 200 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>; 201 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>; 202 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>; 203 204 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 205 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>, 206 SDTCisVT<4, i8>]>; 207 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 208 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>, 209 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>, 210 SDTCisVT<6, i8>]>; 211 212 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>; 213 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>; 214 215 //===----------------------------------------------------------------------===// 216 // SSE Complex Patterns 217 //===----------------------------------------------------------------------===// 218 219 // These are 'extloads' from a scalar to the low element of a vector, zeroing 220 // the top elements. These are used for the SSE 'ss' and 'sd' instruction 221 // forms. 222 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [], 223 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 224 SDNPWantRoot]>; 225 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [], 226 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 227 SDNPWantRoot]>; 228 229 def ssmem : Operand<v4f32> { 230 let PrintMethod = "printf32mem"; 231 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 232 let ParserMatchClass = X86MemAsmOperand; 233 let OperandType = "OPERAND_MEMORY"; 234 } 235 def sdmem : Operand<v2f64> { 236 let PrintMethod = "printf64mem"; 237 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 238 let ParserMatchClass = X86MemAsmOperand; 239 let OperandType = "OPERAND_MEMORY"; 240 } 241 242 //===----------------------------------------------------------------------===// 243 // SSE pattern fragments 244 //===----------------------------------------------------------------------===// 245 246 // 128-bit load pattern fragments 247 // NOTE: all 128-bit integer vector loads are promoted to v2i64 248 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; 249 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; 250 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>; 251 252 // 256-bit load pattern fragments 253 // NOTE: all 256-bit integer vector loads are promoted to v4i64 254 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>; 255 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>; 256 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>; 257 258 // 128-/256-bit extload pattern fragments 259 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>; 260 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>; 261 262 // Like 'store', but always requires 128-bit vector alignment. 263 def alignedstore : PatFrag<(ops node:$val, node:$ptr), 264 (store node:$val, node:$ptr), [{ 265 return cast<StoreSDNode>(N)->getAlignment() >= 16; 266 }]>; 267 268 // Like 'store', but always requires 256-bit vector alignment. 269 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr), 270 (store node:$val, node:$ptr), [{ 271 return cast<StoreSDNode>(N)->getAlignment() >= 32; 272 }]>; 273 274 // Like 'load', but always requires 128-bit vector alignment. 275 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 276 return cast<LoadSDNode>(N)->getAlignment() >= 16; 277 }]>; 278 279 // Like 'X86vzload', but always requires 128-bit vector alignment. 280 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{ 281 return cast<MemSDNode>(N)->getAlignment() >= 16; 282 }]>; 283 284 // Like 'load', but always requires 256-bit vector alignment. 285 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 286 return cast<LoadSDNode>(N)->getAlignment() >= 32; 287 }]>; 288 289 def alignedloadfsf32 : PatFrag<(ops node:$ptr), 290 (f32 (alignedload node:$ptr))>; 291 def alignedloadfsf64 : PatFrag<(ops node:$ptr), 292 (f64 (alignedload node:$ptr))>; 293 294 // 128-bit aligned load pattern fragments 295 // NOTE: all 128-bit integer vector loads are promoted to v2i64 296 def alignedloadv4f32 : PatFrag<(ops node:$ptr), 297 (v4f32 (alignedload node:$ptr))>; 298 def alignedloadv2f64 : PatFrag<(ops node:$ptr), 299 (v2f64 (alignedload node:$ptr))>; 300 def alignedloadv2i64 : PatFrag<(ops node:$ptr), 301 (v2i64 (alignedload node:$ptr))>; 302 303 // 256-bit aligned load pattern fragments 304 // NOTE: all 256-bit integer vector loads are promoted to v4i64 305 def alignedloadv8f32 : PatFrag<(ops node:$ptr), 306 (v8f32 (alignedload256 node:$ptr))>; 307 def alignedloadv4f64 : PatFrag<(ops node:$ptr), 308 (v4f64 (alignedload256 node:$ptr))>; 309 def alignedloadv4i64 : PatFrag<(ops node:$ptr), 310 (v4i64 (alignedload256 node:$ptr))>; 311 312 // Like 'load', but uses special alignment checks suitable for use in 313 // memory operands in most SSE instructions, which are required to 314 // be naturally aligned on some targets but not on others. If the subtarget 315 // allows unaligned accesses, match any load, though this may require 316 // setting a feature bit in the processor (on startup, for example). 317 // Opteron 10h and later implement such a feature. 318 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 319 return Subtarget->hasVectorUAMem() 320 || cast<LoadSDNode>(N)->getAlignment() >= 16; 321 }]>; 322 323 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>; 324 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>; 325 326 // 128-bit memop pattern fragments 327 // NOTE: all 128-bit integer vector loads are promoted to v2i64 328 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>; 329 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; 330 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; 331 332 // 256-bit memop pattern fragments 333 // NOTE: all 256-bit integer vector loads are promoted to v4i64 334 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>; 335 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>; 336 def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>; 337 338 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a 339 // 16-byte boundary. 340 // FIXME: 8 byte alignment for mmx reads is not required 341 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 342 return cast<LoadSDNode>(N)->getAlignment() >= 8; 343 }]>; 344 345 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>; 346 347 // MOVNT Support 348 // Like 'store', but requires the non-temporal bit to be set 349 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), 350 (st node:$val, node:$ptr), [{ 351 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 352 return ST->isNonTemporal(); 353 return false; 354 }]>; 355 356 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 357 (st node:$val, node:$ptr), [{ 358 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 359 return ST->isNonTemporal() && !ST->isTruncatingStore() && 360 ST->getAddressingMode() == ISD::UNINDEXED && 361 ST->getAlignment() >= 16; 362 return false; 363 }]>; 364 365 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 366 (st node:$val, node:$ptr), [{ 367 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 368 return ST->isNonTemporal() && 369 ST->getAlignment() < 16; 370 return false; 371 }]>; 372 373 // 128-bit bitconvert pattern fragments 374 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>; 375 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>; 376 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>; 377 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>; 378 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>; 379 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>; 380 381 // 256-bit bitconvert pattern fragments 382 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>; 383 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>; 384 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>; 385 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>; 386 387 def vzmovl_v2i64 : PatFrag<(ops node:$src), 388 (bitconvert (v2i64 (X86vzmovl 389 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>; 390 def vzmovl_v4i32 : PatFrag<(ops node:$src), 391 (bitconvert (v4i32 (X86vzmovl 392 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>; 393 394 def vzload_v2i64 : PatFrag<(ops node:$src), 395 (bitconvert (v2i64 (X86vzload node:$src)))>; 396 397 398 def fp32imm0 : PatLeaf<(f32 fpimm), [{ 399 return N->isExactlyValue(+0.0); 400 }]>; 401 402 // BYTE_imm - Transform bit immediates into byte immediates. 403 def BYTE_imm : SDNodeXForm<imm, [{ 404 // Transformation function: imm >> 3 405 return getI32Imm(N->getZExtValue() >> 3); 406 }]>; 407 408 // EXTRACT_get_vextractf128_imm xform function: convert extract_subvector index 409 // to VEXTRACTF128 imm. 410 def EXTRACT_get_vextractf128_imm : SDNodeXForm<extract_subvector, [{ 411 return getI8Imm(X86::getExtractVEXTRACTF128Immediate(N)); 412 }]>; 413 414 // INSERT_get_vinsertf128_imm xform function: convert insert_subvector index to 415 // VINSERTF128 imm. 416 def INSERT_get_vinsertf128_imm : SDNodeXForm<insert_subvector, [{ 417 return getI8Imm(X86::getInsertVINSERTF128Immediate(N)); 418 }]>; 419 420 def vextractf128_extract : PatFrag<(ops node:$bigvec, node:$index), 421 (extract_subvector node:$bigvec, 422 node:$index), [{ 423 return X86::isVEXTRACTF128Index(N); 424 }], EXTRACT_get_vextractf128_imm>; 425 426 def vinsertf128_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 427 node:$index), 428 (insert_subvector node:$bigvec, node:$smallvec, 429 node:$index), [{ 430 return X86::isVINSERTF128Index(N); 431 }], INSERT_get_vinsertf128_imm>; 432 433
