1 //===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the X86 instructions that are generally used in 11 // privileged modes. These are not typically used by the compiler, but are 12 // supported for the assembler and disassembler. 13 // 14 //===----------------------------------------------------------------------===// 15 16 let Defs = [RAX, RDX] in 17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>, 18 TB; 19 20 let Defs = [RAX, RCX, RDX] in 21 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB; 22 23 // CPU flow control instructions 24 25 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in { 26 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB; 27 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB; 28 } 29 30 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>; 31 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB; 32 33 // Interrupt and SysCall Instructions. 34 let Uses = [EFLAGS] in 35 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>; 36 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", 37 [(int_x86_int (i8 3))], IIC_INT3>; 38 39 def : Pat<(debugtrap), 40 (INT3)>; 41 42 // The long form of "int $3" turns into int3 as a size optimization. 43 // FIXME: This doesn't work because InstAlias can't match immediate constants. 44 //def : InstAlias<"int\t$3", (INT3)>; 45 46 47 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", 48 [(int_x86_int imm:$trap)], IIC_INT>; 49 50 51 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB; 52 def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB; 53 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB, 54 Requires<[In64BitMode]>; 55 56 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [], 57 IIC_SYS_ENTER_EXIT>, TB; 58 59 def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [], 60 IIC_SYS_ENTER_EXIT>, TB; 61 def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", []>, TB, 62 Requires<[In64BitMode]>; 63 64 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize; 65 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>; 66 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>, 67 Requires<[In64BitMode]>; 68 69 70 //===----------------------------------------------------------------------===// 71 // Input/Output Instructions. 72 // 73 let Defs = [AL], Uses = [DX] in 74 def IN8rr : I<0xEC, RawFrm, (outs), (ins), 75 "in{b}\t{%dx, %al|AL, DX}", [], IIC_IN_RR>; 76 let Defs = [AX], Uses = [DX] in 77 def IN16rr : I<0xED, RawFrm, (outs), (ins), 78 "in{w}\t{%dx, %ax|AX, DX}", [], IIC_IN_RR>, OpSize; 79 let Defs = [EAX], Uses = [DX] in 80 def IN32rr : I<0xED, RawFrm, (outs), (ins), 81 "in{l}\t{%dx, %eax|EAX, DX}", [], IIC_IN_RR>; 82 83 let Defs = [AL] in 84 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port), 85 "in{b}\t{$port, %al|AL, $port}", [], IIC_IN_RI>; 86 let Defs = [AX] in 87 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port), 88 "in{w}\t{$port, %ax|AX, $port}", [], IIC_IN_RI>, OpSize; 89 let Defs = [EAX] in 90 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port), 91 "in{l}\t{$port, %eax|EAX, $port}", [], IIC_IN_RI>; 92 93 let Uses = [DX, AL] in 94 def OUT8rr : I<0xEE, RawFrm, (outs), (ins), 95 "out{b}\t{%al, %dx|DX, AL}", [], IIC_OUT_RR>; 96 let Uses = [DX, AX] in 97 def OUT16rr : I<0xEF, RawFrm, (outs), (ins), 98 "out{w}\t{%ax, %dx|DX, AX}", [], IIC_OUT_RR>, OpSize; 99 let Uses = [DX, EAX] in 100 def OUT32rr : I<0xEF, RawFrm, (outs), (ins), 101 "out{l}\t{%eax, %dx|DX, EAX}", [], IIC_OUT_RR>; 102 103 let Uses = [AL] in 104 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port), 105 "out{b}\t{%al, $port|$port, AL}", [], IIC_OUT_IR>; 106 let Uses = [AX] in 107 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port), 108 "out{w}\t{%ax, $port|$port, AX}", [], IIC_OUT_IR>, OpSize; 109 let Uses = [EAX] in 110 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port), 111 "out{l}\t{%eax, $port|$port, EAX}", [], IIC_OUT_IR>; 112 113 def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", [], IIC_INS>; 114 def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize; 115 def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>; 116 117 //===----------------------------------------------------------------------===// 118 // Moves to and from debug registers 119 120 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src), 121 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB; 122 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src), 123 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB; 124 125 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src), 126 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB; 127 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src), 128 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB; 129 130 //===----------------------------------------------------------------------===// 131 // Moves to and from control registers 132 133 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src), 134 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB; 135 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src), 136 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB; 137 138 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src), 139 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB; 140 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src), 141 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB; 142 143 //===----------------------------------------------------------------------===// 144 // Segment override instruction prefixes 145 146 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>; 147 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>; 148 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>; 149 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>; 150 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>; 151 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>; 152 153 154 //===----------------------------------------------------------------------===// 155 // Moves to and from segment registers. 156 // 157 158 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src), 159 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize; 160 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src), 161 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>; 162 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src), 163 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>; 164 165 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src), 166 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize; 167 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src), 168 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>; 169 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src), 170 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>; 171 172 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src), 173 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize; 174 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src), 175 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>; 176 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src), 177 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>; 178 179 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src), 180 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize; 181 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src), 182 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>; 183 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src), 184 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>; 185 186 //===----------------------------------------------------------------------===// 187 // Segmentation support instructions. 188 189 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB; 190 191 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 192 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB, OpSize; 193 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 194 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB, OpSize; 195 196 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo. 197 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 198 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB; 199 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 200 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB; 201 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo. 202 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 203 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB; 204 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), 205 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB; 206 207 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 208 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB, OpSize; 209 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 210 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB, OpSize; 211 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 212 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB; 213 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 214 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB; 215 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 216 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB; 217 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 218 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB; 219 220 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", 221 [], IIC_INVLPG>, TB; 222 223 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins), 224 "str{w}\t$dst", [], IIC_STR>, TB, OpSize; 225 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins), 226 "str{l}\t$dst", [], IIC_STR>, TB; 227 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins), 228 "str{q}\t$dst", [], IIC_STR>, TB; 229 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins), 230 "str{w}\t$dst", [], IIC_STR>, TB; 231 232 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), 233 "ltr{w}\t$src", [], IIC_LTR>, TB; 234 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), 235 "ltr{w}\t$src", [], IIC_LTR>, TB; 236 237 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), 238 "push{w}\t{%cs|CS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>, 239 OpSize; 240 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), 241 "push{l}\t{%cs|CS}", [], IIC_PUSH_CS>, Requires<[In32BitMode]>; 242 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), 243 "push{w}\t{%ss|SS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>, 244 OpSize; 245 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), 246 "push{l}\t{%ss|SS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>; 247 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), 248 "push{w}\t{%ds|DS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>, 249 OpSize; 250 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), 251 "push{l}\t{%ds|DS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>; 252 def PUSHES16 : I<0x06, RawFrm, (outs), (ins), 253 "push{w}\t{%es|ES}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>, 254 OpSize; 255 def PUSHES32 : I<0x06, RawFrm, (outs), (ins), 256 "push{l}\t{%es|ES}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>; 257 258 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), 259 "push{w}\t{%fs|FS}", [], IIC_PUSH_SR>, OpSize, TB; 260 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), 261 "push{l}\t{%fs|FS}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>; 262 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), 263 "push{w}\t{%gs|GS}", [], IIC_PUSH_SR>, OpSize, TB; 264 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), 265 "push{l}\t{%gs|GS}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>; 266 267 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), 268 "push{q}\t{%fs|FS}", [], IIC_PUSH_SR>, TB; 269 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), 270 "push{q}\t{%gs|GS}", [], IIC_PUSH_SR>, TB; 271 272 // No "pop cs" instruction. 273 def POPSS16 : I<0x17, RawFrm, (outs), (ins), 274 "pop{w}\t{%ss|SS}", [], IIC_POP_SR_SS>, 275 OpSize, Requires<[In32BitMode]>; 276 def POPSS32 : I<0x17, RawFrm, (outs), (ins), 277 "pop{l}\t{%ss|SS}", [], IIC_POP_SR_SS>, 278 Requires<[In32BitMode]>; 279 280 def POPDS16 : I<0x1F, RawFrm, (outs), (ins), 281 "pop{w}\t{%ds|DS}", [], IIC_POP_SR>, 282 OpSize, Requires<[In32BitMode]>; 283 def POPDS32 : I<0x1F, RawFrm, (outs), (ins), 284 "pop{l}\t{%ds|DS}", [], IIC_POP_SR>, 285 Requires<[In32BitMode]>; 286 287 def POPES16 : I<0x07, RawFrm, (outs), (ins), 288 "pop{w}\t{%es|ES}", [], IIC_POP_SR>, 289 OpSize, Requires<[In32BitMode]>; 290 def POPES32 : I<0x07, RawFrm, (outs), (ins), 291 "pop{l}\t{%es|ES}", [], IIC_POP_SR>, 292 Requires<[In32BitMode]>; 293 294 def POPFS16 : I<0xa1, RawFrm, (outs), (ins), 295 "pop{w}\t{%fs|FS}", [], IIC_POP_SR>, OpSize, TB; 296 def POPFS32 : I<0xa1, RawFrm, (outs), (ins), 297 "pop{l}\t{%fs|FS}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>; 298 def POPFS64 : I<0xa1, RawFrm, (outs), (ins), 299 "pop{q}\t{%fs|FS}", [], IIC_POP_SR>, TB; 300 301 def POPGS16 : I<0xa9, RawFrm, (outs), (ins), 302 "pop{w}\t{%gs|GS}", [], IIC_POP_SR>, OpSize, TB; 303 def POPGS32 : I<0xa9, RawFrm, (outs), (ins), 304 "pop{l}\t{%gs|GS}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>; 305 def POPGS64 : I<0xa9, RawFrm, (outs), (ins), 306 "pop{q}\t{%gs|GS}", [], IIC_POP_SR>, TB; 307 308 309 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), 310 "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize; 311 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 312 "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>; 313 314 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), 315 "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize; 316 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 317 "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB; 318 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src), 319 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB; 320 321 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), 322 "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize; 323 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 324 "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>; 325 326 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), 327 "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize; 328 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 329 "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB; 330 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src), 331 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB; 332 333 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), 334 "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize; 335 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 336 "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB; 337 338 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src), 339 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB; 340 341 342 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), 343 "verr\t$seg", [], IIC_VERR>, TB; 344 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), 345 "verr\t$seg", [], IIC_VERR>, TB; 346 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), 347 "verw\t$seg", [], IIC_VERW_MEM>, TB; 348 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), 349 "verw\t$seg", [], IIC_VERW_REG>, TB; 350 351 //===----------------------------------------------------------------------===// 352 // Descriptor-table support instructions 353 354 def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins), 355 "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize, Requires<[In32BitMode]>; 356 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins), 357 "sgdt\t$dst", [], IIC_SGDT>, TB; 358 def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins), 359 "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize, Requires<[In32BitMode]>; 360 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins), 361 "sidt\t$dst", []>, TB; 362 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins), 363 "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize; 364 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins), 365 "sldt{w}\t$dst", [], IIC_SLDT>, TB; 366 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins), 367 "sldt{l}\t$dst", [], IIC_SLDT>, TB; 368 369 // LLDT is not interpreted specially in 64-bit mode because there is no sign 370 // extension. 371 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins), 372 "sldt{q}\t$dst", [], IIC_SLDT>, TB; 373 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins), 374 "sldt{q}\t$dst", [], IIC_SLDT>, TB; 375 376 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src), 377 "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize, Requires<[In32BitMode]>; 378 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src), 379 "lgdt\t$src", [], IIC_LGDT>, TB; 380 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src), 381 "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize, Requires<[In32BitMode]>; 382 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src), 383 "lidt\t$src", [], IIC_LIDT>, TB; 384 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src), 385 "lldt{w}\t$src", [], IIC_LLDT_REG>, TB; 386 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src), 387 "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB; 388 389 //===----------------------------------------------------------------------===// 390 // Specialized register support 391 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB; 392 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB; 393 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [], IIC_RDPMC>, TB; 394 395 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins), 396 "smsw{w}\t$dst", [], IIC_SMSW>, OpSize, TB; 397 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins), 398 "smsw{l}\t$dst", [], IIC_SMSW>, TB; 399 // no m form encodable; use SMSW16m 400 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins), 401 "smsw{q}\t$dst", [], IIC_SMSW>, TB; 402 403 // For memory operands, there is only a 16-bit form 404 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins), 405 "smsw{w}\t$dst", [], IIC_SMSW>, TB; 406 407 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src), 408 "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB; 409 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src), 410 "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB; 411 412 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB; 413 414 //===----------------------------------------------------------------------===// 415 // Cache instructions 416 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB; 417 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB; 418 419 //===----------------------------------------------------------------------===// 420 // XSAVE instructions 421 let Defs = [RDX, RAX], Uses = [RCX] in 422 def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB; 423 424 let Uses = [RDX, RAX, RCX] in 425 def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB; 426 427 let Uses = [RDX, RAX] in { 428 def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins), 429 "xsave\t$dst", []>, TB; 430 def XSAVE64 : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins), 431 "xsaveq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>; 432 def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst), 433 "xrstor\t$dst", []>, TB; 434 def XRSTOR64 : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst), 435 "xrstorq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>; 436 def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins), 437 "xsaveopt\t$dst", []>, TB; 438 def XSAVEOPT64 : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins), 439 "xsaveoptq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>; 440 } 441 442 //===----------------------------------------------------------------------===// 443 // VIA PadLock crypto instructions 444 let Defs = [RAX, RDI], Uses = [RDX, RDI] in 445 def XSTORE : I<0xc0, RawFrm, (outs), (ins), "xstore", []>, A7; 446 447 def : InstAlias<"xstorerng", (XSTORE)>; 448 449 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in { 450 def XCRYPTECB : I<0xc8, RawFrm, (outs), (ins), "xcryptecb", []>, A7; 451 def XCRYPTCBC : I<0xd0, RawFrm, (outs), (ins), "xcryptcbc", []>, A7; 452 def XCRYPTCTR : I<0xd8, RawFrm, (outs), (ins), "xcryptctr", []>, A7; 453 def XCRYPTCFB : I<0xe0, RawFrm, (outs), (ins), "xcryptcfb", []>, A7; 454 def XCRYPTOFB : I<0xe8, RawFrm, (outs), (ins), "xcryptofb", []>, A7; 455 } 456 457 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in { 458 def XSHA1 : I<0xc8, RawFrm, (outs), (ins), "xsha1", []>, A6; 459 def XSHA256 : I<0xd0, RawFrm, (outs), (ins), "xsha256", []>, A6; 460 } 461 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in 462 def MONTMUL : I<0xc0, RawFrm, (outs), (ins), "montmul", []>, A6; 463 464 //===----------------------------------------------------------------------===// 465 // FS/GS Base Instructions 466 let Predicates = [HasFSGSBase, In64BitMode] in { 467 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins), 468 "rdfsbase{l}\t$dst", 469 [(set GR32:$dst, (int_x86_rdfsbase_32))]>, TB, XS; 470 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins), 471 "rdfsbase{q}\t$dst", 472 [(set GR64:$dst, (int_x86_rdfsbase_64))]>, TB, XS; 473 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins), 474 "rdgsbase{l}\t$dst", 475 [(set GR32:$dst, (int_x86_rdgsbase_32))]>, TB, XS; 476 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins), 477 "rdgsbase{q}\t$dst", 478 [(set GR64:$dst, (int_x86_rdgsbase_64))]>, TB, XS; 479 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src), 480 "wrfsbase{l}\t$src", 481 [(int_x86_wrfsbase_32 GR32:$src)]>, TB, XS; 482 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src), 483 "wrfsbase{q}\t$src", 484 [(int_x86_wrfsbase_64 GR64:$src)]>, TB, XS; 485 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src), 486 "wrgsbase{l}\t$src", 487 [(int_x86_wrgsbase_32 GR32:$src)]>, TB, XS; 488 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src), 489 "wrgsbase{q}\t$src", 490 [(int_x86_wrgsbase_64 GR64:$src)]>, TB, XS; 491 } 492 493 //===----------------------------------------------------------------------===// 494 // INVPCID Instruction 495 def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), 496 "invpcid {$src2, $src1|$src1, $src2}", []>, OpSize, T8, 497 Requires<[In32BitMode]>; 498 def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), 499 "invpcid {$src2, $src1|$src1, $src2}", []>, OpSize, T8, 500 Requires<[In64BitMode]>; 501
