1 //===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the itinerary class data for the Intel Atom (Bonnell) 11 // processors. 12 // 13 //===----------------------------------------------------------------------===// 14 15 // 16 // Scheduling information derived from the "Intel 64 and IA32 Architectures 17 // Optimization Reference Manual", Chapter 13, Section 4. 18 // Functional Units 19 // Port 0 20 def Port0 : FuncUnit; // ALU: ALU0, shift/rotate, load/store 21 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide 22 def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA 23 // SIMD/FP: SIMD ALU, FP Adder 24 25 def AtomItineraries : ProcessorItineraries< 26 [ Port0, Port1 ], 27 [], [ 28 // P0 only 29 // InstrItinData<class, [InstrStage<N, [P0]>] >, 30 // P0 or P1 31 // InstrItinData<class, [InstrStage<N, [P0, P1]>] >, 32 // P0 and P1 33 // InstrItinData<class, [InstrStage<N, [P0], 0>, InstrStage<N, [P1]>] >, 34 // 35 // Default is 1 cycle, port0 or port1 36 InstrItinData<IIC_DEFAULT, [InstrStage<1, [Port0, Port1]>] >, 37 InstrItinData<IIC_ALU_MEM, [InstrStage<1, [Port0]>] >, 38 InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [Port0, Port1]>] >, 39 InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >, 40 InstrItinData<IIC_LEA_16, [InstrStage<2, [Port0, Port1]>] >, 41 // mul 42 InstrItinData<IIC_MUL8, [InstrStage<7, [Port0, Port1]>] >, 43 InstrItinData<IIC_MUL16_MEM, [InstrStage<8, [Port0, Port1]>] >, 44 InstrItinData<IIC_MUL16_REG, [InstrStage<7, [Port0, Port1]>] >, 45 InstrItinData<IIC_MUL32_MEM, [InstrStage<7, [Port0, Port1]>] >, 46 InstrItinData<IIC_MUL32_REG, [InstrStage<6, [Port0, Port1]>] >, 47 InstrItinData<IIC_MUL64, [InstrStage<12, [Port0, Port1]>] >, 48 // imul by al, ax, eax, rax 49 InstrItinData<IIC_IMUL8, [InstrStage<7, [Port0, Port1]>] >, 50 InstrItinData<IIC_IMUL16_MEM, [InstrStage<8, [Port0, Port1]>] >, 51 InstrItinData<IIC_IMUL16_REG, [InstrStage<7, [Port0, Port1]>] >, 52 InstrItinData<IIC_IMUL32_MEM, [InstrStage<7, [Port0, Port1]>] >, 53 InstrItinData<IIC_IMUL32_REG, [InstrStage<6, [Port0, Port1]>] >, 54 InstrItinData<IIC_IMUL64, [InstrStage<12, [Port0, Port1]>] >, 55 // imul reg by reg|mem 56 InstrItinData<IIC_IMUL16_RM, [InstrStage<7, [Port0, Port1]>] >, 57 InstrItinData<IIC_IMUL16_RR, [InstrStage<6, [Port0, Port1]>] >, 58 InstrItinData<IIC_IMUL32_RM, [InstrStage<5, [Port0]>] >, 59 InstrItinData<IIC_IMUL32_RR, [InstrStage<5, [Port0]>] >, 60 InstrItinData<IIC_IMUL64_RM, [InstrStage<12, [Port0, Port1]>] >, 61 InstrItinData<IIC_IMUL64_RR, [InstrStage<12, [Port0, Port1]>] >, 62 // imul reg = reg/mem * imm 63 InstrItinData<IIC_IMUL16_RRI, [InstrStage<6, [Port0, Port1]>] >, 64 InstrItinData<IIC_IMUL32_RRI, [InstrStage<5, [Port0]>] >, 65 InstrItinData<IIC_IMUL64_RRI, [InstrStage<14, [Port0, Port1]>] >, 66 InstrItinData<IIC_IMUL16_RMI, [InstrStage<7, [Port0, Port1]>] >, 67 InstrItinData<IIC_IMUL32_RMI, [InstrStage<5, [Port0]>] >, 68 InstrItinData<IIC_IMUL64_RMI, [InstrStage<14, [Port0, Port1]>] >, 69 // idiv 70 InstrItinData<IIC_IDIV8, [InstrStage<62, [Port0, Port1]>] >, 71 InstrItinData<IIC_IDIV16, [InstrStage<62, [Port0, Port1]>] >, 72 InstrItinData<IIC_IDIV32, [InstrStage<62, [Port0, Port1]>] >, 73 InstrItinData<IIC_IDIV64, [InstrStage<130, [Port0, Port1]>] >, 74 // div 75 InstrItinData<IIC_DIV8_REG, [InstrStage<50, [Port0, Port1]>] >, 76 InstrItinData<IIC_DIV8_MEM, [InstrStage<68, [Port0, Port1]>] >, 77 InstrItinData<IIC_DIV16, [InstrStage<50, [Port0, Port1]>] >, 78 InstrItinData<IIC_DIV32, [InstrStage<50, [Port0, Port1]>] >, 79 InstrItinData<IIC_DIV64, [InstrStage<130, [Port0, Port1]>] >, 80 // neg/not/inc/dec 81 InstrItinData<IIC_UNARY_REG, [InstrStage<1, [Port0, Port1]>] >, 82 InstrItinData<IIC_UNARY_MEM, [InstrStage<1, [Port0]>] >, 83 // add/sub/and/or/xor/adc/sbc/cmp/test 84 InstrItinData<IIC_BIN_NONMEM, [InstrStage<1, [Port0, Port1]>] >, 85 InstrItinData<IIC_BIN_MEM, [InstrStage<1, [Port0]>] >, 86 // shift/rotate 87 InstrItinData<IIC_SR, [InstrStage<1, [Port0]>] >, 88 // shift double 89 InstrItinData<IIC_SHD16_REG_IM, [InstrStage<6, [Port0, Port1]>] >, 90 InstrItinData<IIC_SHD16_REG_CL, [InstrStage<6, [Port0, Port1]>] >, 91 InstrItinData<IIC_SHD16_MEM_IM, [InstrStage<6, [Port0, Port1]>] >, 92 InstrItinData<IIC_SHD16_MEM_CL, [InstrStage<6, [Port0, Port1]>] >, 93 InstrItinData<IIC_SHD32_REG_IM, [InstrStage<2, [Port0, Port1]>] >, 94 InstrItinData<IIC_SHD32_REG_CL, [InstrStage<2, [Port0, Port1]>] >, 95 InstrItinData<IIC_SHD32_MEM_IM, [InstrStage<4, [Port0, Port1]>] >, 96 InstrItinData<IIC_SHD32_MEM_CL, [InstrStage<4, [Port0, Port1]>] >, 97 InstrItinData<IIC_SHD64_REG_IM, [InstrStage<9, [Port0, Port1]>] >, 98 InstrItinData<IIC_SHD64_REG_CL, [InstrStage<8, [Port0, Port1]>] >, 99 InstrItinData<IIC_SHD64_MEM_IM, [InstrStage<9, [Port0, Port1]>] >, 100 InstrItinData<IIC_SHD64_MEM_CL, [InstrStage<9, [Port0, Port1]>] >, 101 // cmov 102 InstrItinData<IIC_CMOV16_RM, [InstrStage<1, [Port0]>] >, 103 InstrItinData<IIC_CMOV16_RR, [InstrStage<1, [Port0, Port1]>] >, 104 InstrItinData<IIC_CMOV32_RM, [InstrStage<1, [Port0]>] >, 105 InstrItinData<IIC_CMOV32_RR, [InstrStage<1, [Port0, Port1]>] >, 106 InstrItinData<IIC_CMOV64_RM, [InstrStage<1, [Port0]>] >, 107 InstrItinData<IIC_CMOV64_RR, [InstrStage<1, [Port0, Port1]>] >, 108 // set 109 InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >, 110 InstrItinData<IIC_SET_R, [InstrStage<1, [Port0, Port1]>] >, 111 // jcc 112 InstrItinData<IIC_Jcc, [InstrStage<1, [Port1]>] >, 113 // jcxz/jecxz/jrcxz 114 InstrItinData<IIC_JCXZ, [InstrStage<4, [Port0, Port1]>] >, 115 // jmp rel 116 InstrItinData<IIC_JMP_REL, [InstrStage<1, [Port1]>] >, 117 // jmp indirect 118 InstrItinData<IIC_JMP_REG, [InstrStage<1, [Port1]>] >, 119 InstrItinData<IIC_JMP_MEM, [InstrStage<2, [Port0, Port1]>] >, 120 // jmp far 121 InstrItinData<IIC_JMP_FAR_MEM, [InstrStage<32, [Port0, Port1]>] >, 122 InstrItinData<IIC_JMP_FAR_PTR, [InstrStage<31, [Port0, Port1]>] >, 123 // loop/loope/loopne 124 InstrItinData<IIC_LOOP, [InstrStage<18, [Port0, Port1]>] >, 125 InstrItinData<IIC_LOOPE, [InstrStage<8, [Port0, Port1]>] >, 126 InstrItinData<IIC_LOOPNE, [InstrStage<17, [Port0, Port1]>] >, 127 // call - all but reg/imm 128 InstrItinData<IIC_CALL_RI, [InstrStage<1, [Port0], 0>, 129 InstrStage<1, [Port1]>] >, 130 InstrItinData<IIC_CALL_MEM, [InstrStage<15, [Port0, Port1]>] >, 131 InstrItinData<IIC_CALL_FAR_MEM, [InstrStage<40, [Port0, Port1]>] >, 132 InstrItinData<IIC_CALL_FAR_PTR, [InstrStage<39, [Port0, Port1]>] >, 133 //ret 134 InstrItinData<IIC_RET, [InstrStage<79, [Port0, Port1]>] >, 135 InstrItinData<IIC_RET_IMM, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >, 136 //sign extension movs 137 InstrItinData<IIC_MOVSX,[InstrStage<1, [Port0] >] >, 138 InstrItinData<IIC_MOVSX_R16_R8, [InstrStage<2, [Port0, Port1]>] >, 139 InstrItinData<IIC_MOVSX_R16_M8, [InstrStage<3, [Port0, Port1]>] >, 140 InstrItinData<IIC_MOVSX_R16_R16, [InstrStage<1, [Port0, Port1]>] >, 141 InstrItinData<IIC_MOVSX_R32_R32, [InstrStage<1, [Port0, Port1]>] >, 142 //zero extension movs 143 InstrItinData<IIC_MOVZX,[InstrStage<1, [Port0]>] >, 144 InstrItinData<IIC_MOVZX_R16_R8, [InstrStage<2, [Port0, Port1]>] >, 145 InstrItinData<IIC_MOVZX_R16_M8, [InstrStage<3, [Port0, Port1]>] >, 146 147 InstrItinData<IIC_REP_MOVS, [InstrStage<75, [Port0, Port1]>] >, 148 InstrItinData<IIC_REP_STOS, [InstrStage<74, [Port0, Port1]>] >, 149 150 // SSE binary operations 151 // arithmetic fp scalar 152 InstrItinData<IIC_SSE_ALU_F32S_RR, [InstrStage<5, [Port1]>] >, 153 InstrItinData<IIC_SSE_ALU_F32S_RM, [InstrStage<5, [Port0], 0>, 154 InstrStage<5, [Port1]>] >, 155 InstrItinData<IIC_SSE_ALU_F64S_RR, [InstrStage<5, [Port1]>] >, 156 InstrItinData<IIC_SSE_ALU_F64S_RM, [InstrStage<5, [Port0], 0>, 157 InstrStage<5, [Port1]>] >, 158 InstrItinData<IIC_SSE_MUL_F32S_RR, [InstrStage<4, [Port0]>] >, 159 InstrItinData<IIC_SSE_MUL_F32S_RM, [InstrStage<4, [Port0]>] >, 160 InstrItinData<IIC_SSE_MUL_F64S_RR, [InstrStage<5, [Port0]>] >, 161 InstrItinData<IIC_SSE_MUL_F64S_RM, [InstrStage<5, [Port0]>] >, 162 InstrItinData<IIC_SSE_DIV_F32S_RR, [InstrStage<34, [Port0, Port1]>] >, 163 InstrItinData<IIC_SSE_DIV_F32S_RM, [InstrStage<34, [Port0, Port1]>] >, 164 InstrItinData<IIC_SSE_DIV_F64S_RR, [InstrStage<62, [Port0, Port1]>] >, 165 InstrItinData<IIC_SSE_DIV_F64S_RM, [InstrStage<62, [Port0, Port1]>] >, 166 167 InstrItinData<IIC_SSE_COMIS_RR, [InstrStage<9, [Port0, Port1]>] >, 168 InstrItinData<IIC_SSE_COMIS_RM, [InstrStage<10, [Port0, Port1]>] >, 169 170 InstrItinData<IIC_SSE_HADDSUB_RR, [InstrStage<8, [Port0, Port1]>] >, 171 InstrItinData<IIC_SSE_HADDSUB_RM, [InstrStage<9, [Port0, Port1]>] >, 172 173 // arithmetic fp parallel 174 InstrItinData<IIC_SSE_ALU_F32P_RR, [InstrStage<5, [Port1]>] >, 175 InstrItinData<IIC_SSE_ALU_F32P_RM, [InstrStage<5, [Port0], 0>, 176 InstrStage<5, [Port1]>] >, 177 InstrItinData<IIC_SSE_ALU_F64P_RR, [InstrStage<6, [Port0, Port1]>] >, 178 InstrItinData<IIC_SSE_ALU_F64P_RM, [InstrStage<7, [Port0, Port1]>] >, 179 InstrItinData<IIC_SSE_MUL_F32P_RR, [InstrStage<5, [Port0]>] >, 180 InstrItinData<IIC_SSE_MUL_F32P_RM, [InstrStage<5, [Port0]>] >, 181 InstrItinData<IIC_SSE_MUL_F64P_RR, [InstrStage<9, [Port0, Port1]>] >, 182 InstrItinData<IIC_SSE_MUL_F64P_RM, [InstrStage<10, [Port0, Port1]>] >, 183 InstrItinData<IIC_SSE_DIV_F32P_RR, [InstrStage<70, [Port0, Port1]>] >, 184 InstrItinData<IIC_SSE_DIV_F32P_RM, [InstrStage<70, [Port0, Port1]>] >, 185 InstrItinData<IIC_SSE_DIV_F64P_RR, [InstrStage<125, [Port0, Port1]>] >, 186 InstrItinData<IIC_SSE_DIV_F64P_RM, [InstrStage<125, [Port0, Port1]>] >, 187 188 // bitwise parallel 189 InstrItinData<IIC_SSE_BIT_P_RR, [InstrStage<1, [Port0, Port1]>] >, 190 InstrItinData<IIC_SSE_BIT_P_RM, [InstrStage<1, [Port0]>] >, 191 192 // arithmetic int parallel 193 InstrItinData<IIC_SSE_INTALU_P_RR, [InstrStage<1, [Port0, Port1]>] >, 194 InstrItinData<IIC_SSE_INTALU_P_RM, [InstrStage<1, [Port0]>] >, 195 InstrItinData<IIC_SSE_INTALUQ_P_RR, [InstrStage<2, [Port0, Port1]>] >, 196 InstrItinData<IIC_SSE_INTALUQ_P_RM, [InstrStage<3, [Port0, Port1]>] >, 197 198 // multiply int parallel 199 InstrItinData<IIC_SSE_INTMUL_P_RR, [InstrStage<5, [Port0]>] >, 200 InstrItinData<IIC_SSE_INTMUL_P_RM, [InstrStage<5, [Port0]>] >, 201 202 // shift parallel 203 InstrItinData<IIC_SSE_INTSH_P_RR, [InstrStage<2, [Port0, Port1]>] >, 204 InstrItinData<IIC_SSE_INTSH_P_RM, [InstrStage<3, [Port0, Port1]>] >, 205 InstrItinData<IIC_SSE_INTSH_P_RI, [InstrStage<1, [Port0, Port1]>] >, 206 207 InstrItinData<IIC_SSE_CMPP_RR, [InstrStage<6, [Port0, Port1]>] >, 208 InstrItinData<IIC_SSE_CMPP_RM, [InstrStage<7, [Port0, Port1]>] >, 209 210 InstrItinData<IIC_SSE_SHUFP, [InstrStage<1, [Port0]>] >, 211 InstrItinData<IIC_SSE_PSHUF, [InstrStage<1, [Port0]>] >, 212 213 InstrItinData<IIC_SSE_UNPCK, [InstrStage<1, [Port0]>] >, 214 215 InstrItinData<IIC_SSE_SQRTP_RR, [InstrStage<13, [Port0, Port1]>] >, 216 InstrItinData<IIC_SSE_SQRTP_RM, [InstrStage<14, [Port0, Port1]>] >, 217 InstrItinData<IIC_SSE_SQRTS_RR, [InstrStage<11, [Port0, Port1]>] >, 218 InstrItinData<IIC_SSE_SQRTS_RM, [InstrStage<12, [Port0, Port1]>] >, 219 220 InstrItinData<IIC_SSE_RCPP_RR, [InstrStage<9, [Port0, Port1]>] >, 221 InstrItinData<IIC_SSE_RCPP_RM, [InstrStage<10, [Port0, Port1]>] >, 222 InstrItinData<IIC_SSE_RCPS_RR, [InstrStage<4, [Port0]>] >, 223 InstrItinData<IIC_SSE_RCPS_RM, [InstrStage<4, [Port0]>] >, 224 225 InstrItinData<IIC_SSE_MOVMSK, [InstrStage<3, [Port0]>] >, 226 InstrItinData<IIC_SSE_MASKMOV, [InstrStage<2, [Port0, Port1]>] >, 227 228 InstrItinData<IIC_SSE_PEXTRW, [InstrStage<4, [Port0, Port1]>] >, 229 InstrItinData<IIC_SSE_PINSRW, [InstrStage<1, [Port0]>] >, 230 231 InstrItinData<IIC_SSE_PABS_RR, [InstrStage<1, [Port0, Port1]>] >, 232 InstrItinData<IIC_SSE_PABS_RM, [InstrStage<1, [Port0]>] >, 233 234 InstrItinData<IIC_SSE_MOV_S_RR, [InstrStage<1, [Port0, Port1]>] >, 235 InstrItinData<IIC_SSE_MOV_S_RM, [InstrStage<1, [Port0]>] >, 236 InstrItinData<IIC_SSE_MOV_S_MR, [InstrStage<1, [Port0]>] >, 237 238 InstrItinData<IIC_SSE_MOVA_P_RR, [InstrStage<1, [Port0, Port1]>] >, 239 InstrItinData<IIC_SSE_MOVA_P_RM, [InstrStage<1, [Port0]>] >, 240 InstrItinData<IIC_SSE_MOVA_P_MR, [InstrStage<1, [Port0]>] >, 241 242 InstrItinData<IIC_SSE_MOVU_P_RR, [InstrStage<1, [Port0, Port1]>] >, 243 InstrItinData<IIC_SSE_MOVU_P_RM, [InstrStage<3, [Port0, Port1]>] >, 244 InstrItinData<IIC_SSE_MOVU_P_MR, [InstrStage<2, [Port0, Port1]>] >, 245 246 InstrItinData<IIC_SSE_MOV_LH, [InstrStage<1, [Port0]>] >, 247 248 InstrItinData<IIC_SSE_LDDQU, [InstrStage<3, [Port0, Port1]>] >, 249 250 InstrItinData<IIC_SSE_MOVDQ, [InstrStage<1, [Port0]>] >, 251 InstrItinData<IIC_SSE_MOVD_ToGP, [InstrStage<3, [Port0]>] >, 252 InstrItinData<IIC_SSE_MOVQ_RR, [InstrStage<1, [Port0, Port1]>] >, 253 254 InstrItinData<IIC_SSE_MOVNT, [InstrStage<1, [Port0]>] >, 255 256 InstrItinData<IIC_SSE_PREFETCH, [InstrStage<1, [Port0]>] >, 257 InstrItinData<IIC_SSE_PAUSE, [InstrStage<17, [Port0, Port1]>] >, 258 InstrItinData<IIC_SSE_LFENCE, [InstrStage<1, [Port0, Port1]>] >, 259 InstrItinData<IIC_SSE_MFENCE, [InstrStage<1, [Port0]>] >, 260 InstrItinData<IIC_SSE_SFENCE, [InstrStage<1, [Port0]>] >, 261 InstrItinData<IIC_SSE_LDMXCSR, [InstrStage<5, [Port0, Port1]>] >, 262 InstrItinData<IIC_SSE_STMXCSR, [InstrStage<15, [Port0, Port1]>] >, 263 264 InstrItinData<IIC_SSE_PHADDSUBD_RR, [InstrStage<3, [Port0, Port1]>] >, 265 InstrItinData<IIC_SSE_PHADDSUBD_RM, [InstrStage<4, [Port0, Port1]>] >, 266 InstrItinData<IIC_SSE_PHADDSUBSW_RR, [InstrStage<7, [Port0, Port1]>] >, 267 InstrItinData<IIC_SSE_PHADDSUBSW_RM, [InstrStage<8, [Port0, Port1]>] >, 268 InstrItinData<IIC_SSE_PHADDSUBW_RR, [InstrStage<7, [Port0, Port1]>] >, 269 InstrItinData<IIC_SSE_PHADDSUBW_RM, [InstrStage<8, [Port0, Port1]>] >, 270 InstrItinData<IIC_SSE_PSHUFB_RR, [InstrStage<4, [Port0, Port1]>] >, 271 InstrItinData<IIC_SSE_PSHUFB_RM, [InstrStage<5, [Port0, Port1]>] >, 272 InstrItinData<IIC_SSE_PSIGN_RR, [InstrStage<1, [Port0, Port1]>] >, 273 InstrItinData<IIC_SSE_PSIGN_RM, [InstrStage<1, [Port0]>] >, 274 275 InstrItinData<IIC_SSE_PMADD, [InstrStage<5, [Port0]>] >, 276 InstrItinData<IIC_SSE_PMULHRSW, [InstrStage<5, [Port0]>] >, 277 InstrItinData<IIC_SSE_PALIGNR, [InstrStage<1, [Port0]>] >, 278 InstrItinData<IIC_SSE_MWAIT, [InstrStage<46, [Port0, Port1]>] >, 279 InstrItinData<IIC_SSE_MONITOR, [InstrStage<45, [Port0, Port1]>] >, 280 281 // conversions 282 // to/from PD ... 283 InstrItinData<IIC_SSE_CVT_PD_RR, [InstrStage<7, [Port0, Port1]>] >, 284 InstrItinData<IIC_SSE_CVT_PD_RM, [InstrStage<8, [Port0, Port1]>] >, 285 // to/from PS except to/from PD and PS2PI 286 InstrItinData<IIC_SSE_CVT_PS_RR, [InstrStage<6, [Port0, Port1]>] >, 287 InstrItinData<IIC_SSE_CVT_PS_RM, [InstrStage<7, [Port0, Port1]>] >, 288 InstrItinData<IIC_SSE_CVT_Scalar_RR, [InstrStage<6, [Port0, Port1]>] >, 289 InstrItinData<IIC_SSE_CVT_Scalar_RM, [InstrStage<7, [Port0, Port1]>] >, 290 InstrItinData<IIC_SSE_CVT_SS2SI32_RR, [InstrStage<8, [Port0, Port1]>] >, 291 InstrItinData<IIC_SSE_CVT_SS2SI32_RM, [InstrStage<9, [Port0, Port1]>] >, 292 InstrItinData<IIC_SSE_CVT_SS2SI64_RR, [InstrStage<9, [Port0, Port1]>] >, 293 InstrItinData<IIC_SSE_CVT_SS2SI64_RM, [InstrStage<10, [Port0, Port1]>] >, 294 InstrItinData<IIC_SSE_CVT_SD2SI_RR, [InstrStage<8, [Port0, Port1]>] >, 295 InstrItinData<IIC_SSE_CVT_SD2SI_RM, [InstrStage<9, [Port0, Port1]>] >, 296 297 // MMX MOVs 298 InstrItinData<IIC_MMX_MOV_MM_RM, [InstrStage<1, [Port0]>] >, 299 InstrItinData<IIC_MMX_MOV_REG_MM, [InstrStage<3, [Port0]>] >, 300 InstrItinData<IIC_MMX_MOVQ_RM, [InstrStage<1, [Port0]>] >, 301 InstrItinData<IIC_MMX_MOVQ_RR, [InstrStage<1, [Port0, Port1]>] >, 302 // other MMX 303 InstrItinData<IIC_MMX_ALU_RM, [InstrStage<1, [Port0]>] >, 304 InstrItinData<IIC_MMX_ALU_RR, [InstrStage<1, [Port0, Port1]>] >, 305 InstrItinData<IIC_MMX_ALUQ_RM, [InstrStage<3, [Port0, Port1]>] >, 306 InstrItinData<IIC_MMX_ALUQ_RR, [InstrStage<2, [Port0, Port1]>] >, 307 InstrItinData<IIC_MMX_PHADDSUBW_RM, [InstrStage<6, [Port0, Port1]>] >, 308 InstrItinData<IIC_MMX_PHADDSUBW_RR, [InstrStage<5, [Port0, Port1]>] >, 309 InstrItinData<IIC_MMX_PHADDSUBD_RM, [InstrStage<4, [Port0, Port1]>] >, 310 InstrItinData<IIC_MMX_PHADDSUBD_RR, [InstrStage<3, [Port0, Port1]>] >, 311 InstrItinData<IIC_MMX_PMUL, [InstrStage<4, [Port0]>] >, 312 InstrItinData<IIC_MMX_MISC_FUNC_MEM, [InstrStage<1, [Port0]>] >, 313 InstrItinData<IIC_MMX_MISC_FUNC_REG, [InstrStage<1, [Port0, Port1]>] >, 314 InstrItinData<IIC_MMX_PSADBW, [InstrStage<4, [Port0, Port1]>] >, 315 InstrItinData<IIC_MMX_SHIFT_RI, [InstrStage<1, [Port0, Port1]>] >, 316 InstrItinData<IIC_MMX_SHIFT_RM, [InstrStage<3, [Port0, Port1]>] >, 317 InstrItinData<IIC_MMX_SHIFT_RR, [InstrStage<2, [Port0, Port1]>] >, 318 InstrItinData<IIC_MMX_UNPCK_H_RM, [InstrStage<1, [Port0]>] >, 319 InstrItinData<IIC_MMX_UNPCK_H_RR, [InstrStage<1, [Port0, Port1]>] >, 320 InstrItinData<IIC_MMX_UNPCK_L, [InstrStage<1, [Port0]>] >, 321 InstrItinData<IIC_MMX_PCK_RM, [InstrStage<1, [Port0]>] >, 322 InstrItinData<IIC_MMX_PCK_RR, [InstrStage<1, [Port0, Port1]>] >, 323 InstrItinData<IIC_MMX_PSHUF, [InstrStage<1, [Port0]>] >, 324 InstrItinData<IIC_MMX_PEXTR, [InstrStage<4, [Port0, Port1]>] >, 325 InstrItinData<IIC_MMX_PINSRW, [InstrStage<1, [Port0]>] >, 326 InstrItinData<IIC_MMX_MASKMOV, [InstrStage<1, [Port0]>] >, 327 // conversions 328 // from/to PD 329 InstrItinData<IIC_MMX_CVT_PD_RR, [InstrStage<7, [Port0, Port1]>] >, 330 InstrItinData<IIC_MMX_CVT_PD_RM, [InstrStage<8, [Port0, Port1]>] >, 331 // from/to PI 332 InstrItinData<IIC_MMX_CVT_PS_RR, [InstrStage<5, [Port1]>] >, 333 InstrItinData<IIC_MMX_CVT_PS_RM, [InstrStage<5, [Port0], 0>, 334 InstrStage<5, [Port1]>]>, 335 336 InstrItinData<IIC_CMPX_LOCK, [InstrStage<14, [Port0, Port1]>] >, 337 InstrItinData<IIC_CMPX_LOCK_8, [InstrStage<6, [Port0, Port1]>] >, 338 InstrItinData<IIC_CMPX_LOCK_8B, [InstrStage<18, [Port0, Port1]>] >, 339 InstrItinData<IIC_CMPX_LOCK_16B, [InstrStage<22, [Port0, Port1]>] >, 340 341 InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<2, [Port0, Port1]>] >, 342 InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<3, [Port0, Port1]>] >, 343 344 InstrItinData<IIC_FILD, [InstrStage<5, [Port0], 0>, InstrStage<5, [Port1]>] >, 345 InstrItinData<IIC_FLD, [InstrStage<1, [Port0]>] >, 346 InstrItinData<IIC_FLD80, [InstrStage<4, [Port0, Port1]>] >, 347 348 InstrItinData<IIC_FST, [InstrStage<2, [Port0, Port1]>] >, 349 InstrItinData<IIC_FST80, [InstrStage<5, [Port0, Port1]>] >, 350 InstrItinData<IIC_FIST, [InstrStage<6, [Port0, Port1]>] >, 351 352 InstrItinData<IIC_FLDZ, [InstrStage<1, [Port0, Port1]>] >, 353 InstrItinData<IIC_FUCOM, [InstrStage<1, [Port1]>] >, 354 InstrItinData<IIC_FUCOMI, [InstrStage<9, [Port0, Port1]>] >, 355 InstrItinData<IIC_FCOMI, [InstrStage<9, [Port0, Port1]>] >, 356 InstrItinData<IIC_FNSTSW, [InstrStage<10, [Port0, Port1]>] >, 357 InstrItinData<IIC_FNSTCW, [InstrStage<8, [Port0, Port1]>] >, 358 InstrItinData<IIC_FLDCW, [InstrStage<5, [Port0, Port1]>] >, 359 InstrItinData<IIC_FNINIT, [InstrStage<63, [Port0, Port1]>] >, 360 InstrItinData<IIC_FFREE, [InstrStage<1, [Port0, Port1]>] >, 361 InstrItinData<IIC_FNCLEX, [InstrStage<25, [Port0, Port1]>] >, 362 InstrItinData<IIC_WAIT, [InstrStage<1, [Port0, Port1]>] >, 363 InstrItinData<IIC_FXAM, [InstrStage<1, [Port0]>] >, 364 InstrItinData<IIC_FNOP, [InstrStage<1, [Port0, Port1]>] >, 365 InstrItinData<IIC_FLDL, [InstrStage<10, [Port0, Port1]>] >, 366 InstrItinData<IIC_F2XM1, [InstrStage<99, [Port0, Port1]>] >, 367 InstrItinData<IIC_FYL2X, [InstrStage<146, [Port0, Port1]>] >, 368 InstrItinData<IIC_FPTAN, [InstrStage<168, [Port0, Port1]>] >, 369 InstrItinData<IIC_FPATAN, [InstrStage<183, [Port0, Port1]>] >, 370 InstrItinData<IIC_FXTRACT, [InstrStage<25, [Port0, Port1]>] >, 371 InstrItinData<IIC_FPREM1, [InstrStage<71, [Port0, Port1]>] >, 372 InstrItinData<IIC_FPSTP, [InstrStage<1, [Port0, Port1]>] >, 373 InstrItinData<IIC_FPREM, [InstrStage<55, [Port0, Port1]>] >, 374 InstrItinData<IIC_FYL2XP1, [InstrStage<147, [Port0, Port1]>] >, 375 InstrItinData<IIC_FSINCOS, [InstrStage<174, [Port0, Port1]>] >, 376 InstrItinData<IIC_FRNDINT, [InstrStage<46, [Port0, Port1]>] >, 377 InstrItinData<IIC_FSCALE, [InstrStage<77, [Port0, Port1]>] >, 378 InstrItinData<IIC_FCOMPP, [InstrStage<1, [Port1]>] >, 379 InstrItinData<IIC_FXSAVE, [InstrStage<140, [Port0, Port1]>] >, 380 InstrItinData<IIC_FXRSTOR, [InstrStage<141, [Port0, Port1]>] >, 381 InstrItinData<IIC_FXCH, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >, 382 383 // System instructions 384 InstrItinData<IIC_CPUID, [InstrStage<121, [Port0, Port1]>] >, 385 InstrItinData<IIC_INT, [InstrStage<127, [Port0, Port1]>] >, 386 InstrItinData<IIC_INT3, [InstrStage<130, [Port0, Port1]>] >, 387 InstrItinData<IIC_INVD, [InstrStage<1003, [Port0, Port1]>] >, 388 InstrItinData<IIC_INVLPG, [InstrStage<71, [Port0, Port1]>] >, 389 InstrItinData<IIC_IRET, [InstrStage<109, [Port0, Port1]>] >, 390 InstrItinData<IIC_HLT, [InstrStage<121, [Port0, Port1]>] >, 391 InstrItinData<IIC_LXS, [InstrStage<10, [Port0, Port1]>] >, 392 InstrItinData<IIC_LTR, [InstrStage<83, [Port0, Port1]>] >, 393 InstrItinData<IIC_RDTSC, [InstrStage<30, [Port0, Port1]>] >, 394 InstrItinData<IIC_RSM, [InstrStage<741, [Port0, Port1]>] >, 395 InstrItinData<IIC_SIDT, [InstrStage<4, [Port0, Port1]>] >, 396 InstrItinData<IIC_SGDT, [InstrStage<4, [Port0, Port1]>] >, 397 InstrItinData<IIC_SLDT, [InstrStage<3, [Port0, Port1]>] >, 398 InstrItinData<IIC_STR, [InstrStage<3, [Port0, Port1]>] >, 399 InstrItinData<IIC_SWAPGS, [InstrStage<22, [Port0, Port1]>] >, 400 InstrItinData<IIC_SYSCALL, [InstrStage<96, [Port0, Port1]>] >, 401 InstrItinData<IIC_SYS_ENTER_EXIT, [InstrStage<88, [Port0, Port1]>] >, 402 403 InstrItinData<IIC_IN_RR, [InstrStage<94, [Port0, Port1]>] >, 404 InstrItinData<IIC_IN_RI, [InstrStage<92, [Port0, Port1]>] >, 405 InstrItinData<IIC_OUT_RR, [InstrStage<68, [Port0, Port1]>] >, 406 InstrItinData<IIC_OUT_IR, [InstrStage<72, [Port0, Port1]>] >, 407 InstrItinData<IIC_INS, [InstrStage<59, [Port0, Port1]>] >, 408 409 InstrItinData<IIC_MOV_REG_DR, [InstrStage<88, [Port0, Port1]>] >, 410 InstrItinData<IIC_MOV_DR_REG, [InstrStage<123, [Port0, Port1]>] >, 411 // worst case for mov REG_CRx 412 InstrItinData<IIC_MOV_REG_CR, [InstrStage<12, [Port0, Port1]>] >, 413 InstrItinData<IIC_MOV_CR_REG, [InstrStage<136, [Port0, Port1]>] >, 414 415 InstrItinData<IIC_MOV_REG_SR, [InstrStage<1, [Port0]>] >, 416 InstrItinData<IIC_MOV_MEM_SR, [InstrStage<2, [Port0, Port1]>] >, 417 InstrItinData<IIC_MOV_SR_REG, [InstrStage<21, [Port0, Port1]>] >, 418 InstrItinData<IIC_MOV_SR_MEM, [InstrStage<26, [Port0, Port1]>] >, 419 // LAR 420 InstrItinData<IIC_LAR_RM, [InstrStage<50, [Port0, Port1]>] >, 421 InstrItinData<IIC_LAR_RR, [InstrStage<54, [Port0, Port1]>] >, 422 // LSL 423 InstrItinData<IIC_LSL_RM, [InstrStage<46, [Port0, Port1]>] >, 424 InstrItinData<IIC_LSL_RR, [InstrStage<49, [Port0, Port1]>] >, 425 426 InstrItinData<IIC_LGDT, [InstrStage<44, [Port0, Port1]>] >, 427 InstrItinData<IIC_LIDT, [InstrStage<44, [Port0, Port1]>] >, 428 InstrItinData<IIC_LLDT_REG, [InstrStage<60, [Port0, Port1]>] >, 429 InstrItinData<IIC_LLDT_MEM, [InstrStage<64, [Port0, Port1]>] >, 430 // push control register, segment registers 431 InstrItinData<IIC_PUSH_CS, [InstrStage<2, [Port0, Port1]>] >, 432 InstrItinData<IIC_PUSH_SR, [InstrStage<2, [Port0, Port1]>] >, 433 // pop control register, segment registers 434 InstrItinData<IIC_POP_SR, [InstrStage<29, [Port0, Port1]>] >, 435 InstrItinData<IIC_POP_SR_SS, [InstrStage<48, [Port0, Port1]>] >, 436 // VERR, VERW 437 InstrItinData<IIC_VERR, [InstrStage<41, [Port0, Port1]>] >, 438 InstrItinData<IIC_VERW_REG, [InstrStage<51, [Port0, Port1]>] >, 439 InstrItinData<IIC_VERW_MEM, [InstrStage<50, [Port0, Port1]>] >, 440 // WRMSR, RDMSR 441 InstrItinData<IIC_WRMSR, [InstrStage<202, [Port0, Port1]>] >, 442 InstrItinData<IIC_RDMSR, [InstrStage<78, [Port0, Port1]>] >, 443 InstrItinData<IIC_RDPMC, [InstrStage<46, [Port0, Port1]>] >, 444 // SMSW, LMSW 445 InstrItinData<IIC_SMSW, [InstrStage<9, [Port0, Port1]>] >, 446 InstrItinData<IIC_LMSW_REG, [InstrStage<69, [Port0, Port1]>] >, 447 InstrItinData<IIC_LMSW_MEM, [InstrStage<67, [Port0, Port1]>] >, 448 449 InstrItinData<IIC_ENTER, [InstrStage<32, [Port0, Port1]>] >, 450 InstrItinData<IIC_LEAVE, [InstrStage<2, [Port0, Port1]>] >, 451 452 InstrItinData<IIC_POP_MEM, [InstrStage<3, [Port0, Port1]>] >, 453 InstrItinData<IIC_POP_REG16, [InstrStage<2, [Port0, Port1]>] >, 454 InstrItinData<IIC_POP_REG, [InstrStage<1, [Port0], 0>, 455 InstrStage<1, [Port1]>] >, 456 InstrItinData<IIC_POP_F, [InstrStage<32, [Port0, Port1]>] >, 457 InstrItinData<IIC_POP_FD, [InstrStage<26, [Port0, Port1]>] >, 458 InstrItinData<IIC_POP_A, [InstrStage<9, [Port0, Port1]>] >, 459 460 InstrItinData<IIC_PUSH_IMM, [InstrStage<1, [Port0], 0>, 461 InstrStage<1, [Port1]>] >, 462 InstrItinData<IIC_PUSH_MEM, [InstrStage<2, [Port0, Port1]>] >, 463 InstrItinData<IIC_PUSH_REG, [InstrStage<1, [Port0], 0>, 464 InstrStage<1, [Port1]>] >, 465 InstrItinData<IIC_PUSH_F, [InstrStage<9, [Port0, Port1]>] >, 466 InstrItinData<IIC_PUSH_A, [InstrStage<8, [Port0, Port1]>] >, 467 468 InstrItinData<IIC_BSWAP, [InstrStage<1, [Port0]>] >, 469 InstrItinData<IIC_BSF, [InstrStage<16, [Port0, Port1]>] >, 470 InstrItinData<IIC_BSR, [InstrStage<16, [Port0, Port1]>] >, 471 InstrItinData<IIC_MOVS, [InstrStage<3, [Port0, Port1]>] >, 472 InstrItinData<IIC_STOS, [InstrStage<1, [Port0, Port1]>] >, 473 InstrItinData<IIC_SCAS, [InstrStage<2, [Port0, Port1]>] >, 474 InstrItinData<IIC_CMPS, [InstrStage<3, [Port0, Port1]>] >, 475 InstrItinData<IIC_MOV, [InstrStage<1, [Port0, Port1]>] >, 476 InstrItinData<IIC_MOV_MEM, [InstrStage<1, [Port0]>] >, 477 InstrItinData<IIC_AHF, [InstrStage<1, [Port0, Port1]>] >, 478 InstrItinData<IIC_BT_MI, [InstrStage<1, [Port0, Port1]>] >, 479 InstrItinData<IIC_BT_MR, [InstrStage<9, [Port0, Port1]>] >, 480 InstrItinData<IIC_BT_RI, [InstrStage<1, [Port1]>] >, 481 InstrItinData<IIC_BT_RR, [InstrStage<1, [Port1]>] >, 482 InstrItinData<IIC_BTX_MI, [InstrStage<2, [Port0, Port1]>] >, 483 InstrItinData<IIC_BTX_MR, [InstrStage<11, [Port0, Port1]>] >, 484 InstrItinData<IIC_BTX_RI, [InstrStage<1, [Port1]>] >, 485 InstrItinData<IIC_BTX_RR, [InstrStage<1, [Port1]>] >, 486 InstrItinData<IIC_XCHG_REG, [InstrStage<2, [Port0, Port1]>] >, 487 InstrItinData<IIC_XCHG_MEM, [InstrStage<3, [Port0, Port1]>] >, 488 InstrItinData<IIC_XADD_REG, [InstrStage<2, [Port0, Port1]>] >, 489 InstrItinData<IIC_XADD_MEM, [InstrStage<3, [Port0, Port1]>] >, 490 InstrItinData<IIC_CMPXCHG_MEM, [InstrStage<14, [Port0, Port1]>] >, 491 InstrItinData<IIC_CMPXCHG_REG, [InstrStage<15, [Port0, Port1]>] >, 492 InstrItinData<IIC_CMPXCHG_MEM8, [InstrStage<6, [Port0, Port1]>] >, 493 InstrItinData<IIC_CMPXCHG_REG8, [InstrStage<9, [Port0, Port1]>] >, 494 InstrItinData<IIC_CMPXCHG_8B, [InstrStage<18, [Port0, Port1]>] >, 495 InstrItinData<IIC_CMPXCHG_16B, [InstrStage<22, [Port0, Port1]>] >, 496 InstrItinData<IIC_LODS, [InstrStage<2, [Port0, Port1]>] >, 497 InstrItinData<IIC_OUTS, [InstrStage<74, [Port0, Port1]>] >, 498 InstrItinData<IIC_CLC, [InstrStage<1, [Port0, Port1]>] >, 499 InstrItinData<IIC_CLD, [InstrStage<3, [Port0, Port1]>] >, 500 InstrItinData<IIC_CLI, [InstrStage<14, [Port0, Port1]>] >, 501 InstrItinData<IIC_CMC, [InstrStage<1, [Port0, Port1]>] >, 502 InstrItinData<IIC_CLTS, [InstrStage<33, [Port0, Port1]>] >, 503 InstrItinData<IIC_STC, [InstrStage<1, [Port0, Port1]>] >, 504 InstrItinData<IIC_STI, [InstrStage<17, [Port0, Port1]>] >, 505 InstrItinData<IIC_STD, [InstrStage<21, [Port0, Port1]>] >, 506 InstrItinData<IIC_XLAT, [InstrStage<6, [Port0, Port1]>] >, 507 InstrItinData<IIC_AAA, [InstrStage<13, [Port0, Port1]>] >, 508 InstrItinData<IIC_AAD, [InstrStage<7, [Port0, Port1]>] >, 509 InstrItinData<IIC_AAM, [InstrStage<21, [Port0, Port1]>] >, 510 InstrItinData<IIC_AAS, [InstrStage<13, [Port0, Port1]>] >, 511 InstrItinData<IIC_DAA, [InstrStage<18, [Port0, Port1]>] >, 512 InstrItinData<IIC_DAS, [InstrStage<20, [Port0, Port1]>] >, 513 InstrItinData<IIC_BOUND, [InstrStage<11, [Port0, Port1]>] >, 514 InstrItinData<IIC_ARPL_REG, [InstrStage<24, [Port0, Port1]>] >, 515 InstrItinData<IIC_ARPL_MEM, [InstrStage<23, [Port0, Port1]>] >, 516 InstrItinData<IIC_MOVBE, [InstrStage<1, [Port0]>] >, 517 518 InstrItinData<IIC_NOP, [InstrStage<1, [Port0, Port1]>] > 519 ]>; 520 521 // Atom machine model. 522 def AtomModel : SchedMachineModel { 523 let IssueWidth = 2; // Allows 2 instructions per scheduling group. 524 let MinLatency = 1; // InstrStage cycles overrides MinLatency. 525 // OperandCycles may be used for expected latency. 526 let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles. 527 let HighLatency = 30;// Expected, may be overriden by OperandCycles. 528 let ILPWindow = 0; // Always try to hide expected latency. 529 530 let Itineraries = AtomItineraries; 531 } 532
