1 //===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the XCore instructions in TableGen format. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // Uses of CP, DP are not currently reflected in the patterns, since 15 // having a physical register as an operand prevents loop hoisting and 16 // since the value of these registers never changes during the life of the 17 // function. 18 19 //===----------------------------------------------------------------------===// 20 // Instruction format superclass. 21 //===----------------------------------------------------------------------===// 22 23 include "XCoreInstrFormats.td" 24 25 //===----------------------------------------------------------------------===// 26 // XCore specific DAG Nodes. 27 // 28 29 // Call 30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, 32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 33 SDNPVariadic]>; 34 35 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, 36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>; 37 38 def SDT_XCoreBR_JT : SDTypeProfile<0, 2, 39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 40 41 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT, 42 [SDNPHasChain]>; 43 44 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT, 45 [SDNPHasChain]>; 46 47 def SDT_XCoreAddress : SDTypeProfile<1, 1, 48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 49 50 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, 51 []>; 52 53 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, 54 []>; 55 56 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, 57 []>; 58 59 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; 60 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, 61 [SDNPHasChain, SDNPMayStore]>; 62 63 // These are target-independent nodes, but have target-specific formats. 64 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 65 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 66 SDTCisVT<1, i32> ]>; 67 68 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart, 69 [SDNPHasChain, SDNPOutGlue]>; 70 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd, 71 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 72 73 //===----------------------------------------------------------------------===// 74 // Instruction Pattern Stuff 75 //===----------------------------------------------------------------------===// 76 77 def div4_xform : SDNodeXForm<imm, [{ 78 // Transformation function: imm/4 79 assert(N->getZExtValue() % 4 == 0); 80 return getI32Imm(N->getZExtValue()/4); 81 }]>; 82 83 def msksize_xform : SDNodeXForm<imm, [{ 84 // Transformation function: get the size of a mask 85 assert(isMask_32(N->getZExtValue())); 86 // look for the first non-zero bit 87 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue())); 88 }]>; 89 90 def neg_xform : SDNodeXForm<imm, [{ 91 // Transformation function: -imm 92 uint32_t value = N->getZExtValue(); 93 return getI32Imm(-value); 94 }]>; 95 96 def bpwsub_xform : SDNodeXForm<imm, [{ 97 // Transformation function: 32-imm 98 uint32_t value = N->getZExtValue(); 99 return getI32Imm(32-value); 100 }]>; 101 102 def div4neg_xform : SDNodeXForm<imm, [{ 103 // Transformation function: -imm/4 104 uint32_t value = N->getZExtValue(); 105 assert(-value % 4 == 0); 106 return getI32Imm(-value/4); 107 }]>; 108 109 def immUs4Neg : PatLeaf<(imm), [{ 110 uint32_t value = (uint32_t)N->getZExtValue(); 111 return (-value)%4 == 0 && (-value)/4 <= 11; 112 }]>; 113 114 def immUs4 : PatLeaf<(imm), [{ 115 uint32_t value = (uint32_t)N->getZExtValue(); 116 return value%4 == 0 && value/4 <= 11; 117 }]>; 118 119 def immUsNeg : PatLeaf<(imm), [{ 120 return -((uint32_t)N->getZExtValue()) <= 11; 121 }]>; 122 123 def immUs : PatLeaf<(imm), [{ 124 return (uint32_t)N->getZExtValue() <= 11; 125 }]>; 126 127 def immU6 : PatLeaf<(imm), [{ 128 return (uint32_t)N->getZExtValue() < (1 << 6); 129 }]>; 130 131 def immU10 : PatLeaf<(imm), [{ 132 return (uint32_t)N->getZExtValue() < (1 << 10); 133 }]>; 134 135 def immU16 : PatLeaf<(imm), [{ 136 return (uint32_t)N->getZExtValue() < (1 << 16); 137 }]>; 138 139 def immU20 : PatLeaf<(imm), [{ 140 return (uint32_t)N->getZExtValue() < (1 << 20); 141 }]>; 142 143 def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>; 144 145 def immBitp : PatLeaf<(imm), [{ 146 uint32_t value = (uint32_t)N->getZExtValue(); 147 return (value >= 1 && value <= 8) 148 || value == 16 149 || value == 24 150 || value == 32; 151 }]>; 152 153 def immBpwSubBitp : PatLeaf<(imm), [{ 154 uint32_t value = (uint32_t)N->getZExtValue(); 155 return (value >= 24 && value <= 31) 156 || value == 16 157 || value == 8 158 || value == 0; 159 }]>; 160 161 def lda16f : PatFrag<(ops node:$addr, node:$offset), 162 (add node:$addr, (shl node:$offset, 1))>; 163 def lda16b : PatFrag<(ops node:$addr, node:$offset), 164 (sub node:$addr, (shl node:$offset, 1))>; 165 def ldawf : PatFrag<(ops node:$addr, node:$offset), 166 (add node:$addr, (shl node:$offset, 2))>; 167 def ldawb : PatFrag<(ops node:$addr, node:$offset), 168 (sub node:$addr, (shl node:$offset, 2))>; 169 170 // Instruction operand types 171 def calltarget : Operand<i32>; 172 def brtarget : Operand<OtherVT>; 173 def pclabel : Operand<i32>; 174 175 // Addressing modes 176 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; 177 def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper], 178 []>; 179 def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper], 180 []>; 181 182 // Address operands 183 def MEMii : Operand<i32> { 184 let PrintMethod = "printMemOperand"; 185 let DecoderMethod = "DecodeMEMiiOperand"; 186 let MIOperandInfo = (ops i32imm, i32imm); 187 } 188 189 // Jump tables. 190 def InlineJT : Operand<i32> { 191 let PrintMethod = "printInlineJT"; 192 } 193 194 def InlineJT32 : Operand<i32> { 195 let PrintMethod = "printInlineJT32"; 196 } 197 198 //===----------------------------------------------------------------------===// 199 // Instruction Class Templates 200 //===----------------------------------------------------------------------===// 201 202 // Three operand short 203 204 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> { 205 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 206 !strconcat(OpcStr, " $dst, $b, $c"), 207 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 208 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 209 !strconcat(OpcStr, " $dst, $b, $c"), 210 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 211 } 212 213 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> { 214 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 215 !strconcat(OpcStr, " $dst, $b, $c"), []>; 216 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 217 !strconcat(OpcStr, " $dst, $b, $c"), []>; 218 } 219 220 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr, 221 SDNode OpNode> { 222 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 223 !strconcat(OpcStr, " $dst, $b, $c"), 224 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 225 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 226 !strconcat(OpcStr, " $dst, $b, $c"), 227 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 228 } 229 230 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> : 231 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 232 !strconcat(OpcStr, " $dst, $b, $c"), 233 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 234 235 class F3R_np<bits<5> opc, string OpcStr> : 236 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 237 !strconcat(OpcStr, " $dst, $b, $c"), []>; 238 // Three operand long 239 240 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 241 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr, 242 SDNode OpNode> { 243 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 244 !strconcat(OpcStr, " $dst, $b, $c"), 245 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 246 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 247 !strconcat(OpcStr, " $dst, $b, $c"), 248 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 249 } 250 251 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 252 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr, 253 SDNode OpNode> { 254 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 255 !strconcat(OpcStr, " $dst, $b, $c"), 256 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 257 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 258 !strconcat(OpcStr, " $dst, $b, $c"), 259 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 260 } 261 262 class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> : 263 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 264 !strconcat(OpcStr, " $dst, $b, $c"), 265 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 266 267 // Register - U6 268 // Operand register - U6 269 multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> { 270 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 271 !strconcat(OpcStr, " $a, $b"), []>; 272 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 273 !strconcat(OpcStr, " $a, $b"), []>; 274 } 275 276 multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> { 277 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 278 !strconcat(OpcStr, " $a, -$b"), []>; 279 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 280 !strconcat(OpcStr, " $a, -$b"), []>; 281 } 282 283 multiclass FRU6_LRU6_cp<bits<6> opc, string OpcStr> { 284 def _ru6: _FRU6<opc, (outs GRRegs:$a), (ins i32imm:$b), 285 !strconcat(OpcStr, " $a, cp[$b]"), []>; 286 def _lru6: _FLRU6<opc, (outs GRRegs:$a), (ins i32imm:$b), 287 !strconcat(OpcStr, " $a, cp[$b]"), []>; 288 } 289 290 // U6 291 multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> { 292 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 293 [(OpNode immU6:$a)]>; 294 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 295 [(OpNode immU16:$a)]>; 296 } 297 298 multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> { 299 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 300 [(Int immU6:$a)]>; 301 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 302 [(Int immU16:$a)]>; 303 } 304 305 multiclass FU6_LU6_np<bits<10> opc, string OpcStr> { 306 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; 307 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; 308 } 309 310 // Two operand short 311 312 class F2R_np<bits<6> opc, string OpcStr> : 313 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b), 314 !strconcat(OpcStr, " $dst, $b"), []>; 315 316 // Two operand long 317 318 //===----------------------------------------------------------------------===// 319 // Pseudo Instructions 320 //===----------------------------------------------------------------------===// 321 322 let Defs = [SP], Uses = [SP] in { 323 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt), 324 "# ADJCALLSTACKDOWN $amt", 325 [(callseq_start timm:$amt)]>; 326 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), 327 "# ADJCALLSTACKUP $amt1", 328 [(callseq_end timm:$amt1, timm:$amt2)]>; 329 } 330 331 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 332 "# LDWFI $dst, $addr", 333 [(set GRRegs:$dst, (load ADDRspii:$addr))]>; 334 335 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 336 "# LDAWFI $dst, $addr", 337 [(set GRRegs:$dst, ADDRspii:$addr)]>; 338 339 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), 340 "# STWFI $src, $addr", 341 [(store GRRegs:$src, ADDRspii:$addr)]>; 342 343 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 344 // instruction selection into a branch sequence. 345 let usesCustomInserter = 1 in { 346 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), 347 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), 348 "# SELECT_CC PSEUDO!", 349 [(set GRRegs:$dst, 350 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; 351 } 352 353 //===----------------------------------------------------------------------===// 354 // Instructions 355 //===----------------------------------------------------------------------===// 356 357 // Three operand short 358 defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>; 359 defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>; 360 let neverHasSideEffects = 1 in { 361 defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">; 362 def LSS_3r : F3R_np<0b11000, "lss">; 363 def LSU_3r : F3R_np<0b11001, "lsu">; 364 } 365 def AND_3r : F3R<0b00111, "and", and>; 366 def OR_3r : F3R<0b01000, "or", or>; 367 368 let mayLoad=1 in { 369 def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst), 370 (ins GRRegs:$addr, GRRegs:$offset), 371 "ldw $dst, $addr[$offset]", []>; 372 373 def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst), 374 (ins GRRegs:$addr, i32imm:$offset), 375 "ldw $dst, $addr[$offset]", []>; 376 377 def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst), 378 (ins GRRegs:$addr, GRRegs:$offset), 379 "ld16s $dst, $addr[$offset]", []>; 380 381 def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst), 382 (ins GRRegs:$addr, GRRegs:$offset), 383 "ld8u $dst, $addr[$offset]", []>; 384 } 385 386 let mayStore=1 in { 387 def STW_l3r : _FL3R<0b000001100, (outs), 388 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 389 "stw $val, $addr[$offset]", []>; 390 391 def STW_2rus : _F2RUS<0b0000, (outs), 392 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), 393 "stw $val, $addr[$offset]", []>; 394 } 395 396 defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>; 397 defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>; 398 399 // The first operand is treated as an immediate since it refers to a register 400 // number in another thread. 401 def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c), 402 "set t[$c]:r$a, $b", []>; 403 404 // Three operand long 405 def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst), 406 (ins GRRegs:$addr, GRRegs:$offset), 407 "ldaw $dst, $addr[$offset]", 408 [(set GRRegs:$dst, 409 (ldawf GRRegs:$addr, GRRegs:$offset))]>; 410 411 let neverHasSideEffects = 1 in 412 def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst), 413 (ins GRRegs:$addr, i32imm:$offset), 414 "ldaw $dst, $addr[$offset]", []>; 415 416 def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst), 417 (ins GRRegs:$addr, GRRegs:$offset), 418 "ldaw $dst, $addr[-$offset]", 419 [(set GRRegs:$dst, 420 (ldawb GRRegs:$addr, GRRegs:$offset))]>; 421 422 let neverHasSideEffects = 1 in 423 def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst), 424 (ins GRRegs:$addr, i32imm:$offset), 425 "ldaw $dst, $addr[-$offset]", []>; 426 427 def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst), 428 (ins GRRegs:$addr, GRRegs:$offset), 429 "lda16 $dst, $addr[$offset]", 430 [(set GRRegs:$dst, 431 (lda16f GRRegs:$addr, GRRegs:$offset))]>; 432 433 def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst), 434 (ins GRRegs:$addr, GRRegs:$offset), 435 "lda16 $dst, $addr[-$offset]", 436 [(set GRRegs:$dst, 437 (lda16b GRRegs:$addr, GRRegs:$offset))]>; 438 439 def MUL_l3r : FL3R<0b001111100, "mul", mul>; 440 // Instructions which may trap are marked as side effecting. 441 let hasSideEffects = 1 in { 442 def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>; 443 def DIVU_l3r : FL3R<0b010011100, "divu", udiv>; 444 def REMS_l3r : FL3R<0b110001100, "rems", srem>; 445 def REMU_l3r : FL3R<0b110011100, "remu", urem>; 446 } 447 def XOR_l3r : FL3R<0b000011100, "xor", xor>; 448 defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>; 449 450 let Constraints = "$src1 = $dst" in 451 def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst), 452 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 453 "crc32 $dst, $src2, $src3", 454 [(set GRRegs:$dst, 455 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, 456 GRRegs:$src3))]>; 457 458 let mayStore=1 in { 459 def ST16_l3r : _FL3R<0b100001100, (outs), 460 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 461 "st16 $val, $addr[$offset]", []>; 462 463 def ST8_l3r : _FL3R<0b100011100, (outs), 464 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 465 "st8 $val, $addr[$offset]", []>; 466 } 467 468 def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a), 469 (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c", 470 []>; 471 472 def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs), 473 (ins GRRegs:$a, GRRegs:$b, i32imm:$c), 474 "outpw res[$b], $a, $c", []>; 475 476 // Four operand long 477 let Constraints = "$e = $a,$f = $b" in { 478 def MACCU_l4r : _FL4RSrcDstSrcDst< 479 0b000001, (outs GRRegs:$a, GRRegs:$b), 480 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>; 481 482 def MACCS_l4r : _FL4RSrcDstSrcDst< 483 0b000010, (outs GRRegs:$a, GRRegs:$b), 484 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>; 485 } 486 487 let Constraints = "$e = $b" in 488 def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b), 489 (ins GRRegs:$e, GRRegs:$c, GRRegs:$d), 490 "crc8 $b, $a, $c, $d", []>; 491 492 // Five operand long 493 494 def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2), 495 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 496 "ladd $dst2, $dst1, $src1, $src2, $src3", 497 []>; 498 499 def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2), 500 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 501 "lsub $dst2, $dst1, $src1, $src2, $src3", []>; 502 503 def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2), 504 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 505 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>; 506 507 // Six operand long 508 509 def LMUL_l6r : _FL6R< 510 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2), 511 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4), 512 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>; 513 514 // Register - U6 515 516 //let Uses = [DP] in ... 517 let neverHasSideEffects = 1, isReMaterializable = 1 in 518 def LDAWDP_ru6: _FRU6<0b011000, (outs GRRegs:$a), (ins MEMii:$b), 519 "ldaw $a, dp[$b]", []>; 520 521 let isReMaterializable = 1 in 522 def LDAWDP_lru6: _FLRU6<0b011000, (outs GRRegs:$a), (ins MEMii:$b), 523 "ldaw $a, dp[$b]", 524 [(set GRRegs:$a, ADDRdpii:$b)]>; 525 526 let mayLoad=1 in 527 def LDWDP_ru6: _FRU6<0b010110, (outs GRRegs:$a), (ins MEMii:$b), 528 "ldw $a, dp[$b]", []>; 529 530 def LDWDP_lru6: _FLRU6<0b010110, (outs GRRegs:$a), (ins MEMii:$b), 531 "ldw $a, dp[$b]", 532 [(set GRRegs:$a, (load ADDRdpii:$b))]>; 533 534 let mayStore=1 in 535 def STWDP_ru6 : _FRU6<0b010100, (outs), (ins GRRegs:$a, MEMii:$b), 536 "stw $a, dp[$b]", []>; 537 538 def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins GRRegs:$a, MEMii:$b), 539 "stw $a, dp[$b]", 540 [(store GRRegs:$a, ADDRdpii:$b)]>; 541 542 //let Uses = [CP] in .. 543 let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in 544 defm LDWCP : FRU6_LRU6_cp<0b011011, "ldw">; 545 546 let Uses = [SP] in { 547 let mayStore=1 in { 548 def STWSP_ru6 : _FRU6<0b010101, (outs), (ins GRRegs:$a, i32imm:$b), 549 "stw $a, sp[$b]", 550 [(XCoreStwsp GRRegs:$a, immU6:$b)]>; 551 552 def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins GRRegs:$a, i32imm:$b), 553 "stw $a, sp[$b]", 554 [(XCoreStwsp GRRegs:$a, immU16:$b)]>; 555 } 556 557 let mayLoad=1 in { 558 def LDWSP_ru6 : _FRU6<0b010111, (outs GRRegs:$a), (ins i32imm:$b), 559 "ldw $a, sp[$b]", []>; 560 561 def LDWSP_lru6 : _FLRU6<0b010111, (outs GRRegs:$a), (ins i32imm:$b), 562 "ldw $a, sp[$b]", []>; 563 } 564 565 let neverHasSideEffects = 1 in { 566 def LDAWSP_ru6 : _FRU6<0b011001, (outs GRRegs:$a), (ins i32imm:$b), 567 "ldaw $a, sp[$b]", []>; 568 569 def LDAWSP_lru6 : _FLRU6<0b011001, (outs GRRegs:$a), (ins i32imm:$b), 570 "ldaw $a, sp[$b]", []>; 571 572 let isCodeGenOnly = 1 in 573 def LDAWSP_ru6_RRegs : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), 574 "ldaw $a, sp[$b]", []>; 575 576 let isCodeGenOnly = 1 in 577 def LDAWSP_lru6_RRegs : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), 578 "ldaw $a, sp[$b]", []>; 579 } 580 } 581 582 let isReMaterializable = 1 in { 583 def LDC_ru6 : _FRU6<0b011010, (outs GRRegs:$a), (ins i32imm:$b), 584 "ldc $a, $b", [(set GRRegs:$a, immU6:$b)]>; 585 586 def LDC_lru6 : _FLRU6<0b011010, (outs GRRegs:$a), (ins i32imm:$b), 587 "ldc $a, $b", [(set GRRegs:$a, immU16:$b)]>; 588 } 589 590 def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), 591 "setc res[$a], $b", 592 [(int_xcore_setc GRRegs:$a, immU6:$b)]>; 593 594 def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), 595 "setc res[$a], $b", 596 [(int_xcore_setc GRRegs:$a, immU16:$b)]>; 597 598 // Operand register - U6 599 let isBranch = 1, isTerminator = 1 in { 600 defm BRFT: FRU6_LRU6_branch<0b011100, "bt">; 601 defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">; 602 defm BRFF: FRU6_LRU6_branch<0b011110, "bf">; 603 defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">; 604 } 605 606 // U6 607 let Defs = [SP], Uses = [SP] in { 608 let neverHasSideEffects = 1 in 609 defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">; 610 611 let mayStore = 1 in 612 defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">; 613 614 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 615 defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>; 616 } 617 } 618 619 let neverHasSideEffects = 1 in 620 defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">; 621 622 let Uses = [R11], isCall=1 in 623 defm BLAT : FU6_LU6_np<0b0111001101, "blat">; 624 625 let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 626 def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>; 627 628 def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>; 629 630 def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; 631 632 def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; 633 } 634 635 //let Uses = [CP] in ... 636 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in 637 def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]", 638 []>; 639 640 let Defs = [R11], isReMaterializable = 1 in 641 def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]", 642 [(set R11, ADDRcpii:$a)]>; 643 644 let Defs = [R11] in 645 defm GETSR : FU6_LU6_np<0b0111111100, "getsr r11,">; 646 647 defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>; 648 649 defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>; 650 651 // setsr may cause a branch if it is used to enable events. clrsr may 652 // branch if it is executed while events are enabled. 653 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 654 isCodeGenOnly = 1 in { 655 defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">; 656 defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">; 657 } 658 659 defm KCALL : FU6_LU6_np<0b0111001111, "kcall">; 660 661 let Uses = [SP], Defs = [SP], mayStore = 1 in 662 defm KENTSP : FU6_LU6_np<0b0111101110, "kentsp">; 663 664 let Uses = [SP], Defs = [SP], mayLoad = 1 in 665 defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">; 666 667 // U10 668 669 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in 670 def LDAPF_u10 : _FU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", []>; 671 672 let Defs = [R11], isReMaterializable = 1 in 673 def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", 674 [(set R11, (pcrelwrapper tglobaladdr:$a))]>; 675 676 let Defs = [R11], isReMaterializable = 1, isCodeGenOnly = 1 in 677 def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", 678 [(set R11, (pcrelwrapper tblockaddress:$a))]>; 679 680 let isCall=1, 681 // All calls clobber the link register and the non-callee-saved registers: 682 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 683 def BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; 684 685 def BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; 686 687 def BLRF_u10 : _FU10<0b110100, (outs), (ins calltarget:$a), "bl $a", 688 [(XCoreBranchLink immU10:$a)]>; 689 690 def BLRF_lu10 : _FLU10<0b110100, (outs), (ins calltarget:$a), "bl $a", 691 [(XCoreBranchLink immU20:$a)]>; 692 } 693 694 let Defs = [R11], mayLoad = 1, isReMaterializable = 1, 695 neverHasSideEffects = 1 in { 696 def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>; 697 698 def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", 699 []>; 700 } 701 702 // Two operand short 703 def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b), 704 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>; 705 706 def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b), 707 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>; 708 709 let Constraints = "$src1 = $dst" in { 710 def SEXT_rus : 711 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 712 "sext $dst, $src2", 713 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, 714 immBitp:$src2))]>; 715 716 def SEXT_2r : 717 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 718 "sext $dst, $src2", 719 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>; 720 721 def ZEXT_rus : 722 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 723 "zext $dst, $src2", 724 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, 725 immBitp:$src2))]>; 726 727 def ZEXT_2r : 728 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 729 "zext $dst, $src2", 730 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>; 731 732 def ANDNOT_2r : 733 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 734 "andnot $dst, $src2", 735 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; 736 } 737 738 let isReMaterializable = 1, neverHasSideEffects = 1 in 739 def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size), 740 "mkmsk $dst, $size", []>; 741 742 def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size), 743 "mkmsk $dst, $size", 744 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>; 745 746 def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type), 747 "getr $dst, $type", 748 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>; 749 750 def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r), 751 "getts $dst, res[$r]", 752 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>; 753 754 def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val), 755 "setpt res[$r], $val", 756 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>; 757 758 def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val), 759 "outct res[$r], $val", 760 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>; 761 762 def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val), 763 "outct res[$r], $val", 764 [(int_xcore_outct GRRegs:$r, immUs:$val)]>; 765 766 def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val), 767 "outt res[$r], $val", 768 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>; 769 770 def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val), 771 "out res[$r], $val", 772 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>; 773 774 let Constraints = "$src = $dst" in 775 def OUTSHR_2r : 776 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), 777 "outshr res[$r], $src", 778 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>; 779 780 def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r), 781 "inct $dst, res[$r]", 782 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>; 783 784 def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r), 785 "int $dst, res[$r]", 786 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>; 787 788 def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r), 789 "in $dst, res[$r]", 790 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>; 791 792 let Constraints = "$src = $dst" in 793 def INSHR_2r : 794 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), 795 "inshr $dst, res[$r]", 796 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>; 797 798 def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val), 799 "chkct res[$r], $val", 800 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>; 801 802 def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val), 803 "chkct res[$r], $val", 804 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>; 805 806 def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src), 807 "testct $dst, res[$src]", 808 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>; 809 810 def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src), 811 "testwct $dst, res[$src]", 812 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>; 813 814 def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val), 815 "setd res[$r], $val", 816 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; 817 818 def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 819 "setpsc res[$src1], $src2", 820 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; 821 822 def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r), 823 "getst $dst, res[$r]", 824 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>; 825 826 def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t), 827 "init t[$t]:sp, $src", 828 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>; 829 830 def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t), 831 "init t[$t]:pc, $src", 832 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>; 833 834 def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t), 835 "init t[$t]:cp, $src", 836 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>; 837 838 def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t), 839 "init t[$t]:dp, $src", 840 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>; 841 842 def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src), 843 "peek $dst, res[$src]", 844 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>; 845 846 def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src), 847 "endin $dst, res[$src]", 848 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>; 849 850 def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b), 851 "eef $a, res[$b]", []>; 852 853 def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b), 854 "eet $a, res[$b]", []>; 855 856 def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b), 857 "tsetmr r$a, $b", []>; 858 859 // Two operand long 860 def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src), 861 "bitrev $dst, $src", 862 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; 863 864 def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src), 865 "byterev $dst, $src", 866 [(set GRRegs:$dst, (bswap GRRegs:$src))]>; 867 868 def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src), 869 "clz $dst, $src", 870 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; 871 872 def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src), 873 "getd $dst, res[$src]", []>; 874 875 def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src), 876 "getn $dst, res[$src]", []>; 877 878 def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val), 879 "setc res[$r], $val", 880 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>; 881 882 def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val), 883 "settw res[$r], $val", 884 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>; 885 886 def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src), 887 "get $dst, ps[$src]", 888 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>; 889 890 def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 891 "set ps[$src1], $src2", 892 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>; 893 894 def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t), 895 "init t[$t]:lr, $src", 896 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>; 897 898 def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2), 899 "setclk res[$src1], $src2", 900 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>; 901 902 def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 903 "setn res[$src1], $src2", []>; 904 905 def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 906 "setrdy res[$src1], $src2", 907 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>; 908 909 def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src), 910 "testlcl $dst, res[$src]", []>; 911 912 // One operand short 913 def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a), 914 "msync res[$a]", 915 [(int_xcore_msync GRRegs:$a)]>; 916 def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a), 917 "mjoin res[$a]", 918 [(int_xcore_mjoin GRRegs:$a)]>; 919 920 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 921 def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a), 922 "bau $a", 923 [(brind GRRegs:$a)]>; 924 925 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 926 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i), 927 "bru $i\n$t", 928 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>; 929 930 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 931 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), 932 "bru $i\n$t", 933 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; 934 935 let Defs=[SP], neverHasSideEffects=1 in 936 def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>; 937 938 let neverHasSideEffects=1 in 939 def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>; 940 941 let neverHasSideEffects=1 in 942 def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>; 943 944 let hasCtrlDep = 1 in 945 def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a), 946 "ecallt $a", 947 []>; 948 949 let hasCtrlDep = 1 in 950 def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a), 951 "ecallf $a", 952 []>; 953 954 let isCall=1, 955 // All calls clobber the link register and the non-callee-saved registers: 956 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 957 def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a), 958 "bla $a", 959 [(XCoreBranchLink GRRegs:$a)]>; 960 } 961 962 def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a), 963 "syncr res[$a]", 964 [(int_xcore_syncr GRRegs:$a)]>; 965 966 def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a), 967 "freer res[$a]", 968 [(int_xcore_freer GRRegs:$a)]>; 969 970 let Uses=[R11] in { 971 def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a), 972 "setv res[$a], r11", 973 [(int_xcore_setv GRRegs:$a, R11)]>; 974 975 def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a), 976 "setev res[$a], r11", 977 [(int_xcore_setev GRRegs:$a, R11)]>; 978 } 979 980 def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>; 981 982 def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", []>; 983 984 def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a), 985 "eeu res[$a]", 986 [(int_xcore_eeu GRRegs:$a)]>; 987 988 def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>; 989 990 def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>; 991 992 def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>; 993 994 def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>; 995 996 def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", []>; 997 998 // Zero operand short 999 1000 def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>; 1001 1002 def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>; 1003 1004 let Defs = [SP], Uses = [SP] in 1005 def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>; 1006 1007 let Defs = [SP] in 1008 def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>; 1009 1010 def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>; 1011 1012 def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>; 1013 1014 let Defs = [R11] in { 1015 def GETID_0R : _F0R<0b0001001110, (outs), (ins), 1016 "get r11, id", 1017 [(set R11, (int_xcore_getid))]>; 1018 1019 def GETED_0R : _F0R<0b0000111110, (outs), (ins), 1020 "get r11, ed", 1021 [(set R11, (int_xcore_geted))]>; 1022 1023 def GETET_0R : _F0R<0b0000111111, (outs), (ins), 1024 "get r11, et", 1025 [(set R11, (int_xcore_getet))]>; 1026 1027 def GETKEP_0R : _F0R<0b0001001111, (outs), (ins), 1028 "get r11, kep", []>; 1029 1030 def GETKSP_0R : _F0R<0b0001011100, (outs), (ins), 1031 "get r11, ksp", []>; 1032 } 1033 1034 let Defs = [SP] in 1035 def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>; 1036 1037 let Uses = [SP], mayLoad = 1 in { 1038 def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>; 1039 1040 def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>; 1041 1042 def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>; 1043 1044 def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>; 1045 } 1046 1047 let Uses=[R11] in 1048 def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>; 1049 1050 def SSYNC_0r : _F0R<0b0000001110, (outs), (ins), 1051 "ssync", 1052 [(int_xcore_ssync)]>; 1053 1054 let Uses = [SP], mayStore = 1 in { 1055 def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>; 1056 1057 def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>; 1058 1059 def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>; 1060 1061 def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>; 1062 } 1063 1064 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 1065 hasSideEffects = 1 in 1066 def WAITEU_0R : _F0R<0b0000001100, (outs), (ins), 1067 "waiteu", 1068 [(brind (int_xcore_waitevent))]>; 1069 1070 //===----------------------------------------------------------------------===// 1071 // Non-Instruction Patterns 1072 //===----------------------------------------------------------------------===// 1073 1074 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BLRF_lu10 tglobaladdr:$addr)>; 1075 def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>; 1076 1077 /// sext_inreg 1078 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; 1079 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>; 1080 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>; 1081 1082 /// loads 1083 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1084 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1085 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1086 1087 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1088 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1089 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1090 1091 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)), 1092 (LDW_3r GRRegs:$addr, GRRegs:$offset)>; 1093 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)), 1094 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1095 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>; 1096 1097 /// anyext 1098 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1099 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1100 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1101 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1102 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1103 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1104 1105 /// stores 1106 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), 1107 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1108 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), 1109 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1110 1111 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), 1112 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1113 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), 1114 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1115 1116 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), 1117 (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1118 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), 1119 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; 1120 def : Pat<(store GRRegs:$val, GRRegs:$addr), 1121 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; 1122 1123 /// cttz 1124 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; 1125 1126 /// trap 1127 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; 1128 1129 /// 1130 /// branch patterns 1131 /// 1132 1133 // unconditional branch 1134 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>; 1135 1136 // direct match equal/notequal zero brcond 1137 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst), 1138 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>; 1139 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst), 1140 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>; 1141 1142 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1143 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1144 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1145 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1146 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1147 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1148 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1149 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1150 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1151 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1152 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst), 1153 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>; 1154 1155 // generic brcond pattern 1156 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>; 1157 1158 1159 /// 1160 /// Select patterns 1161 /// 1162 1163 // direct match equal/notequal zero select 1164 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1165 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>; 1166 1167 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1168 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>; 1169 1170 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1171 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1172 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1173 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1174 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1175 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1176 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1177 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1178 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1179 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1180 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F), 1181 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>; 1182 1183 /// 1184 /// setcc patterns, only matched when none of the above brcond 1185 /// patterns match 1186 /// 1187 1188 // setcc 2 register operands 1189 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs), 1190 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1191 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs), 1192 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1193 1194 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 1195 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>; 1196 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs), 1197 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>; 1198 1199 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs), 1200 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1201 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs), 1202 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1203 1204 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 1205 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>; 1206 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs), 1207 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>; 1208 1209 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs), 1210 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1211 1212 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs), 1213 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>; 1214 1215 // setcc reg/imm operands 1216 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs), 1217 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>; 1218 def : Pat<(setne GRRegs:$lhs, immUs:$rhs), 1219 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>; 1220 1221 // misc 1222 def : Pat<(add GRRegs:$addr, immUs4:$offset), 1223 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1224 1225 def : Pat<(sub GRRegs:$addr, immUs4:$offset), 1226 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1227 1228 def : Pat<(and GRRegs:$val, immMskBitp:$mask), 1229 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>; 1230 1231 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1232 def : Pat<(add GRRegs:$src1, immUsNeg:$src2), 1233 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>; 1234 1235 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2), 1236 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>; 1237 1238 /// 1239 /// Some peepholes 1240 /// 1241 1242 def : Pat<(mul GRRegs:$src, 3), 1243 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>; 1244 1245 def : Pat<(mul GRRegs:$src, 5), 1246 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>; 1247 1248 def : Pat<(mul GRRegs:$src, -3), 1249 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>; 1250 1251 // ashr X, 32 is equivalent to ashr X, 31 on the XCore. 1252 def : Pat<(sra GRRegs:$src, 31), 1253 (ASHR_l2rus GRRegs:$src, 32)>; 1254 1255 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1256 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1257 1258 // setge X, 0 is canonicalized to setgt X, -1 1259 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1260 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1261 1262 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1263 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; 1264 1265 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1266 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; 1267 1268 def : Pat<(setgt GRRegs:$lhs, -1), 1269 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; 1270 1271 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), 1272 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; 1273
