1 ; RUN: llc -mtriple=thumbv7-apple-ios -disable-code-place < %s | FileCheck %s 2 ; RUN: llc -mtriple=armv7-apple-ios -disable-code-place < %s | FileCheck %s 3 4 ; LSR should compare against the post-incremented induction variable. 5 ; In this case, the immediate value is -2 which requires a cmn instruction. 6 ; 7 ; CHECK: f: 8 ; CHECK: %for.body 9 ; CHECK: sub{{.*}}[[IV:r[0-9]+]], #2 10 ; CHECK: cmn{{.*}}[[IV]], #2 11 ; CHECK: bne 12 define i32 @f(i32* nocapture %a, i32 %i) nounwind readonly ssp { 13 entry: 14 %cmp3 = icmp eq i32 %i, -2 15 br i1 %cmp3, label %for.end, label %for.body 16 17 for.body: ; preds = %entry, %for.body 18 %bi.06 = phi i32 [ %i.addr.0.bi.0, %for.body ], [ 0, %entry ] 19 %i.addr.05 = phi i32 [ %sub, %for.body ], [ %i, %entry ] 20 %b.04 = phi i32 [ %.b.0, %for.body ], [ 0, %entry ] 21 %arrayidx = getelementptr inbounds i32* %a, i32 %i.addr.05 22 %0 = load i32* %arrayidx, align 4 23 %cmp1 = icmp sgt i32 %0, %b.04 24 %.b.0 = select i1 %cmp1, i32 %0, i32 %b.04 25 %i.addr.0.bi.0 = select i1 %cmp1, i32 %i.addr.05, i32 %bi.06 26 %sub = add nsw i32 %i.addr.05, -2 27 %cmp = icmp eq i32 %i.addr.05, 0 28 br i1 %cmp, label %for.end, label %for.body 29 30 for.end: ; preds = %for.body, %entry 31 %bi.0.lcssa = phi i32 [ 0, %entry ], [ %i.addr.0.bi.0, %for.body ] 32 ret i32 %bi.0.lcssa 33 } 34
