1 ; RUN: llc < %s -march=arm | FileCheck %s 2 3 define i32 @t9(i32 %v) nounwind readnone { 4 entry: 5 ; CHECK: t9: 6 ; CHECK: add r0, r0, r0, lsl #3 7 %0 = mul i32 %v, 9 8 ret i32 %0 9 } 10 11 define i32 @t7(i32 %v) nounwind readnone { 12 entry: 13 ; CHECK: t7: 14 ; CHECK: rsb r0, r0, r0, lsl #3 15 %0 = mul i32 %v, 7 16 ret i32 %0 17 } 18 19 define i32 @t5(i32 %v) nounwind readnone { 20 entry: 21 ; CHECK: t5: 22 ; CHECK: add r0, r0, r0, lsl #2 23 %0 = mul i32 %v, 5 24 ret i32 %0 25 } 26 27 define i32 @t3(i32 %v) nounwind readnone { 28 entry: 29 ; CHECK: t3: 30 ; CHECK: add r0, r0, r0, lsl #1 31 %0 = mul i32 %v, 3 32 ret i32 %0 33 } 34 35 define i32 @t12288(i32 %v) nounwind readnone { 36 entry: 37 ; CHECK: t12288: 38 ; CHECK: add r0, r0, r0, lsl #1 39 ; CHECK: lsl{{.*}}#12 40 %0 = mul i32 %v, 12288 41 ret i32 %0 42 } 43 44 define i32 @tn9(i32 %v) nounwind readnone { 45 entry: 46 ; CHECK: tn9: 47 ; CHECK: add r0, r0, r0, lsl #3 48 ; CHECK: rsb r0, r0, #0 49 %0 = mul i32 %v, -9 50 ret i32 %0 51 } 52 53 define i32 @tn7(i32 %v) nounwind readnone { 54 entry: 55 ; CHECK: tn7: 56 ; CHECK: sub r0, r0, r0, lsl #3 57 %0 = mul i32 %v, -7 58 ret i32 %0 59 } 60 61 define i32 @tn5(i32 %v) nounwind readnone { 62 entry: 63 ; CHECK: tn5: 64 ; CHECK: add r0, r0, r0, lsl #2 65 ; CHECK: rsb r0, r0, #0 66 %0 = mul i32 %v, -5 67 ret i32 %0 68 } 69 70 define i32 @tn3(i32 %v) nounwind readnone { 71 entry: 72 ; CHECK: tn3: 73 ; CHECK: sub r0, r0, r0, lsl #2 74 %0 = mul i32 %v, -3 75 ret i32 %0 76 } 77 78 define i32 @tn12288(i32 %v) nounwind readnone { 79 entry: 80 ; CHECK: tn12288: 81 ; CHECK: sub r0, r0, r0, lsl #2 82 ; CHECK: lsl{{.*}}#12 83 %0 = mul i32 %v, -12288 84 ret i32 %0 85 } 86
