1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s 2 ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s 3 4 define <8 x i8> @vld1i8(i8* %A) nounwind { 5 ;CHECK: vld1i8: 6 ;Check the alignment value. Max for this instruction is 64 bits: 7 ;CHECK: vld1.8 {d16}, [r0:64] 8 %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16) 9 ret <8 x i8> %tmp1 10 } 11 12 define <4 x i16> @vld1i16(i16* %A) nounwind { 13 ;CHECK: vld1i16: 14 ;CHECK: vld1.16 15 %tmp0 = bitcast i16* %A to i8* 16 %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1) 17 ret <4 x i16> %tmp1 18 } 19 20 ;Check for a post-increment updating load. 21 define <4 x i16> @vld1i16_update(i16** %ptr) nounwind { 22 ;CHECK: vld1i16_update: 23 ;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]! 24 %A = load i16** %ptr 25 %tmp0 = bitcast i16* %A to i8* 26 %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1) 27 %tmp2 = getelementptr i16* %A, i32 4 28 store i16* %tmp2, i16** %ptr 29 ret <4 x i16> %tmp1 30 } 31 32 define <2 x i32> @vld1i32(i32* %A) nounwind { 33 ;CHECK: vld1i32: 34 ;CHECK: vld1.32 35 %tmp0 = bitcast i32* %A to i8* 36 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1) 37 ret <2 x i32> %tmp1 38 } 39 40 ;Check for a post-increment updating load with register increment. 41 define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind { 42 ;CHECK: vld1i32_update: 43 ;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}} 44 %A = load i32** %ptr 45 %tmp0 = bitcast i32* %A to i8* 46 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1) 47 %tmp2 = getelementptr i32* %A, i32 %inc 48 store i32* %tmp2, i32** %ptr 49 ret <2 x i32> %tmp1 50 } 51 52 define <2 x float> @vld1f(float* %A) nounwind { 53 ;CHECK: vld1f: 54 ;CHECK: vld1.32 55 %tmp0 = bitcast float* %A to i8* 56 %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0, i32 1) 57 ret <2 x float> %tmp1 58 } 59 60 define <1 x i64> @vld1i64(i64* %A) nounwind { 61 ;CHECK: vld1i64: 62 ;CHECK: vld1.64 63 %tmp0 = bitcast i64* %A to i8* 64 %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0, i32 1) 65 ret <1 x i64> %tmp1 66 } 67 68 define <16 x i8> @vld1Qi8(i8* %A) nounwind { 69 ;CHECK: vld1Qi8: 70 ;Check the alignment value. Max for this instruction is 128 bits: 71 ;CHECK: vld1.8 {d16, d17}, [r0:64] 72 %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8) 73 ret <16 x i8> %tmp1 74 } 75 76 ;Check for a post-increment updating load. 77 define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind { 78 ;CHECK: vld1Qi8_update: 79 ;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]! 80 %A = load i8** %ptr 81 %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8) 82 %tmp2 = getelementptr i8* %A, i32 16 83 store i8* %tmp2, i8** %ptr 84 ret <16 x i8> %tmp1 85 } 86 87 define <8 x i16> @vld1Qi16(i16* %A) nounwind { 88 ;CHECK: vld1Qi16: 89 ;Check the alignment value. Max for this instruction is 128 bits: 90 ;CHECK: vld1.16 {d16, d17}, [r0:128] 91 %tmp0 = bitcast i16* %A to i8* 92 %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0, i32 32) 93 ret <8 x i16> %tmp1 94 } 95 96 define <4 x i32> @vld1Qi32(i32* %A) nounwind { 97 ;CHECK: vld1Qi32: 98 ;CHECK: vld1.32 99 %tmp0 = bitcast i32* %A to i8* 100 %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %tmp0, i32 1) 101 ret <4 x i32> %tmp1 102 } 103 104 define <4 x float> @vld1Qf(float* %A) nounwind { 105 ;CHECK: vld1Qf: 106 ;CHECK: vld1.32 107 %tmp0 = bitcast float* %A to i8* 108 %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0, i32 1) 109 ret <4 x float> %tmp1 110 } 111 112 define <2 x i64> @vld1Qi64(i64* %A) nounwind { 113 ;CHECK: vld1Qi64: 114 ;CHECK: vld1.64 115 %tmp0 = bitcast i64* %A to i8* 116 %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0, i32 1) 117 ret <2 x i64> %tmp1 118 } 119 120 declare <8 x i8> @llvm.arm.neon.vld1.v8i8(i8*, i32) nounwind readonly 121 declare <4 x i16> @llvm.arm.neon.vld1.v4i16(i8*, i32) nounwind readonly 122 declare <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) nounwind readonly 123 declare <2 x float> @llvm.arm.neon.vld1.v2f32(i8*, i32) nounwind readonly 124 declare <1 x i64> @llvm.arm.neon.vld1.v1i64(i8*, i32) nounwind readonly 125 126 declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8*, i32) nounwind readonly 127 declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*, i32) nounwind readonly 128 declare <4 x i32> @llvm.arm.neon.vld1.v4i32(i8*, i32) nounwind readonly 129 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly 130 declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly 131 132 ; Radar 8355607 133 ; Do not crash if the vld1 result is not used. 134 define void @unused_vld1_result() { 135 entry: 136 %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) 137 call void @llvm.trap() 138 unreachable 139 } 140 141 declare void @llvm.trap() nounwind 142
