1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s 2 3 define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { 4 ;CHECK: vpmins8: 5 ;CHECK: vpmin.s8 6 %tmp1 = load <8 x i8>* %A 7 %tmp2 = load <8 x i8>* %B 8 %tmp3 = call <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) 9 ret <8 x i8> %tmp3 10 } 11 12 define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind { 13 ;CHECK: vpmins16: 14 ;CHECK: vpmin.s16 15 %tmp1 = load <4 x i16>* %A 16 %tmp2 = load <4 x i16>* %B 17 %tmp3 = call <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) 18 ret <4 x i16> %tmp3 19 } 20 21 define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind { 22 ;CHECK: vpmins32: 23 ;CHECK: vpmin.s32 24 %tmp1 = load <2 x i32>* %A 25 %tmp2 = load <2 x i32>* %B 26 %tmp3 = call <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) 27 ret <2 x i32> %tmp3 28 } 29 30 define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { 31 ;CHECK: vpminu8: 32 ;CHECK: vpmin.u8 33 %tmp1 = load <8 x i8>* %A 34 %tmp2 = load <8 x i8>* %B 35 %tmp3 = call <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) 36 ret <8 x i8> %tmp3 37 } 38 39 define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { 40 ;CHECK: vpminu16: 41 ;CHECK: vpmin.u16 42 %tmp1 = load <4 x i16>* %A 43 %tmp2 = load <4 x i16>* %B 44 %tmp3 = call <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) 45 ret <4 x i16> %tmp3 46 } 47 48 define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { 49 ;CHECK: vpminu32: 50 ;CHECK: vpmin.u32 51 %tmp1 = load <2 x i32>* %A 52 %tmp2 = load <2 x i32>* %B 53 %tmp3 = call <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) 54 ret <2 x i32> %tmp3 55 } 56 57 define <2 x float> @vpminf32(<2 x float>* %A, <2 x float>* %B) nounwind { 58 ;CHECK: vpminf32: 59 ;CHECK: vpmin.f32 60 %tmp1 = load <2 x float>* %A 61 %tmp2 = load <2 x float>* %B 62 %tmp3 = call <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) 63 ret <2 x float> %tmp3 64 } 65 66 declare <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8>, <8 x i8>) nounwind readnone 67 declare <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnone 68 declare <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone 69 70 declare <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone 71 declare <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone 72 declare <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone 73 74 declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwind readnone 75 76 define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { 77 ;CHECK: vpmaxs8: 78 ;CHECK: vpmax.s8 79 %tmp1 = load <8 x i8>* %A 80 %tmp2 = load <8 x i8>* %B 81 %tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) 82 ret <8 x i8> %tmp3 83 } 84 85 define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { 86 ;CHECK: vpmaxs16: 87 ;CHECK: vpmax.s16 88 %tmp1 = load <4 x i16>* %A 89 %tmp2 = load <4 x i16>* %B 90 %tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) 91 ret <4 x i16> %tmp3 92 } 93 94 define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { 95 ;CHECK: vpmaxs32: 96 ;CHECK: vpmax.s32 97 %tmp1 = load <2 x i32>* %A 98 %tmp2 = load <2 x i32>* %B 99 %tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) 100 ret <2 x i32> %tmp3 101 } 102 103 define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { 104 ;CHECK: vpmaxu8: 105 ;CHECK: vpmax.u8 106 %tmp1 = load <8 x i8>* %A 107 %tmp2 = load <8 x i8>* %B 108 %tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) 109 ret <8 x i8> %tmp3 110 } 111 112 define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { 113 ;CHECK: vpmaxu16: 114 ;CHECK: vpmax.u16 115 %tmp1 = load <4 x i16>* %A 116 %tmp2 = load <4 x i16>* %B 117 %tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) 118 ret <4 x i16> %tmp3 119 } 120 121 define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { 122 ;CHECK: vpmaxu32: 123 ;CHECK: vpmax.u32 124 %tmp1 = load <2 x i32>* %A 125 %tmp2 = load <2 x i32>* %B 126 %tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) 127 ret <2 x i32> %tmp3 128 } 129 130 define <2 x float> @vpmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind { 131 ;CHECK: vpmaxf32: 132 ;CHECK: vpmax.f32 133 %tmp1 = load <2 x float>* %A 134 %tmp2 = load <2 x float>* %B 135 %tmp3 = call <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) 136 ret <2 x float> %tmp3 137 } 138 139 declare <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone 140 declare <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone 141 declare <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone 142 143 declare <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone 144 declare <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone 145 declare <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone 146 147 declare <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float>, <2 x float>) nounwind readnone 148
