1 ;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s 2 3 ;CHECK: S_MOV_B32 4 ;CHECK-NEXT: V_INTERP_MOV_F32 5 6 define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" { 7 main_body: 8 %4 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3) 9 %5 = call i32 @llvm.SI.packf16(float %4, float %4) 10 %6 = bitcast i32 %5 to float 11 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %6, float %6, float %6, float %6) 12 ret void 13 } 14 15 declare void @llvm.AMDGPU.shader.type(i32) 16 17 declare float @llvm.SI.fs.constant(i32, i32, i32) readonly 18 19 declare i32 @llvm.SI.packf16(float, float) readnone 20 21 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) 22
