1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the interface of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef X86RECOGNIZABLEINSTR_H 18 #define X86RECOGNIZABLEINSTR_H 19 20 #include "CodeGenTarget.h" 21 #include "X86DisassemblerTables.h" 22 #include "llvm/ADT/SmallVector.h" 23 #include "llvm/Support/DataTypes.h" 24 #include "llvm/TableGen/Record.h" 25 26 namespace llvm { 27 28 namespace X86Disassembler { 29 30 /// RecognizableInstr - Encapsulates all information required to decode a single 31 /// instruction, as extracted from the LLVM instruction tables. Has methods 32 /// to interpret the information available in the LLVM tables, and to emit the 33 /// instruction into DisassemblerTables. 34 class RecognizableInstr { 35 private: 36 /// The opcode of the instruction, as used in an MCInst 37 InstrUID UID; 38 /// The record from the .td files corresponding to this instruction 39 const Record* Rec; 40 /// The prefix field from the record 41 uint8_t Prefix; 42 /// The opcode field from the record; this is the opcode used in the Intel 43 /// encoding and therefore distinct from the UID 44 uint8_t Opcode; 45 /// The form field from the record 46 uint8_t Form; 47 /// The segment override field from the record 48 uint8_t SegOvr; 49 /// The hasOpSizePrefix field from the record 50 bool HasOpSizePrefix; 51 /// The hasAdSizePrefix field from the record 52 bool HasAdSizePrefix; 53 /// The hasREX_WPrefix field from the record 54 bool HasREX_WPrefix; 55 /// The hasVEXPrefix field from the record 56 bool HasVEXPrefix; 57 /// The hasVEX_4VPrefix field from the record 58 bool HasVEX_4VPrefix; 59 /// The hasVEX_4VOp3Prefix field from the record 60 bool HasVEX_4VOp3Prefix; 61 /// The hasVEX_WPrefix field from the record 62 bool HasVEX_WPrefix; 63 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set 64 bool HasVEX_LPrefix; 65 /// The hasMemOp4Prefix field from the record 66 bool HasMemOp4Prefix; 67 /// The ignoreVEX_L field from the record 68 bool IgnoresVEX_L; 69 /// The hasLockPrefix field from the record 70 bool HasLockPrefix; 71 /// The isCodeGenOnly filed from the record 72 bool IsCodeGenOnly; 73 // Whether the instruction has the predicate "In64BitMode" 74 bool Is64Bit; 75 // Whether the instruction has the predicate "In32BitMode" 76 bool Is32Bit; 77 78 /// The instruction name as listed in the tables 79 std::string Name; 80 /// The AT&T AsmString for the instruction 81 std::string AsmString; 82 83 /// Indicates whether the instruction is SSE 84 bool IsSSE; 85 /// Indicates whether the instruction has FR operands - MOVs with FR operands 86 /// are typically ignored 87 bool HasFROperands; 88 /// Indicates whether the instruction should be emitted into the decode 89 /// tables; regardless, it will be emitted into the instruction info table 90 bool ShouldBeEmitted; 91 92 /// The operands of the instruction, as listed in the CodeGenInstruction. 93 /// They are not one-to-one with operands listed in the MCInst; for example, 94 /// memory operands expand to 5 operands in the MCInst 95 const std::vector<CGIOperandList::OperandInfo>* Operands; 96 97 /// The description of the instruction that is emitted into the instruction 98 /// info table 99 InstructionSpecifier* Spec; 100 101 /// insnContext - Returns the primary context in which the instruction is 102 /// valid. 103 /// 104 /// @return - The context in which the instruction is valid. 105 InstructionContext insnContext() const; 106 107 enum filter_ret { 108 FILTER_STRONG, // instruction has no place in the instruction tables 109 FILTER_WEAK, // instruction may conflict, and should be eliminated if 110 // it does 111 FILTER_NORMAL // instruction should have high priority and generate an 112 // error if it conflcits with any other FILTER_NORMAL 113 // instruction 114 }; 115 116 /// filter - Determines whether the instruction should be decodable. Some 117 /// instructions are pure intrinsics and use unencodable operands; many 118 /// synthetic instructions are duplicates of other instructions; other 119 /// instructions only differ in the logical way in which they are used, and 120 /// have the same decoding. Because these would cause decode conflicts, 121 /// they must be filtered out. 122 /// 123 /// @return - The degree of filtering to be applied (see filter_ret). 124 filter_ret filter() const; 125 126 /// hasFROperands - Returns true if any operand is a FR operand. 127 bool hasFROperands() const; 128 129 /// typeFromString - Translates an operand type from the string provided in 130 /// the LLVM tables to an OperandType for use in the operand specifier. 131 /// 132 /// @param s - The string, as extracted by calling Rec->getName() 133 /// on a CodeGenInstruction::OperandInfo. 134 /// @param isSSE - Indicates whether the instruction is an SSE 135 /// instruction. For SSE instructions, immediates are 136 /// fixed-size rather than being affected by the 137 /// mandatory OpSize prefix. 138 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W 139 /// prefix. If it does, 32-bit register operands stay 140 /// 32-bit regardless of the operand size. 141 /// @param hasOpSizePrefix Indicates whether the instruction has an OpSize 142 /// prefix. If it does not, then 16-bit register 143 /// operands stay 16-bit. 144 /// @return - The operand's type. 145 static OperandType typeFromString(const std::string& s, 146 bool isSSE, 147 bool hasREX_WPrefix, 148 bool hasOpSizePrefix); 149 150 /// immediateEncodingFromString - Translates an immediate encoding from the 151 /// string provided in the LLVM tables to an OperandEncoding for use in 152 /// the operand specifier. 153 /// 154 /// @param s - See typeFromString(). 155 /// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize 156 /// prefix. If it does not, then 16-bit immediate 157 /// operands stay 16-bit. 158 /// @return - The operand's encoding. 159 static OperandEncoding immediateEncodingFromString(const std::string &s, 160 bool hasOpSizePrefix); 161 162 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 163 /// handles operands that are in the REG field of the ModR/M byte. 164 static OperandEncoding rmRegisterEncodingFromString(const std::string &s, 165 bool hasOpSizePrefix); 166 167 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 168 /// handles operands that are in the REG field of the ModR/M byte. 169 static OperandEncoding roRegisterEncodingFromString(const std::string &s, 170 bool hasOpSizePrefix); 171 static OperandEncoding memoryEncodingFromString(const std::string &s, 172 bool hasOpSizePrefix); 173 static OperandEncoding relocationEncodingFromString(const std::string &s, 174 bool hasOpSizePrefix); 175 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s, 176 bool hasOpSizePrefix); 177 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s, 178 bool HasOpSizePrefix); 179 180 /// handleOperand - Converts a single operand from the LLVM table format to 181 /// the emitted table format, handling any duplicate operands it encounters 182 /// and then one non-duplicate. 183 /// 184 /// @param optional - Determines whether to assert that the 185 /// operand exists. 186 /// @param operandIndex - The index into the generated operand table. 187 /// Incremented by this function one or more 188 /// times to reflect possible duplicate 189 /// operands). 190 /// @param physicalOperandIndex - The index of the current operand into the 191 /// set of non-duplicate ('physical') operands. 192 /// Incremented by this function once. 193 /// @param numPhysicalOperands - The number of non-duplicate operands in the 194 /// instructions. 195 /// @param operandMapping - The operand mapping, which has an entry for 196 /// each operand that indicates whether it is a 197 /// duplicate, and of what. 198 void handleOperand(bool optional, 199 unsigned &operandIndex, 200 unsigned &physicalOperandIndex, 201 unsigned &numPhysicalOperands, 202 const unsigned *operandMapping, 203 OperandEncoding (*encodingFromString) 204 (const std::string&, 205 bool hasOpSizePrefix)); 206 207 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter() 208 /// filters out many instructions, at various points in decoding we 209 /// determine that the instruction should not actually be decodable. In 210 /// particular, MMX MOV instructions aren't emitted, but they're only 211 /// identified during operand parsing. 212 /// 213 /// @return - true if at this point we believe the instruction should be 214 /// emitted; false if not. This will return false if filter() returns false 215 /// once emitInstructionSpecifier() has been called. 216 bool shouldBeEmitted() const { 217 return ShouldBeEmitted; 218 } 219 220 /// emitInstructionSpecifier - Loads the instruction specifier for the current 221 /// instruction into a DisassemblerTables. 222 /// 223 /// \param tables The DisassemblerTables to populate with the specifier for 224 /// the current instruction. 225 void emitInstructionSpecifier(DisassemblerTables &tables); 226 227 /// emitDecodePath - Populates the proper fields in the decode tables 228 /// corresponding to the decode paths for this instruction. 229 /// 230 /// \param tables The DisassemblerTables to populate with the decode 231 /// decode information for the current instruction. 232 void emitDecodePath(DisassemblerTables &tables) const; 233 234 /// Constructor - Initializes a RecognizableInstr with the appropriate fields 235 /// from a CodeGenInstruction. 236 /// 237 /// \param tables The DisassemblerTables that the specifier will be added to. 238 /// \param insn The CodeGenInstruction to extract information from. 239 /// \param uid The unique ID of the current instruction. 240 RecognizableInstr(DisassemblerTables &tables, 241 const CodeGenInstruction &insn, 242 InstrUID uid); 243 public: 244 /// processInstr - Accepts a CodeGenInstruction and loads decode information 245 /// for it into a DisassemblerTables if appropriate. 246 /// 247 /// \param tables The DiassemblerTables to be populated with decode 248 /// information. 249 /// \param insn The CodeGenInstruction to be used as a source for this 250 /// information. 251 /// \param uid The unique ID of the instruction. 252 static void processInstr(DisassemblerTables &tables, 253 const CodeGenInstruction &insn, 254 InstrUID uid); 255 }; 256 257 } // namespace X86Disassembler 258 259 } // namespace llvm 260 261 #endif 262
