1 @/* 2 @ ** Copyright 2003-2010, VisualOn, Inc. 3 @ ** 4 @ ** Licensed under the Apache License, Version 2.0 (the "License"); 5 @ ** you may not use this file except in compliance with the License. 6 @ ** You may obtain a copy of the License at 7 @ ** 8 @ ** http://www.apache.org/licenses/LICENSE-2.0 9 @ ** 10 @ ** Unless required by applicable law or agreed to in writing, software 11 @ ** distributed under the License is distributed on an "AS IS" BASIS, 12 @ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 @ ** See the License for the specific language governing permissions and 14 @ ** limitations under the License. 15 @ */ 16 17 @**********************************************************************/ 18 @void Filt_6k_7k( 19 @ Word16 signal[], /* input: signal */ 20 @ Word16 lg, /* input: length of input */ 21 @ Word16 mem[] /* in/out: memory (size=30) */ 22 @) 23 @****************************************************************** 24 @ r0 --- signal[] 25 @ r1 --- lg 26 @ r2 --- mem[] 27 28 .section .text 29 .global Filt_6k_7k_asm 30 .extern voAWB_Copy 31 .extern fir_6k_7k 32 33 Filt_6k_7k_asm: 34 35 STMFD r13!, {r4 - r12, r14} 36 SUB r13, r13, #240 @ x[L_SUBFR16k + (L_FIR - 1)] 37 MOV r8, r0 @ copy signal[] address 38 MOV r4, r1 @ copy lg address 39 MOV r5, r2 @ copy mem[] address 40 41 MOV r1, r13 42 MOV r0, r2 43 MOV r2, #30 @ L_FIR - 1 44 BL voAWB_Copy @ memcpy(x, mem, (L_FIR - 1)<<1) 45 46 ADR r3, Lable1 @ get fir_7k address 47 LDR r10, [r3] 48 ADD r10, r3 49 50 MOV r14, #0 51 MOV r3, r8 @ change myMemCopy to Copy, due to Copy will change r3 content 52 ADD r6, r13, #60 @ get x[L_FIR - 1] address 53 MOV r7, r3 @ get signal[i] 54 LOOP1: 55 LDRSH r8, [r7], #2 56 LDRSH r9, [r7], #2 57 MOV r8, r8, ASR #2 58 MOV r9, r9, ASR #2 59 LDRSH r11, [r7], #2 60 LDRSH r12, [r7], #2 61 MOV r11, r11, ASR #2 62 MOV r12, r12, ASR #2 63 STRH r8, [r6], #2 64 STRH r9, [r6], #2 65 STRH r11, [r6], #2 66 STRH r12, [r6], #2 67 LDRSH r8, [r7], #2 68 LDRSH r9, [r7], #2 69 MOV r8, r8, ASR #2 70 MOV r9, r9, ASR #2 71 LDRSH r11, [r7], #2 72 LDRSH r12, [r7], #2 73 MOV r11, r11, ASR #2 74 MOV r12, r12, ASR #2 75 STRH r8, [r6], #2 76 STRH r9, [r6], #2 77 STRH r11, [r6], #2 78 STRH r12, [r6], #2 79 ADD r14, r14, #8 80 CMP r14, #80 81 BLT LOOP1 82 83 84 STR r5, [sp, #-4] @ PUSH r5 to stack 85 86 @ not use registers: r4, r10, r12, r14, r5 87 MOV r4, r13 88 MOV r5, #0 @ i = 0 89 LOOP2: 90 LDR r0, [r10] 91 92 LDRSH r1, [r4] @ load x[i] 93 LDRSH r2, [r4, #60] @ load x[i + 30] 94 LDRSH r6, [r4, #2] @ load x[i + 1] 95 LDRSH r7, [r4, #58] @ load x[i + 29] 96 ADD r1, r1, r2 @ x[i] + x[i + 30] 97 ADD r6, r6, r7 @ x[i + 1] + x[i + 29] 98 LDRSH r8, [r4, #4] @ load x[i + 2] 99 LDRSH r9, [r4, #56] @ load x[i + 28] 100 101 SMULBB r14, r1, r0 @ (x[i] + x[i + 30]) * fir_7k[0] 102 ADD r8, r8, r9 @ x[i + 2] + x[i + 28] 103 SMLABT r14, r6, r0, r14 @ (x[i + 1] + x[i + 29]) * fir_7k[1] 104 105 LDR r0, [r10, #4] 106 LDRSH r1, [r4, #6] @ load x[i+3] 107 LDRSH r2, [r4, #54] @ load x[i+27] 108 LDRSH r6, [r4, #8] @ load x[i+4] 109 LDRSH r7, [r4, #52] @ load x[i+26] 110 ADD r1, r1, r2 @ x[i+3] + x[i+27] 111 ADD r6, r6, r7 @ x[i+4] + x[i+26] 112 SMLABB r14, r8, r0, r14 @ (x[i + 2] + x[i + 28]) * fir_7k[2] 113 LDRSH r8, [r4, #10] @ load x[i+5] 114 LDRSH r9, [r4, #50] @ load x[i+25] 115 SMLABT r14, r1, r0, r14 @ (x[i+3] + x[i+27]) * fir_7k[3] 116 ADD r8, r8, r9 @ x[i+5] + x[i+25] 117 118 LDR r0, [r10, #8] 119 LDRSH r1, [r4, #12] @ x[i+6] 120 LDRSH r2, [r4, #48] @ x[i+24] 121 SMLABB r14, r6, r0, r14 @ (x[i+4] + x[i+26]) * fir_7k[4] 122 LDRSH r6, [r4, #14] @ x[i+7] 123 LDRSH r7, [r4, #46] @ x[i+23] 124 SMLABT r14, r8, r0, r14 @ (x[i+5] + x[i+25]) * fir_7k[5] 125 LDR r0, [r10, #12] 126 ADD r1, r1, r2 @ (x[i+6] + x[i+24]) 127 ADD r6, r6, r7 @ (x[i+7] + x[i+23]) 128 SMLABB r14, r1, r0, r14 @ (x[i+6] + x[i+24]) * fir_7k[6] 129 LDRSH r8, [r4, #16] @ x[i+8] 130 LDRSH r9, [r4, #44] @ x[i+22] 131 SMLABT r14, r6, r0, r14 @ (x[i+7] + x[i+23]) * fir_7k[7] 132 LDR r0, [r10, #16] 133 LDRSH r1, [r4, #18] @ x[i+9] 134 LDRSH r2, [r4, #42] @ x[i+21] 135 LDRSH r6, [r4, #20] @ x[i+10] 136 LDRSH r7, [r4, #40] @ x[i+20] 137 ADD r8, r8, r9 @ (x[i+8] + x[i+22]) 138 ADD r1, r1, r2 @ (x[i+9] + x[i+21]) 139 ADD r6, r6, r7 @ (x[i+10] + x[i+20]) 140 SMLABB r14, r8, r0, r14 @ (x[i+8] + x[i+22]) * fir_7k[8] 141 LDRSH r8, [r4, #22] @ x[i+11] 142 LDRSH r9, [r4, #38] @ x[i+19] 143 SMLABT r14, r1, r0, r14 @ (x[i+9] + x[i+21]) * fir_7k[9] 144 LDR r0, [r10, #20] 145 LDRSH r1, [r4, #24] @ x[i+12] 146 LDRSH r2, [r4, #36] @ x[i+18] 147 SMLABB r14, r6, r0, r14 @ (x[i+10] + x[i+20]) * fir_7k[10] 148 LDRSH r6, [r4, #26] @ x[i+13] 149 ADD r8, r8, r9 @ (x[i+11] + x[i+19]) 150 LDRSH r7, [r4, #34] @ x[i+17] 151 SMLABT r14, r8, r0, r14 @ (x[i+11] + x[i+19]) * fir_7k[11] 152 LDR r0, [r10, #24] 153 ADD r1, r1, r2 @ x[i+12] + x[i+18] 154 LDRSH r8, [r4, #28] @ x[i+14] 155 SMLABB r14, r1, r0, r14 @ (x[i+12] + x[i+18]) * fir_7k[12] 156 ADD r6, r6, r7 @ (x[i+13] + x[i+17]) 157 LDRSH r9, [r4, #32] @ x[i+16] 158 SMLABT r14, r6, r0, r14 @ (x[i+13] + x[i+17]) * fir_7k[13] 159 LDR r0, [r10, #28] 160 ADD r8, r8, r9 @ (x[i+14] + x[i+16]) 161 LDRSH r1, [r4, #30] @ x[i+15] 162 SMLABB r14, r8, r0, r14 @ (x[i+14] + x[i+16]) * fir_7k[14] 163 SMLABT r14, r1, r0, r14 @ x[i+15] * fir_7k[15] 164 165 ADD r5, r5, #1 166 ADD r14, r14, #0x4000 167 ADD r4, r4, #2 168 MOV r1, r14, ASR #15 169 CMP r5, #80 170 STRH r1, [r3], #2 @signal[i] = (L_tmp + 0x4000) >> 15 171 BLT LOOP2 172 173 LDR r1, [sp, #-4] @mem address 174 ADD r0, r13, #160 @x + lg 175 MOV r2, #30 176 BL voAWB_Copy 177 178 Filt_6k_7k_end: 179 ADD r13, r13, #240 180 LDMFD r13!, {r4 - r12, r15} 181 182 Lable1: 183 .word fir_6k_7k-Lable1 184 @ENDFUNC 185 .END 186 187 188
