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itable.ol `B`B__text__TEXT__cstring__TEXT__data__DATA&(C	0d`dLP32fdspdsp2mdmxmips16mips16emips32mips32r2mips3dmips64mips64r2mipsImipsIImipsIIImipsIVmipsVr3900sb1smartmipsvr4100vr4120vr5000vr5400vr55006.0x0,5.*,5.*,5.*,5.OP,6.0x5SPECIALRSVDmips.igen6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x20mips32,mips32r2,mips64,mips64r2,mipsI,mipsII,mipsIII,mipsIV,mipsV,r3900,vr4100,vr5000ADD6.0x8,5.RS,5.RT,16.IMMEDIATENORMALADDI6.0x9,5.RS,5.RT,16.IMMEDIATEADDIU6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x21ADDU6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x24AND6.0xc,5.RS,5.RT,16.IMMEDIATEANDI6.0x4,5.RS,5.RT,16.OFFSETBEQ6.0x14,5.RS,5.RT,16.OFFSETmips32,mips32r2,mips64,mips64r2,mipsII,mipsIII,mipsIV,mipsV,r3900,vr4100,vr5000BEQL6.0x1,5.RS,5.0x1,16.OFFSETREGIMMBGEZ6.0x1,5.RS,5.0x11,16.OFFSETBGEZAL6.0x1,5.RS,5.0x13,16.OFFSETBGEZALL6.0x1,5.RS,5.0x3,16.OFFSETBGEZL6.0x7,5.RS,5.0x0,16.OFFSETBGTZ6.0x17,5.RS,5.0x0,16.OFFSETBGTZL6.0x6,5.RS,5.0x0,16.OFFSETBLEZ6.0x16,5.RS,5.0x0,16.OFFSETBLEZL6.0x1,5.RS,5.0x0,16.OFFSETBLTZ6.0x1,5.RS,5.0x10,16.OFFSETBLTZAL6.0x1,5.RS,5.0x12,16.OFFSETBLTZALL6.0x1,5.RS,5.0x2,16.OFFSETBLTZL6.0x5,5.RS,5.RT,16.OFFSETBNE6.0x15,5.RS,5.RT,16.OFFSETBNEL6.0x0,20.CODE,6.0xdBREAK6.0x0,5.RS,5.RT,10.0x0,6.0x1aDIV6.0x0,5.RS,5.RT,10.0x0,6.0x1bDIVU6.0x2,26.INSTR_INDEXJ6.0x3,26.INSTR_INDEXJAL6.0x0,5.RS,5.0x0,5.RD,5.0x0,6.0x9JALR6.0x0,5.RS,10.0x0,5.0x0,6.0x8JR6.0x20,5.BASE,5.RT,16.OFFSETLB6.0x24,5.BASE,5.RT,16.OFFSETLBU6.0x21,5.BASE,5.RT,16.OFFSETLH6.0x25,5.BASE,5.RT,16.OFFSETLHU6.0x30,5.BASE,5.RT,16.OFFSETmips32,mips32r2,mips64,mips64r2,mipsII,mipsIII,mipsIV,mipsV,vr4100,vr5000LL6.0xf,5.0x0,5.RT,16.IMMEDIATELUI6.0x23,5.BASE,5.RT,16.OFFSETLW4.0xc,2.ZZ,5.BASE,5.RT,16.OFFSETLWCz6.0x22,5.BASE,5.RT,16.OFFSETLWL6.0x26,5.BASE,5.RT,16.OFFSETLWR6.0x0,10.0x0,5.RD,5.0x0,6.0x10mips32,mips64,mipsI,mipsII,mipsIII,mipsIV,mipsV,r3900,vr4100,vr5000MFHI6.0x0,10.0x0,5.RD,5.0x0,6.0x12MFLO6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0xbmips32,mips32r2,mips64,mips64r2,mipsIV,mipsV,vr5000MOVN6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0xaMOVZ6.0x0,5.RS,15.0x0,6.0x11MTHI6.0x0,5.RS,15.0x0,6.0x13MTLO6.0x0,5.RS,5.RT,10.0x0,6.0x18mips32,mips64,mipsI,mipsII,mipsIII,mipsIV,mipsV,vr4100MULT6.0x0,5.RS,5.RT,10.0x0,6.0x19MULTU6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x27NOR6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x25OR6.0xd,5.RS,5.RT,16.IMMEDIATEORI6.0x33,5.BASE,5.HINT,16.OFFSETPREF6.0x28,5.BASE,5.RT,16.OFFSETSB6.0x38,5.BASE,5.RT,16.OFFSETSC6.0x29,5.BASE,5.RT,16.OFFSETSH6.0x0,5.0x0,5.RT,5.RD,5.SHIFT,6.0x0mipsI,mipsII,mipsIII,mipsIV,mipsV,r3900,vr4100,vr5000SLLa6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x4SLLV6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x2aSLT6.0xa,5.RS,5.RT,16.IMMEDIATESLTI6.0xb,5.RS,5.RT,16.IMMEDIATESLTIU6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x2bSLTU6.0x0,5.0x0,5.RT,5.RD,5.SHIFT,6.0x3SRA6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x7SRAV6.0x0,5.0x0,5.RT,5.RD,5.SHIFT,6.0x2SRL6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x6SRLV6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x22SUB6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x23SUBU6.0x2b,5.BASE,5.RT,16.OFFSETSW4.0xe,2.ZZ,5.BASE,5.RT,16.OFFSETSWCz6.0x2a,5.BASE,5.RT,16.OFFSETSWL6.0x2e,5.BASE,5.RT,16.OFFSETSWR6.0x0,15.0x0,5.STYPE,6.0xfSYNC6.0x0,20.CODE,6.0xcSYSCALL6.0x0,5.RS,5.RT,10.CODE,6.0x34TEQ6.0x1,5.RS,5.0xc,16.IMMEDIATETEQI6.0x0,5.RS,5.RT,10.CODE,6.0x30TGE6.0x1,5.RS,5.0x8,16.IMMEDIATETGEI6.0x1,5.RS,5.0x9,16.IMMEDIATETGEIU6.0x0,5.RS,5.RT,10.CODE,6.0x31TGEU6.0x0,5.RS,5.RT,10.CODE,6.0x32TLT6.0x1,5.RS,5.0xa,16.IMMEDIATETLTI6.0x1,5.RS,5.0xb,16.IMMEDIATETLTIU6.0x0,5.RS,5.RT,10.CODE,6.0x33TLTU6.0x0,5.RS,5.RT,10.CODE,6.0x36TNE6.0x1,5.RS,5.0xe,16.IMMEDIATETNEI6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x26XOR6.0xe,5.RS,5.RT,16.IMMEDIATEXORI6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0x5COP132,fABS.fmt6.0x11,2.0x2,3.FMT,5.FT,5.FS,5.FD,6.0x0ADD.fmt6.0x11,5.0x8,3.CC,1.ND,1.TF,16.OFFSETCOP1Smips32,mips32r2,mips64,mips64r2,mipsIV,mipsV,r3900,vr5000BC1b6.0x11,2.0x2,3.FMT,5.FT,5.FS,3.CC,2.0x0,2.0x3,4.CONDmips32,mips32r2,mips64,mips64r2,mipsIV,mipsV,r3900,vr4100,vr5000C.cond.fmtb6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0xamips32r2,mips64,mips64r2,mipsIII,mipsIV,mipsV,r3900,vr4100,vr5000CEIL.L.fmt6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0xeCEIL.W6.0x11,5.0x2,5.RT,5.FS,11.0x0mipsIV,r3900,vr4100,vr5000CFC1b6.0x11,5.0x6,5.RT,5.FS,11.0x0CTC1b6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0x21CVT.D.fmt6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0x25CVT.L.fmt6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0x20CVT.S.fmt6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0x24CVT.W.fmt6.0x11,2.0x2,3.FMT,5.FT,5.FS,5.FD,6.0x3DIV.fmt6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0xbFLOOR.L.fmt6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0xfFLOOR.W.fmt6.0x35,5.BASE,5.FT,16.OFFSETmips64,mips64r2,mipsIII,mipsIV,mipsV,r3900,vr4100,vr5000LDC1b6.0x31,5.BASE,5.FT,16.OFFSETLWC16.0x13,5.BASE,5.INDEX,5.0x0,5.FD,6.0x0COP1Xmips32r2,mips64,mips64r2,mipsIV,mipsV,vr5000LWXC16.0x13,5.FR,5.FT,5.FS,5.FD,3.0x4,3.FMTMADD.fmt6.0x11,5.0x0,5.RT,5.FS,11.0x0MFC1b6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0x6MOV.fmt6.0x0,5.RS,3.CC,1.0x0,1.TF,5.RD,5.0x0,6.0x1MOVtf6.0x11,2.0x2,3.FMT,3.CC,1.0x0,1.TF,5.FS,5.FD,6.0x11MOVtf.fmt6.0x11,2.0x2,3.FMT,5.RT,5.FS,5.FD,6.0x13MOVN.fmt6.0x11,2.0x2,3.FMT,5.RT,5.FS,5.FD,6.0x12MOVZ.fmt6.0x13,5.FR,5.FT,5.F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#1/20           1346989466  501   20    100644  243580    `
semantics.o __text__TEXT[v__cstring__TEXT\Ql__data__DATA__bss__DATA__pointers__IMPORT {`"PJJB{U8E;E}E;E|}NU)M}NU)ME;E|}NUU}NMMMMUE;E|}NMM}NUUEMEEUUE;E|&}NU)U$}NU)U}|E;E|}NMU}NMUE;E|}NMM}NUUEMEEUUUM!MEU8?+U?+E9)?+E?+U?+E9|!?+EN)M?+EN)M?+U?+E9|?+ENM?+ENMMMU?+U?+E9|?+ENM?+ENMEMEEUU9?+U?+E9|*?+EN)U(?+EN)U?+E?+U?+E9|#?+ENU!?+ENU?+U?+E9|?+ENM?+ENMEMEEUUUM!MEUSd[E;E}hEEEE</uE@EEEt
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EUEEE"=EE%tEu	EEE2Et
EUEEEEE!UE!3E	EE#E3EEuD$D$E$gZE t1EUEtUUMuED$(T$$EUD$T$ EUD$T$D$L$ED$t$E$$uD$D$E$YEE[^_UWVS[E	#D$D$E$WYD$D$E$XD$D$E$YI!EI!EE	EEt$(|$$L$ D$ED$ED$T$ED$ED$UT$E$?E	t9I!UD$AD$D$T$E$??EftE@EEE@uD$D$E$WED$D$E$zWED$~ED$E$arED$ED$D$~ED$E$/EEtHUD$D$ED$D$D$ED$T$E$->UD$ ED$ED$D$D$ED$ED$T$E$ EEEEEEE%t!Eu
EUEEEE=EE%tEu	EEE2Et
EUEEEEE!UE!3E	EE#E3EED$D$E$UEUL$D$ED$T$E$<E t1EUUMuED$(T$$EUD$T$ EUD$T$D$L$ED$t$E$E[^_UWVS\[E	#D$D$E$TD$D$E$_TD$D$E$T E EE	EEt$(|$$L$ D$ED$ED$T$ED$ED$UT$E$;E	t9 UD$
D$D$T$E$:EftE@EEE@D${ED$E$*nD$D$E$cSUD$D$ED$T$E$+:D$D$E$REuD$D$E$R|$UT$D$D$D${ED$E$xXE\[^_/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-bits.cstart >= stop%s:%d: assertion failed - %sstart <= stopsign_bit < 64/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-n-bits.hshift <= Nsign_bit < N/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-n-endian.hoffset + sizeof_word <= sizeof(unsigned_N)word < (sizeof (unsigned_N) / sizeof_word)(sizeof (unsigned_N) % sizeof_word) == 0/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-core.c(addr & (nr_bytes - 1)) == 0(addr + (nr_bytes - 1)) >= addr!abort || cpu != NULLreadwrite-><-sim-n-core.h:%d: %s-%d %s:0x%08lx %s 0x%08lx%08lx%08lx%08lx
%s-%d %s:0x%08lx %s 0x%08lx%08lx
%s-%d %s:0x%08lx %s 0x%08lx
%s-%d %s:0x%08lx %s 0x%04lx
%s-%d %s:0x%08lx %s 0x%02lx
/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-events.c%s:%d: , event time-from-event - time %ld, delta %ld - event %d, tag 0x%lx, time %ld, handler 0x%lx, data 0x%lx%s%s
current_time == sim_events_time (sd)sim_watch_valid - bad switchn > 0slip > 0events->nr_ticks_to_process != 0events_were_nextevent issued at %ld - tag 0x%lx - handler 0x%lx, data 0x%lx%s%s
events->time_from_event >= events->nr_ticks_to_processevents->queue != NULL,10/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-fpu.csrc->fraction >= IMPLICIT_1src->fraction < IMPLICIT_2(exp == EXPMAX) <= ((fraction & ~IMPLICIT_1) == 0)val.i == packedval == orgs->fraction >= IMPLICIT_1val == if->fraction < IMPLICIT_2f->fraction >= IMPLICIT_1(f->class == sim_fpu_class_number || f->class == sim_fpu_class_denorm) <= (f->fraction < IMPLICIT_2 && f->fraction >= IMPLICIT_1)f->fraction >= IMPLICIT_1 && f->fraction < IMPLICIT_2high < LSBIT64 (((NR_FRAC_GUARD + 1) * 2) - 64)high >= LSBIT64 ((NR_FRAC_GUARD * 2) - 64)high >= IMPLICIT_1 && high < IMPLICIT_2numerator >= denominatorl->sign == r->signy >= IMPLICIT_1 && y < IMPLICIT_4y >= IMPLICIT_1 && y < (IMPLICIT_2 << 1)q >= IMPLICIT_1 && q < IMPLICIT_2-+%s0.*QuietNaN*SignalNaN0.0INF1.*2^%+d%sD%sSNaN%sQNaN%sISI%sIDI%sZDZ%sIMZ%sCVI%sCMP%sSQRT%sX%sO%sU%s/%sRLOAD AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s
STORE AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s
Instruction CACHE operation %d to be coded
Data CACHE operation %d to be coded
PENDING_DRAIN - Mis-match on pending update pointers
Internal function must longjump
load instructionHILO: %s: %s at 0x%08lx too close to MF at 0x%08lx
MTHILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx
OPsdwlps?tfunequeqoltultoleulesfngleseqnglltngelengtsave: aregs=%d causes unpredictable results
hiuinvalid multiplication operand at 0x%08lx
rsvd %ld %ssyscall %#lxbreak %#lxtge r%ld, r%ldtgeu r%ld, r%ldtlt r%ld, r%ldtltu r%ld, r%ldteq r%ld, r%ldtne r%ld, r%ldsllv r%ld, r%ld, r%ldsrlv r%ld, r%ld, r%ldsrav r%ld, r%ld, r%ldmovz r%ld, r%ld, r%ldmovn r%ld, r%ld, r%ldadd r%ld, r%ld, r%ldaddu r%ld, r%ld, r%ldsub r%ld, r%ld, r%ldsubu r%ld, r%ld, r%ldand r%ld, r%ld, r%ldor r%ld, r%ld, r%ldxor r%ld, r%ld, r%ldnor r%ld, r%ld, r%ldslt r%ld, r%ld, r%ldsltu r%ld, r%ld, r%ldmult r%ld, r%ldmultu r%ld, r%lddiv r%ld, r%lddivu r%ld, r%ldmov%s r%ld, r%ld, %ldjalr r%ldjalr r%ld, r%ldjr r%ldmthi r%ldmtlo r%ldnopsll r%ld, r%ld, %ldsrl r%ld, r%ld, %ldsra r%ld, r%ld, %ldmfhi r%ldmflo r%ldsyncsync %ldbltz r%ld, %ldbgez r%ld, %ldbltzl r%ld, %ldbgezl r%ld, %ldtgei r%ld, %ldtgeiu r%ld, %ldtlti r%ld, %ldtltiu r%ld, %ldteqi r%ld, %ldtnei r%ld, %ldbltzal r%ld, %ldbgezal r%ld, %ldbltzall r%ld, %ldbgezall r%ld, %ldj %ldjal %ldbeq r%ld, r%ld, %ldbne r%ld, r%ld, %ldblez r%ld, %ldbgtz r%ld, %ldaddi r%ld, r%ld, %ldaddiu r%ld, r%ld, %ldslti r%ld, r%ld, %ldsltiu r%ld, r%ld, %ldandi r%ld, r%ld, %#lxori r%ld, r%ld, %#lxxori r%ld, r%ld, %#lxlui r%ld, %#lxcop%ld %ld%ld%ldmfc0 r%ld, r%ld # %ldmtc0 r%ld, r%ld # %ldbc0f %ldmips.igen:5679:0x%08lx:%s unimplemented
bc0t %ldmips.igen:5717:0x%08lx:%s unimplemented
bc0fl %ldmips.igen:5702:0x%08lx:%s unimplemented
bc0tl %ldmips.igen:5731:0x%08lx:%s unimplemented
tlbrmips.igen:5912:0x%08lx:%s unimplemented
tlbwimips.igen:5927:0x%08lx:%s unimplemented
tlbwrmips.igen:5942:0x%08lx:%s unimplemented
tlbpmips.igen:5897:0x%08lx:%s unimplemented
rfeeretWarning: ERET when SR[ERL] set not supportedmfc1 r%ld, f%ldcfc1 r%ld, f%ldmtc1 r%ld, f%ldctc1 r%ld, f%ldbc1%s%s %ldbc1%s%s %ld, %ldadd.%s f%ld, f%ld, f%ldsub.%s f%ld, f%ld, f%ldmul.%s f%ld, f%ld, f%lddiv.%s f%ld, f%ld, f%ldmovz.%s f%ld, f%ld, r%ldmovn.%s f%ld, f%ld, r%ldc.%s.%s f%ld, f%ldc.%s.%s %ld, f%ld, f%ldmov%s.%s f%ld, f%ld, %ldsqrt.%s f%ld, f%ldabs.%s f%ld, f%ldmov.%s f%ld, f%ldneg.%s f%ld, f%ldround.l.%s f%ld, f%ldtrunc.l.%s f%ld, f%ldceil.l.%s f%ld, f%ldfloor.l.%s f%ld, f%ldround.w.%s f%ld, f%ldtrunc.w.%s f%ld, f%ldceil.w.%s f%ld, f%ldfloor.w.%s f%ld, f%ldrecip.%s f%ld, f%ldrsqrt.%s f%ld, f%ldcvt.s.%s f%ld, f%ldcvt.d.%s f%ld, f%ldcvt.w.%s f%ld, f%ldcvt.l.%s f%ld, f%ldmadd.%s f%ld, f%ld, f%ld, f%ldmsub.%s f%ld, f%ld, f%ld, f%ldnmadd.%s f%ld, f%ld, f%ld, f%ldnmsub.%s f%ld, f%ld, f%ld, f%ldswxc1 f%ld, r%ld(r%ld)prefx %ld, r%ld(r%ld)lwxc1 f%ld, r%ld(r%ld)beql r%ld, r%ld, %ldbnel r%ld, r%ld, %ldbgtzl r%ld, %ldlb r%ld, %ld(r%ld)lh r%ld, %ld(r%ld)lwl r%ld, %ld(r%ld)lw r%ld, %ld(r%ld)lbu r%ld, %ld(r%ld)lhu r%ld, %ld(r%ld)lwr r%ld, %ld(r%ld)sb r%ld, %ld(r%ld)sh r%ld, %ld(r%ld)swl r%ld, %ld(r%ld)sw r%ld, %ld(r%ld)swr r%ld, %ld(r%ld)cache %ld, %ld(r%ld)lwc%ld r%ld, %ld(r%ld)ll r%ld, %ld(r%ld)lwc1 f%ld, %ld(r%ld)pref %ld, %ld(r%ld)ldc1 f%ld, %ld(r%ld)swc%ld r%ld, %ld(r%ld)sc r%ld, %ld(r%ld)swc1 f%ld, %ld(r%ld)sdc1 f%ld, %ld(r%ld)L
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%s-%d %s:0x%08lx %s 0x%04lx
%s-%d %s:0x%08lx %s 0x%02lx
/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-events.c%s:%d: , event time-from-event - time %ld, delta %ld - event %d, tag 0x%lx, time %ld, handler 0x%lx, data 0x%lx%s%s
current_time == sim_events_time (sd)sim_watch_valid - bad switchn > 0slip > 0events->nr_ticks_to_process != 0events_were_nextevent issued at %ld - tag 0x%lx - handler 0x%lx, data 0x%lx%s%s
events->time_from_event >= events->nr_ticks_to_processevents->queue != NULL,10/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-fpu.csrc->fraction >= IMPLICIT_1src->fraction < IMPLICIT_2(exp == EXPMAX) <= ((fraction & ~IMPLICIT_1) == 0)val.i == packedval == orgs->fraction >= IMPLICIT_1val == if->fraction < IMPLICIT_2f->fraction >= IMPLICIT_1(f->class == sim_fpu_class_number || f->class == sim_fpu_class_denorm) <= (f->fraction < IMPLICIT_2 && f->fraction >= IMPLICIT_1)f->fraction >= IMPLICIT_1 && f->fraction < IMPLICIT_2high < LSBIT64 (((NR_FRAC_GUARD + 1) * 2) - 64)high >= LSBIT64 ((NR_FRAC_GUARD * 2) - 64)high >= IMPLICIT_1 && high < IMPLICIT_2numerator >= denominatorl->sign == r->signy >= IMPLICIT_1 && y < IMPLICIT_4y >= IMPLICIT_1 && y < (IMPLICIT_2 << 1)q >= IMPLICIT_1 && q < IMPLICIT_2-+%s0.*QuietNaN*SignalNaN0.0INF1.*2^%+d%sD%sSNaN%sQNaN%sISI%sIDI%sZDZ%sIMZ%sCVI%sCMP%sSQRT%sX%sO%sU%s/%sRLOAD AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s
STORE AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s
Instruction CACHE operation %d to be coded
Data CACHE operation %d to be coded
PENDING_DRAIN - Mis-match on pending update pointers
Internal function must longjump
load instructionHILO: %s: %s at 0x%08lx too close to MF at 0x%08lx
MTHILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx
OPsdwlps?tfunequeqoltultoleulesfngleseqnglltngelengtsave: aregs=%d causes unpredictable results
hiuinvalid multiplication operand at 0x%08lx
Internal error - bad switch generated
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          1346989464  501   20    100644  164       `
icache.o| |__text__TEXT#1/12           1346989466  501   20    100644  150260    `
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ED$E$$LEED$ED$E$x\EED$ED$E$W\EED$ED$E$6\EED$ED$E$\EoED$ED$E$[ENED$ED$E$[E-ED$ED$E$[EED$ED$E$[EED$ED$E$p[EED$ED$E$O[EED$ED$E$.[EED$ED$E$
[EgED$ED$E$ZEFED$ED$E$ZE%ED$ED$E$ZEED$ED$E$ZEED$ED$E$hZEED$ED$E$GZEED$ED$E$&ZEED$ED$E$ZEbED$ED$E$YEDED$ED$E$YE&UJD$ED$T$E$YEEE$UEE$EE/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-bits.cstart >= stop%s:%d: assertion failed - %sstart <= stopsign_bit < 64/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-n-bits.hshift <= Nsign_bit < N/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-n-endian.hoffset + sizeof_word <= sizeof(unsigned_N)word < (sizeof (unsigned_N) / sizeof_word)(sizeof (unsigned_N) % sizeof_word) == 0/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-core.c(addr & (nr_bytes - 1)) == 0(addr + (nr_bytes - 1)) >= addr!abort || cpu != NULLreadwrite-><-sim-n-core.h:%d: %s-%d %s:0x%08lx %s 0x%08lx%08lx%08lx%08lx
%s-%d %s:0x%08lx %s 0x%08lx%08lx
%s-%d %s:0x%08lx %s 0x%08lx
%s-%d %s:0x%08lx %s 0x%04lx
%s-%d %s:0x%08lx %s 0x%02lx
/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-events.c%s:%d: , event time-from-event - time %ld, delta %ld - event %d, tag 0x%lx, time %ld, handler 0x%lx, data 0x%lx%s%s
current_time == sim_events_time (sd)sim_watch_valid - bad switchn > 0slip > 0events->nr_ticks_to_process != 0events_were_nextevent issued at %ld - tag 0x%lx - handler 0x%lx, data 0x%lx%s%s
events->time_from_event >= events->nr_ticks_to_processevents->queue != NULL,10/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-fpu.csrc->fraction >= IMPLICIT_1src->fraction < IMPLICIT_2(exp == EXPMAX) <= ((fraction & ~IMPLICIT_1) == 0)val.i == packedval == orgs->fraction >= IMPLICIT_1val == if->fraction < IMPLICIT_2f->fraction >= IMPLICIT_1(f->class == sim_fpu_class_number || f->class == sim_fpu_class_denorm) <= (f->fraction < IMPLICIT_2 && f->fraction >= IMPLICIT_1)f->fraction >= IMPLICIT_1 && f->fraction < IMPLICIT_2high < LSBIT64 (((NR_FRAC_GUARD + 1) * 2) - 64)high >= LSBIT64 ((NR_FRAC_GUARD * 2) - 64)high >= IMPLICIT_1 && high < IMPLICIT_2numerator >= denominatorl->sign == r->signy >= IMPLICIT_1 && y < IMPLICIT_4y >= IMPLICIT_1 && y < (IMPLICIT_2 << 1)q >= IMPLICIT_1 && q < IMPLICIT_2-+%s0.*QuietNaN*SignalNaN0.0INF1.*2^%+d%sD%sSNaN%sQNaN%sISI%sIDI%sZDZ%sIMZ%sCVI%sCMP%sSQRT%sX%sO%sU%s/%sRLOAD AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s
STORE AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s
Instruction CACHE operation %d to be coded
Data CACHE operation %d to be coded
PENDING_DRAIN - Mis-match on pending update pointers
Internal function must longjump
load instructionHILO: %s: %s at 0x%08lx too close to MF at 0x%08lx
MTHILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx
OPsdwlps?tfunequeqoltultoleulesfngleseqnglltngelengtsave: aregs=%d causes unpredictable results
hiuinvalid multiplication operand at 0x%08lx
engine.ccurrent_cpu == 0nr_cpus == 1Internal error - bad switch generatedo^
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=u	EEE$9EE$[UHEfEEE#Eu-ED$ED$ED$ED$E$hE$`fEED$ED$ED$ED$ED$$^tEED$D$ED$D$ED$ED$ED$$VE_tMUEPEE	t@ED$D$ED$ED$D$D$fED$E$UVSP[E E}uE	EEE}uaE	dEEEE	t)EED$gD$ED$$PuE$AEt$ ED$ED$T$E$D$ED$D$ED$$P[^UHEEEEEEED$ED$D$D$D$ED$ED$E$EED$E$$EE_tMUEPEE	t@ED$D$ED$ED$D$D$ED$E$EUYEE=u	EEEEEUVDEEEEEEEEED$ED$D$D$D$ED$ED$E$SEED$E$HE$E_tMUEPEE	t@ED$D$ED$ED$D$D$AED$E$D^UYEE=u	EEEEE/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-core.cSTATE_MAGIC (sd) == SIM_MAGIC_NUMBER%s:%d: assertion failed - %stbd->buffer != NULLreadwritecore: %d byte %s to unmapped address 0x%lx at 0x%lx
core: %d byte misaligned %s to address 0x%lx at 0x%lx
sim_core_signal - internal error - bad switch(client == NULL) != (buffer == NULL)(client == NULL) >= (free_buffer != NULL)called on sim_core_map_attach with size zeronext_mapping == NULL || next_mapping->level >= levelmemory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)sim_core_map_attach - processor specific memory map not yet supportedsim_core_attach - internal error - modulo and callback memory conflictsim_core_attach - internal error - modulo %lx not power of twosim_core_attach - internal error - conflicting buffer and attach arguments(addr & (nr_bytes - 1)) == 0(addr + (nr_bytes - 1)) >= addr!abort || cpu != NULLAttempted to enable xor-endian mode when permenantly disabled.-><-sim-n-core.h:%d: %s-%d %s:0x%08lx %s 0x%08lx%08lx%08lx%08lx
/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-n-endian.hoffset + sizeof_word <= sizeof(unsigned_N)word < (sizeof (unsigned_N) / sizeof_word)(sizeof (unsigned_N) % sizeof_word) == 0%s-%d %s:0x%08lx %s 0x%08lx%08lx
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#1/20           1346989455  501   20    100644  172       `
sim-endian.o| |__text__TEXT#1/20           1346989456  501   20    100644  22916     `
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9TT@E$PE@;P%D$E$A[UYEEG=u	EEEEEUS$[EfE=u	EEE$EE$[UEfEEEf	US$[=uEEE$EE$[UEEEUS4[EEEEP=uEUEU4EUEUE$EE$EEUEUEU4[UEfEEUEUEEEEEUUEEEU(EfEE$UE$U8EEEEEUEUE$EE$EEUUEEEnext_event_queue - bad queue/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/../common/sim-events.cSTATE_MAGIC (sd) == SIM_MAGIC_NUMBER%s:%d: assertion failed - %sevents->resume_wallclock == 0events->resume_wallclock != 0events->queue != NULLwhat is past is past!
curr->next == NULL || curr->time_of_event <= curr->next->time_of_eventcurr == NULL || time_of_event < curr->time_of_event%s:%d: , event time-from-event - time %ld, delta %ld - event %d, tag 0x%lx, time %ld, handler 0x%lx, data 0x%lx%s%s
current_time == sim_events_time (sd)event scheduled at %ld - tag 0x%lx - time %ld, handler 0x%lx, data 0x%lx%s%s
sim_events_schedule_after_signal - buffer oveflowsignal scheduled at %ld - tag 0x%lx - time %ld, handler 0x%lx, data 0x%lx
event watching clock at %ld - tag 0x%lx - wallclock %ld, handler 0x%lx, data 0x%lx
sim_events_watch_sim - invalid nr bytessim_events_watch_sim - invalid byte orderevent watching host at %ld - tag 0x%lx - host-addr 0x%lx, 0x%lx..0x%lx, handler 0x%lx, data 0x%lx
sim_events_watch_core - invalid nr bytessim_events_watch_core - invalid byte orderevent/watch descheduled at %ld - tag 0x%lx - time %ld, handler 0x%lx, data 0x%lx%s%s
(events->time_from_event >= 0) == (events->queue != NULL)event/watch descheduled at %ld - tag 0x%lx - not found
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#1/20           1346989460  501   20    100644  13692     `
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#1/20           1346989460  501   20    100644  18724     `
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#1/20           1346989460  501   20    100644  5596      `
sim-utils.o

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#1/20           1346989461  501   20    100644  8276      `
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#1/12           1346989461  501   20    100644  20284     `
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dinero-traceon|offEnable dinero tracingdinero-fileFILEWrite dinero trace to FILEfirmware[idt|pmon|lsipmon|none][@ADDRESS]Emulate ROM monitorboardnone|jmr3904|jmr3904pal|jmr3904debug|bspCustomize simulation for a particular board.info-memoryList configured memory regionsmemory-info/Users/User/ndk-User/src/build/../gdb/gdb-7.3.x/sim/mips/interp.cSTATE_MAGIC (sd) == SIM_MAGIC_NUMBER%s:%d: assertion failed - %s memory region 0x7fff8000,0x8000memory delete %d:0x%lx@%dmemory alias 0x%lx@1,0x%lx%%0x%lx,0x%0xbspmemory alias 0x%lx@1,0x%lx,0x%0xol != NULLmemory region 0x%x,0x%xidt_monitor_base != 0wb+Failed to create file "%s", writing trace information to stderr.
Invalid register width for %d (register store ignored)
Invalid register width for %d (register fetch ignored)
Error: "%s" is not a valid MIPS simulator command.
Invalid address given to the`sim firmware NAME@ADDRESS' command: %s
idtpmonlsipmonnoneThe `sim firmware none' command does not take an `ADDRESS' argument.
Unrecognized name given to the `sim firmware NAME' command: %s
Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.
Invalid return from character readsim_monitor(17): _exit(int reason) to be coded
match != NULLdobxXulscefg%%%%c(null)dobxXu<binary not supported>ll%%%s%ceEfgG%%%d.%d%c%d %s ; width %d ; sim_monitor: unhandled reason = %d, pc = 0x%s
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Warning: ERET when SR[ERL] set not handled yetDelay slot already activated (branch in delay slot?)
Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present
COP2 instruction 0x%08X at PC = 0x%s : No handler present
%08lx%08lx%08lxreadwritemips-core: %d byte %s to unmapped address 0x%lx at 0x%lx
mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx
mips_core_signal - internal error - bad switchcpu != NULLWarning, nested exception triggered (%d)
Warning, nested exception signal (%d then %d)
Warning, resuming but ignoring pending exception signal (%d)
Warning, resuming with mismatched exception signal (%d vs %d)
Warning, ignoring spontanous exception signal (%d)
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#1/20           1346989461  501   20    100644  1372      `
sim-hload.ol __text__TEXT__cstring__TEXT\__pointers__IMPORT
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#1/20           1346989461  501   20    100644  1172      `
sim-stop.o( D__text__TEXTtDL__cstring__TEXTtdPUS4[E|=BBthhEEEE</uE@EEEt
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#1/20           1346989461  501   20    100644  1876      `
sim-resume.o( JDJ__text__TEXTD__cstring__TEXTp$P
US4[E|=BBthEEEE</uE@EEEt
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sim-reason.o( D__text__TEXTD	__cstring__TEXT8D@PUSD[EE|=BBtgEEEE</uE@EEEt
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