1 /* 2 * pci_regs.h 3 * 4 * PCI standard defines 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <mj (at) ucw.cz> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 * 16 * For hypertransport information, please consult the following manuals 17 * from http://www.hypertransport.org 18 * 19 * The Hypertransport I/O Link Specification 20 */ 21 22 #ifndef LINUX_PCI_REGS_H 23 #define LINUX_PCI_REGS_H 24 25 /* 26 * Under PCI, each device has 256 bytes of configuration address space, 27 * of which the first 64 bytes are standardized as follows: 28 */ 29 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 30 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 31 #define PCI_COMMAND 0x04 /* 16 bits */ 32 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 33 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 34 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 35 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 36 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 37 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 38 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 39 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 40 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 41 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 42 #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ 43 44 #define PCI_STATUS 0x06 /* 16 bits */ 45 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 46 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 47 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 48 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 49 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 50 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 51 #define PCI_STATUS_DEVSEL_FAST 0x000 52 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 53 #define PCI_STATUS_DEVSEL_SLOW 0x400 54 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 55 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 56 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 57 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 58 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 59 60 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ 61 #define PCI_REVISION_ID 0x08 /* Revision ID */ 62 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 63 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 64 65 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 66 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 67 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 68 #define PCI_HEADER_TYPE_NORMAL 0 69 #define PCI_HEADER_TYPE_BRIDGE 1 70 #define PCI_HEADER_TYPE_CARDBUS 2 71 72 #define PCI_BIST 0x0f /* 8 bits */ 73 #define PCI_BIST_CODE_MASK 0x0f /* Return result */ 74 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 75 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 76 77 /* 78 * Base addresses specify locations in memory or I/O space. 79 * Decoded size can be determined by writing a value of 80 * 0xffffffff to the register, and reading it back. Only 81 * 1 bits are decoded. 82 */ 83 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 84 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 85 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 86 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 87 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 88 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 89 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 90 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 91 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 92 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 93 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 94 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 95 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 96 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 97 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 98 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 99 /* bit 1 is reserved if address_space = 1 */ 100 101 /* Header type 0 (normal devices) */ 102 #define PCI_CARDBUS_CIS 0x28 103 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 104 #define PCI_SUBSYSTEM_ID 0x2e 105 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 106 #define PCI_ROM_ADDRESS_ENABLE 0x01 107 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 108 109 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 110 111 /* 0x35-0x3b are reserved */ 112 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 113 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 114 #define PCI_MIN_GNT 0x3e /* 8 bits */ 115 #define PCI_MAX_LAT 0x3f /* 8 bits */ 116 117 /* Header type 1 (PCI-to-PCI bridges) */ 118 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 119 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 120 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 121 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 122 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 123 #define PCI_IO_LIMIT 0x1d 124 #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ 125 #define PCI_IO_RANGE_TYPE_16 0x00 126 #define PCI_IO_RANGE_TYPE_32 0x01 127 #define PCI_IO_RANGE_MASK (~0x0fUL) 128 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 129 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 130 #define PCI_MEMORY_LIMIT 0x22 131 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 132 #define PCI_MEMORY_RANGE_MASK (~0x0fUL) 133 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 134 #define PCI_PREF_MEMORY_LIMIT 0x26 135 #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 136 #define PCI_PREF_RANGE_TYPE_32 0x00 137 #define PCI_PREF_RANGE_TYPE_64 0x01 138 #define PCI_PREF_RANGE_MASK (~0x0fUL) 139 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 140 #define PCI_PREF_LIMIT_UPPER32 0x2c 141 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 142 #define PCI_IO_LIMIT_UPPER16 0x32 143 /* 0x34 same as for htype 0 */ 144 /* 0x35-0x3b is reserved */ 145 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 146 /* 0x3c-0x3d are same as for htype 0 */ 147 #define PCI_BRIDGE_CONTROL 0x3e 148 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 149 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 150 #define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */ 151 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 152 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 153 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 154 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 155 156 /* Header type 2 (CardBus bridges) */ 157 #define PCI_CB_CAPABILITY_LIST 0x14 158 /* 0x15 reserved */ 159 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 160 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 161 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 162 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 163 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 164 #define PCI_CB_MEMORY_BASE_0 0x1c 165 #define PCI_CB_MEMORY_LIMIT_0 0x20 166 #define PCI_CB_MEMORY_BASE_1 0x24 167 #define PCI_CB_MEMORY_LIMIT_1 0x28 168 #define PCI_CB_IO_BASE_0 0x2c 169 #define PCI_CB_IO_BASE_0_HI 0x2e 170 #define PCI_CB_IO_LIMIT_0 0x30 171 #define PCI_CB_IO_LIMIT_0_HI 0x32 172 #define PCI_CB_IO_BASE_1 0x34 173 #define PCI_CB_IO_BASE_1_HI 0x36 174 #define PCI_CB_IO_LIMIT_1 0x38 175 #define PCI_CB_IO_LIMIT_1_HI 0x3a 176 #define PCI_CB_IO_RANGE_MASK (~0x03UL) 177 /* 0x3c-0x3d are same as for htype 0 */ 178 #define PCI_CB_BRIDGE_CONTROL 0x3e 179 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 180 #define PCI_CB_BRIDGE_CTL_SERR 0x02 181 #define PCI_CB_BRIDGE_CTL_ISA 0x04 182 #define PCI_CB_BRIDGE_CTL_VGA 0x08 183 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 184 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 185 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 186 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 187 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 188 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 189 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 190 #define PCI_CB_SUBSYSTEM_ID 0x42 191 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 192 /* 0x48-0x7f reserved */ 193 194 /* Capability lists */ 195 196 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 197 #define PCI_CAP_ID_PM 0x01 /* Power Management */ 198 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 199 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 200 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 201 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 202 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 203 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ 204 #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ 205 #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ 206 #define PCI_CAP_ID_DBG 0x0A /* Debug port */ 207 #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ 208 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ 209 #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ 210 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ 211 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 212 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ 213 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 214 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 215 #define PCI_CAP_SIZEOF 4 216 217 /* Power Management Registers */ 218 219 #define PCI_PM_PMC 2 /* PM Capabilities Register */ 220 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 221 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 222 #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ 223 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 224 #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */ 225 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 226 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 227 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 228 #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ 229 #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ 230 #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ 231 #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ 232 #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ 233 #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ 234 #define PCI_PM_CTRL 4 /* PM control and status register */ 235 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 236 #define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */ 237 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 238 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 239 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 240 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 241 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 242 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 243 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 244 #define PCI_PM_DATA_REGISTER 7 /* (??) */ 245 #define PCI_PM_SIZEOF 8 246 247 /* AGP registers */ 248 249 #define PCI_AGP_VERSION 2 /* BCD version number */ 250 #define PCI_AGP_RFU 3 /* Rest of capability flags */ 251 #define PCI_AGP_STATUS 4 /* Status register */ 252 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 253 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 254 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 255 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 256 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 257 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 258 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 259 #define PCI_AGP_COMMAND 8 /* Control register */ 260 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 261 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 262 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 263 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 264 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 265 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 266 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ 267 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ 268 #define PCI_AGP_SIZEOF 12 269 270 /* Vital Product Data */ 271 272 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ 273 #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ 274 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ 275 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */ 276 277 /* Slot Identification */ 278 279 #define PCI_SID_ESR 2 /* Expansion Slot Register */ 280 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 281 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 282 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 283 284 /* Message Signalled Interrupts registers */ 285 286 #define PCI_MSI_FLAGS 2 /* Various flags */ 287 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 288 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 289 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 290 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 291 #define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */ 292 #define PCI_MSI_RFU 3 /* Rest of capability flags */ 293 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 294 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 295 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 296 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 297 #define PCI_MSI_MASK_BIT 16 /* Mask bits register */ 298 299 /* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */ 300 #define PCI_MSIX_FLAGS 2 301 #define PCI_MSIX_FLAGS_QSIZE 0x7FF 302 #define PCI_MSIX_FLAGS_ENABLE (1 << 15) 303 #define PCI_MSIX_FLAGS_MASKALL (1 << 14) 304 #define PCI_MSIX_FLAGS_BIRMASK (7 << 0) 305 #define PCI_MSIX_FLAGS_BITMASK (1 << 0) 306 307 /* CompactPCI Hotswap Register */ 308 309 #define PCI_CHSWP_CSR 2 /* Control and Status Register */ 310 #define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ 311 #define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ 312 #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ 313 #define PCI_CHSWP_LOO 0x08 /* LED On / Off */ 314 #define PCI_CHSWP_PI 0x30 /* Programming Interface */ 315 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ 316 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ 317 318 /* PCI-X registers */ 319 320 #define PCI_X_CMD 2 /* Modes & Features */ 321 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 322 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 323 #define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */ 324 #define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */ 325 #define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */ 326 #define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */ 327 #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ 328 /* Max # of outstanding split transactions */ 329 #define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */ 330 #define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */ 331 #define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */ 332 #define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */ 333 #define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */ 334 #define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */ 335 #define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ 336 #define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ 337 #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ 338 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 339 #define PCI_X_STATUS 4 /* PCI-X capabilities */ 340 #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ 341 #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ 342 #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */ 343 #define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */ 344 #define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */ 345 #define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */ 346 #define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */ 347 #define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */ 348 #define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ 349 #define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ 350 #define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ 351 #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ 352 #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ 353 354 /* PCI Express capability registers */ 355 356 #define PCI_EXP_FLAGS 2 /* Capabilities register */ 357 #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ 358 #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ 359 #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ 360 #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ 361 #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ 362 #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ 363 #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ 364 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ 365 #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ 366 #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ 367 #define PCI_EXP_DEVCAP 4 /* Device capabilities */ 368 #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ 369 #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ 370 #define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ 371 #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ 372 #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ 373 #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ 374 #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ 375 #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ 376 #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ 377 #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ 378 #define PCI_EXP_DEVCTL 8 /* Device Control */ 379 #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ 380 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ 381 #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ 382 #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ 383 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 384 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ 385 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ 386 #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ 387 #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ 388 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ 389 #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ 390 #define PCI_EXP_DEVSTA 10 /* Device Status */ 391 #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */ 392 #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ 393 #define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */ 394 #define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */ 395 #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ 396 #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ 397 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ 398 #define PCI_EXP_LNKCTL 16 /* Link Control */ 399 #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ 400 #define PCI_EXP_LNKSTA 18 /* Link Status */ 401 #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ 402 #define PCI_EXP_SLTCTL 24 /* Slot Control */ 403 #define PCI_EXP_SLTSTA 26 /* Slot Status */ 404 #define PCI_EXP_RTCTL 28 /* Root Control */ 405 #define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */ 406 #define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */ 407 #define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */ 408 #define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */ 409 #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ 410 #define PCI_EXP_RTCAP 30 /* Root Capabilities */ 411 #define PCI_EXP_RTSTA 32 /* Root Status */ 412 413 /* Extended Capabilities (PCI-X 2.0 and Express) */ 414 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 415 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 416 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 417 418 #define PCI_EXT_CAP_ID_ERR 1 419 #define PCI_EXT_CAP_ID_VC 2 420 #define PCI_EXT_CAP_ID_DSN 3 421 #define PCI_EXT_CAP_ID_PWR 4 422 423 /* Advanced Error Reporting */ 424 #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ 425 #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ 426 #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ 427 #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ 428 #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ 429 #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ 430 #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ 431 #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ 432 #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ 433 #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ 434 #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ 435 #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ 436 #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ 437 /* Same bits as above */ 438 #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ 439 /* Same bits as above */ 440 #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ 441 #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ 442 #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ 443 #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ 444 #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ 445 #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ 446 #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ 447 /* Same bits as above */ 448 #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ 449 #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ 450 #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ 451 #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ 452 #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ 453 #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ 454 #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ 455 #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ 456 /* Correctable Err Reporting Enable */ 457 #define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 458 /* Non-fatal Err Reporting Enable */ 459 #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 460 /* Fatal Err Reporting Enable */ 461 #define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 462 #define PCI_ERR_ROOT_STATUS 48 463 #define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ 464 /* Multi ERR_COR Received */ 465 #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 466 /* ERR_FATAL/NONFATAL Recevied */ 467 #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 468 /* Multi ERR_FATAL/NONFATAL Recevied */ 469 #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 470 #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */ 471 #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ 472 #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ 473 #define PCI_ERR_ROOT_COR_SRC 52 474 #define PCI_ERR_ROOT_SRC 54 475 476 /* Virtual Channel */ 477 #define PCI_VC_PORT_REG1 4 478 #define PCI_VC_PORT_REG2 8 479 #define PCI_VC_PORT_CTRL 12 480 #define PCI_VC_PORT_STATUS 14 481 #define PCI_VC_RES_CAP 16 482 #define PCI_VC_RES_CTRL 20 483 #define PCI_VC_RES_STATUS 26 484 485 /* Power Budgeting */ 486 #define PCI_PWR_DSR 4 /* Data Select Register */ 487 #define PCI_PWR_DATA 8 /* Data Register */ 488 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ 489 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ 490 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ 491 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ 492 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ 493 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ 494 #define PCI_PWR_CAP 12 /* Capability */ 495 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ 496 497 /* 498 * Hypertransport sub capability types 499 * 500 * Unfortunately there are both 3 bit and 5 bit capability types defined 501 * in the HT spec, catering for that is a little messy. You probably don't 502 * want to use these directly, just use pci_find_ht_capability() and it 503 * will do the right thing for you. 504 */ 505 #define HT_3BIT_CAP_MASK 0xE0 506 #define HT_CAPTYPE_SLAVE 0x00 /* Slave/Primary link configuration */ 507 #define HT_CAPTYPE_HOST 0x20 /* Host/Secondary link configuration */ 508 509 #define HT_5BIT_CAP_MASK 0xF8 510 #define HT_CAPTYPE_IRQ 0x80 /* IRQ Configuration */ 511 #define HT_CAPTYPE_REMAPPING_40 0xA0 /* 40 bit address remapping */ 512 #define HT_CAPTYPE_REMAPPING_64 0xA2 /* 64 bit address remapping */ 513 #define HT_CAPTYPE_UNITID_CLUMP 0x90 /* Unit ID clumping */ 514 #define HT_CAPTYPE_EXTCONF 0x98 /* Extended Configuration Space Access */ 515 #define HT_CAPTYPE_MSI_MAPPING 0xA8 /* MSI Mapping Capability */ 516 #define HT_MSI_FLAGS 0x02 /* Offset to flags */ 517 #define HT_MSI_FLAGS_ENABLE 0x1 /* Mapping enable */ 518 #define HT_MSI_FLAGS_FIXED 0x2 /* Fixed mapping only */ 519 #define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL /* Fixed addr */ 520 #define HT_MSI_ADDR_LO 0x04 /* Offset to low addr bits */ 521 #define HT_MSI_ADDR_LO_MASK 0xFFF00000 /* Low address bit mask */ 522 #define HT_MSI_ADDR_HI 0x08 /* Offset to high addr bits */ 523 #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */ 524 #define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */ 525 #define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ 526 #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */ 527 #define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */ 528 529 530 #endif /* LINUX_PCI_REGS_H */ 531
